reg-ccu.h

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2013-2025
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * 
 * original from bsp uboot defines
 */
 
#ifndef __SUN8IW22_REG_CCU_H__
#define __SUN8IW22_REG_CCU_H__
 
#include <reg-ncat.h>
 
#define PLL_PERI0_CTRL_REG 0x000000a0//PLL_PERI0 Control Register
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK (0x00700000)
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK (0x00070000)
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK (0x0000001c)
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK (0x00000002)
 
#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8//PLL_PERI0 Pattern0 Control Register
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00080000)
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)
 
#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac//PLL_PERI0 Pattern1 Control Register
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)
 
#define PLL_PERI0_BIAS_REG 0x000000b0//PLL_PERI0 Bias Register
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)
 
#define PLL_PERI1_CTRL_REG 0x000000c0//PLL_PERI1 Control Register
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK (0x00700000)
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK (0x00070000)
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK (0x0000001c)
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK (0x00000002)
 
#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8//PLL_PERI1 Pattern0 Control Register
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00080000)
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)
 
#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc//PLL_PERI1 Pattern1 Control Register
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)
 
#define PLL_PERI1_BIAS_REG 0x000000d0//PLL_PERI1 Bias Register
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)
 
#define PLL_VIDEO0_CTRL_REG 0x00000120//PLL_VIDEO0 Control Register
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK (0x00700000)
#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK (0x00070000)
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK (0x00000002)
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128//PLL_VIDEO0 Pattern0 Control Register
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00080000)
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)
 
#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c//PLL_VIDEO0 Pattern1 Control Register
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)
 
#define PLL_VIDEO0_BIAS_REG 0x00000130//PLL_VIDEO0 Bias Register
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)
 
#define PLL_AUDIO0_CTRL_REG 0x00000260//PLL_AUDIO0 Control Register
#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET 16
#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK (0x003f0000)
#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK (0x00000002)
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268//PLL_AUDIO0 Pattern0 Control Register
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00080000)
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)
 
#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c//PLL_AUDIO0 Pattern1 Control Register
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)
 
#define PLL_AUDIO0_BIAS_REG 0x00000270//PLL_AUDIO0 Bias Register
#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)
 
#define PLL_CPU_CTRL_REG 0x00000340//PLL_CPU Control Register
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_OFFSET 31
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_DISABLE 0b0
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_ENABLE 0b1
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_CPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_CPU_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_CPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_CPU_CTRL_REG_PLL_UPDATE_OFFSET 26
#define PLL_CPU_CTRL_REG_PLL_UPDATE_CLEAR_MASK (0x04000000)
#define PLL_CPU_CTRL_REG_PLL_M0_OFFSET 20
#define PLL_CPU_CTRL_REG_PLL_M0_CLEAR_MASK (0x00300000)
#define PLL_CPU_CTRL_REG_PLL_P_OFFSET 16
#define PLL_CPU_CTRL_REG_PLL_P_CLEAR_MASK (0x00070000)
#define PLL_CPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_CPU_CTRL_REG_PLL_M1_OFFSET 0
#define PLL_CPU_CTRL_REG_PLL_M1_CLEAR_MASK (0x0000000f)
 
#define PLL_CPU_PAT0_CTRL_REG 0x00000344//PLL_CPU Pattern0 Control Register
#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_SDM 0b00
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_1_8_BIT 0b01
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_2_8_BIT 0b10
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_3_8_BIT 0b11
#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 17
#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ffe0000)
#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)
 
#define PLL_CPU_PAT1_CTRL_REG 0x00000348//PLL_CPU Pattern1 Control Register
#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_OFFSET 22
#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_CLEAR_MASK (0xffc00000)
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_OFFSET 20
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_CLEAR_MASK 0x00100000
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_UP 0b0
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_DOWM 0b1
#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 18
#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x00040000)
#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 17
#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00020000)
#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)
 
#define PLL_CPU_BIAS_REG 0x0000034c//PLL_CPU Bias Register
#define PLL_CPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CPU_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)
 
#define PLL_CPU_TUN1_REG 0x00000350//PLL_CPU Tuning1 Control Register
#define PLL_CPU_TUN1_REG_PLL_SDM_EN_OFFSET 31
#define PLL_CPU_TUN1_REG_PLL_SDM_EN_CLEAR_MASK (0x80000000)
 
#define PLL_CPU_SSC_REG 0x00000354//PLL_CPU SSC Register
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_OFFSET 31
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CLEAR_MASK (0x80000000)
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_NORMAL_MODE 0b0
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CONTINUOUSLY_FREQUENCY_SCALE 0b1
#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_OFFSET 30
#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_CLEAR_MASK (0x40000000)
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_OFFSET 29
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_CLEAR_MASK (0x20000000)
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_REF_CLK 0b0
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_PLL_CLK_SDM 0b1
#define PLL_CPU_SSC_REG_PLL_SSC_OFFSET 12
#define PLL_CPU_SSC_REG_PLL_SSC_CLEAR_MASK (0x1ffff000)
#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_OFFSET 4
#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_CLEAR_MASK (0x00000070)
#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_4_IS_BASED_ON_24M_CLOCK_THEN_THE_DEFAULT_PLL_PHASE_COMPENSATE_IS_3_24000000_S (0b6)
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_OFFSET 0
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_CLEAR_MASK (0x0000000f)
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00439MHZ_US_576_2_17 0b0000
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00879MHZ_US_576_2_16 0b0001
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_01758MHZ_US_576_2_15 0b0010
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_03516MHZ_US_576_2_14 0b0011
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_07031MHZ_US_576_2_13 0b0100
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_14062MHZ_US_576_2_12 0b0101
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_28125MHZ_US_576_2_11 0b0110
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_56250MHZ_US_576_2_10 0b0111
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_1_12500MHZ_US_576_2_9 0b1000
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_2_25000MHZ_US_576_2_8 0b1001
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_4_50000MHZ_US_576_2_7 0b1010
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_9_00000MHZ_US_576_2_6 0b1011
 
#define PLL_CPU_ECHO_REG 0x00000358//PLL_CPU Echo Register
#define PLL_CPU_ECHO_REG_PLL_CPU_EN_ECHO_OFFSET 31
#define PLL_CPU_ECHO_REG_PLL_CPU_EN_ECHO_CLEAR_MASK (0x80000000)
#define PLL_CPU_ECHO_REG_PLL_CPU_EN_ECHO_DISABLE 0b0
#define PLL_CPU_ECHO_REG_PLL_CPU_EN_ECHO_ENABLE 0b1
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ENABLE_ECHO_OFFSET 29
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ENABLE_ECHO_CLEAR_MASK (0x20000000)
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ENABLE_ECHO_DISABLE 0b0
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ENABLE_ECHO_ENABLE 0b1
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ECHO_OFFSET 28
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ECHO_CLEAR_MASK 0x10000000
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ECHO_UNLOCKED 0b0
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_ECHO_LOCKED_IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_CPU_ECHO_REG_PLL_CPU_OUTPUT_GATE_ECHO_OFFSET 27
#define PLL_CPU_ECHO_REG_PLL_CPU_OUTPUT_GATE_ECHO_CLEAR_MASK (0x08000000)
#define PLL_CPU_ECHO_REG_PLL_CPU_OUTPUT_GATE_ECHO_DISABLE 0b0
#define PLL_CPU_ECHO_REG_PLL_CPU_OUTPUT_GATE_ECHO_ENABLE 0b1
#define PLL_CPU_ECHO_REG_PLL_CPU_UPDATE_ECHO_OFFSET 26
#define PLL_CPU_ECHO_REG_PLL_CPU_UPDATE_ECHO_CLEAR_MASK (0x04000000)
#define PLL_CPU_ECHO_REG_PLL_CPU_M0_ECHO_OFFSET 20
#define PLL_CPU_ECHO_REG_PLL_CPU_M0_ECHO_CLEAR_MASK (0x00300000)
#define PLL_CPU_ECHO_REG_PLL_CPU_P_ECHO_OFFSET 16
#define PLL_CPU_ECHO_REG_PLL_CPU_P_ECHO_CLEAR_MASK (0x00070000)
#define PLL_CPU_ECHO_REG_PLL_CPU_N_SDM_PLLCFG_ECHO_OFFSET 8
#define PLL_CPU_ECHO_REG_PLL_CPU_N_SDM_PLLCFG_ECHO_CLEAR_MASK (0x0000ff00)
#define PLL_CPU_ECHO_REG_PLL_CPU_UNLOCK_MDSEL_ECHO_OFFSET 6
#define PLL_CPU_ECHO_REG_PLL_CPU_UNLOCK_MDSEL_ECHO_CLEAR_MASK (0x000000c0)
#define PLL_CPU_ECHO_REG_PLL_CPU_UNLOCK_MDSEL_ECHO_21_29_CLOCK_CYCLES 0b00
#define PLL_CPU_ECHO_REG_PLL_CPU_UNLOCK_MDSEL_ECHO_22_28_CLOCK_CYCLES 0b01
#define PLL_CPU_ECHO_REG_PLL_CPU_UNLOCK_MDSEL_ECHO_20_30_CLOCK_CYCLES 0b10
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_MDSEL_ECHO_OFFSET 5
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_MDSEL_ECHO_CLEAR_MASK (0x00000020)
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_MDSEL_ECHO_24_26_CLOCK_CYCLES 0b0
#define PLL_CPU_ECHO_REG_PLL_CPU_LOCK_MDSEL_ECHO_23_27_CLOCK_CYCLES 0b1
#define PLL_CPU_ECHO_REG_PLL_CPU_M1_ECHO_OFFSET 0
#define PLL_CPU_ECHO_REG_PLL_CPU_M1_ECHO_CLEAR_MASK (0x0000000f)
 
#define AHB_CLK_REG 0x00000500//AHB Clock Register
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define AHB_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define AHB_CLK_REG_FACTOR_M_OFFSET 0
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define APB0_CLK_REG 0x00000510//APB0 Clock Register
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define APB0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB0_CLK_REG_FACTOR_M_OFFSET 0
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define APB1_CLK_REG 0x00000518//APB1 Clock Register
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define APB1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB1_CLK_REG_FACTOR_M_OFFSET 0
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define APB_UART_CLK_REG 0x00000538//APB_UART Clock Register
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b001
#define APB_UART_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b010
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100
#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define MBUS_CLK_REG 0x00000588//MBUS Clock Register
#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK (0x80000000)
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1
#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28
#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK 0x10000000
#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0
#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1
#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27
#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK (0x08000000)
#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0
#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1
#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24
#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK (0x07000000)
#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_24M_CLK 0b000
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b001
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b010
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_300M 0b011
#define MBUS_CLK_REG_MBUS_CLK_SEL_HDR_CLK 0b100
#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0
#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK (0x0000001f)
 
#define AHB_MAT_CLK_GATE_EN_REG 0x000005c0//AHB Master Clock Gate Enable Register
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK (0x80000000)
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK (0x20000000)
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_OFFSET 28
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SPIF_AHB_GATE_SW_CFG_OFFSET 22
#define AHB_MAT_CLK_GATE_EN_REG_SPIF_AHB_GATE_SW_CFG_CLEAR_MASK (0x00400000)
#define AHB_MAT_CLK_GATE_EN_REG_SPIF_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SPIF_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_USB2P0_SYS_AHB_GATE_SW_CFG_OFFSET 16
#define AHB_MAT_CLK_GATE_EN_REG_USB2P0_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define AHB_MAT_CLK_GATE_EN_REG_USB2P0_SYS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_USB2P0_SYS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_GMAC2_AHB_GATE_SW_CFG_OFFSET 15
#define AHB_MAT_CLK_GATE_EN_REG_GMAC2_AHB_GATE_SW_CFG_CLEAR_MASK (0x00008000)
#define AHB_MAT_CLK_GATE_EN_REG_GMAC2_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_GMAC2_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 14
#define AHB_MAT_CLK_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK (0x00004000)
#define AHB_MAT_CLK_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 13
#define AHB_MAT_CLK_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00002000)
#define AHB_MAT_CLK_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_OFFSET 12
#define AHB_MAT_CLK_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00001000
#define AHB_MAT_CLK_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000080)
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000040)
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000020)
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_OFFSET 3
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000008)
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_OFFSET 2
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000004)
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_ENABLE 0b1
 
#define PERI_MAT_CLK_GATE_EN_REG 0x000005d0//PERI Master Clock Gate Enable Register
#define PERI_MAT_CLK_GATE_EN_REG_PERI_APB0_GATE_SW_CFG_OFFSET 16
#define PERI_MAT_CLK_GATE_EN_REG_PERI_APB0_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI_MAT_CLK_GATE_EN_REG_PERI_APB0_GATE_SW_CFG_DISABLE 0b0
#define PERI_MAT_CLK_GATE_EN_REG_PERI_APB0_GATE_SW_CFG_ENABLE 0b1
#define PERI_MAT_CLK_GATE_EN_REG_PERI_AHB_GATE_SW_CFG_OFFSET 0
#define PERI_MAT_CLK_GATE_EN_REG_PERI_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000001
#define PERI_MAT_CLK_GATE_EN_REG_PERI_AHB_GATE_SW_CFG_DISABLE 0b0
#define PERI_MAT_CLK_GATE_EN_REG_PERI_AHB_GATE_SW_CFG_ENABLE 0b1
 
#define MBUS_CLK_GATE_EN_REG 0x000005e0//MBUS Clock Gate Enable Register
#define MBUS_CLK_GATE_EN_REG_CAN_MBUS_CLK_EN_OFFSET 17
#define MBUS_CLK_GATE_EN_REG_CAN_MBUS_CLK_EN_CLEAR_MASK (0x00020000)
#define MBUS_CLK_GATE_EN_REG_CAN_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_CAN_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_GMAC2_MBUS_CLK_EN_OFFSET 13
#define MBUS_CLK_GATE_EN_REG_GMAC2_MBUS_CLK_EN_CLEAR_MASK (0x00002000)
#define MBUS_CLK_GATE_EN_REG_GMAC2_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_GMAC2_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_GMAC1_MBUS_CLK_EN_OFFSET 12
#define MBUS_CLK_GATE_EN_REG_GMAC1_MBUS_CLK_EN_CLEAR_MASK 0x00001000
#define MBUS_CLK_GATE_EN_REG_GMAC1_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_GMAC1_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_GMAC0_MBUS_CLK_EN_OFFSET 11
#define MBUS_CLK_GATE_EN_REG_GMAC0_MBUS_CLK_EN_CLEAR_MASK (0x00000800)
#define MBUS_CLK_GATE_EN_REG_GMAC0_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_GMAC0_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_OFFSET 9
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_CLEAR_MASK (0x00000200)
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_OFFSET 8
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_CLEAR_MASK 0x00000100
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_DMA1_MBUS_CLK_EN_OFFSET 3
#define MBUS_CLK_GATE_EN_REG_DMA1_MBUS_CLK_EN_CLEAR_MASK (0x00000008)
#define MBUS_CLK_GATE_EN_REG_DMA1_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_DMA1_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_CE_SYS_MBUS_CLK_EN_OFFSET 2
#define MBUS_CLK_GATE_EN_REG_CE_SYS_MBUS_CLK_EN_CLEAR_MASK (0x00000004)
#define MBUS_CLK_GATE_EN_REG_CE_SYS_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_CE_SYS_MBUS_CLK_EN_SECURE_DEBUG 0b1
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_OFFSET 0
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_CLEAR_MASK 0x00000001
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_PASS 0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG 0x000005e4//MBUS Master Clock Gate Enable Register
#define MBUS_MAT_CLK_GATE_EN_REG_DMA1_MBUS_GATE_SW_CFG_OFFSET 29
#define MBUS_MAT_CLK_GATE_EN_REG_DMA1_MBUS_GATE_SW_CFG_CLEAR_MASK (0x20000000)
#define MBUS_MAT_CLK_GATE_EN_REG_DMA1_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_DMA1_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_OFFSET 28
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_LBC_MBUS_GATE_SW_CFG_OFFSET 27
#define MBUS_MAT_CLK_GATE_EN_REG_LBC_MBUS_GATE_SW_CFG_CLEAR_MASK (0x08000000)
#define MBUS_MAT_CLK_GATE_EN_REG_LBC_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_LBC_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_MBUS_GATE_SW_CFG_OFFSET 23
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00800000)
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_MCU_SYS_MBUS_GATE_SW_CFG_OFFSET 21
#define MBUS_MAT_CLK_GATE_EN_REG_MCU_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00200000)
#define MBUS_MAT_CLK_GATE_EN_REG_MCU_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_MCU_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_OFFSET 20
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_CAN_MBUS_GATE_SW_CFG_OFFSET 19
#define MBUS_MAT_CLK_GATE_EN_REG_CAN_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00080000)
#define MBUS_MAT_CLK_GATE_EN_REG_CAN_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_CAN_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_MBUS_GATE_SW_CFG_OFFSET 18
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00040000)
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC2_MBUS_GATE_SW_CFG_OFFSET 14
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC2_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00004000)
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC2_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC2_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC1_MBUS_GATE_SW_CFG_OFFSET 13
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC1_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00002000)
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC1_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC1_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC0_MBUS_GATE_SW_CFG_OFFSET 12
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00001000
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC0_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC_MBUS_GATE_SW_CFG_OFFSET 11
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000800)
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_GMAC_MBUS_GATE_SW_CFG_ENABLE 0b1
 
#define AHB_MAT_CLK_AUTO_GATE_EN_REG 0x000005f0//AHB Master Clock Auto Gate Enable Register
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SPIF_AHB_AUTO_GATE_EN_OFFSET 22
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SPIF_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00400000)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SPIF_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SPIF_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_USB2P0_SYS_AHB_AUTO_GATE_EN_OFFSET 16
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_USB2P0_SYS_AHB_AUTO_GATE_EN_CLEAR_MASK 0x00010000
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_USB2P0_SYS_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_USB2P0_SYS_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_AHB_AUTO_GATE_EN_OFFSET 15
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00008000)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_AHB_AUTO_GATE_EN_OFFSET 14
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00004000)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_AHB_AUTO_GATE_EN_OFFSET 13
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00002000)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_AHB_AUTO_GATE_EN_OFFSET 12
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_AHB_AUTO_GATE_EN_CLEAR_MASK 0x00001000
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC2_AHB_AUTO_GATE_EN_OFFSET 7
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC2_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC2_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC2_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC1_AHB_AUTO_GATE_EN_OFFSET 6
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC1_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC1_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC1_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC0_AHB_AUTO_GATE_EN_OFFSET 5
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC0_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00000020)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC0_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_SMHC0_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_AHB_AUTO_GATE_EN_OFFSET 3
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_AHB_AUTO_GATE_EN_AUTO 0b1
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_AHB_AUTO_GATE_EN_OFFSET 2
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_AHB_AUTO_GATE_EN_CLEAR_MASK (0x00000004)
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_AHB_AUTO_GATE_EN_NO_AUTO 0b0
#define AHB_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_AHB_AUTO_GATE_EN_AUTO 0b1
 
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG 0x000005f4//MBUS Master Clock Auto Gate Enable Register
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA1_MBUS_AUTO_GATE_EN_OFFSET 29
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA1_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x20000000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA1_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA1_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA0_MBUS_AUTO_GATE_EN_OFFSET 28
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA0_MBUS_AUTO_GATE_EN_CLEAR_MASK 0x10000000
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA0_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_DMA0_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_LBC_MBUS_AUTO_GATE_EN_OFFSET 27
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_LBC_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x08000000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_LBC_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_LBC_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_MBUS_AUTO_GATE_EN_OFFSET 23
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00800000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_OUT0_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_MBUS_AUTO_GATE_EN_OFFSET 21
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00200000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_MCU_SYS_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_MBUS_AUTO_GATE_EN_OFFSET 20
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_MBUS_AUTO_GATE_EN_CLEAR_MASK 0x00100000
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_VIDEO_IN_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CAN_MBUS_AUTO_GATE_EN_OFFSET 19
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CAN_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00080000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CAN_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CAN_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CE_SYS_MBUS_AUTO_GATE_EN_OFFSET 18
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CE_SYS_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00040000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CE_SYS_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_CE_SYS_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_MBUS_AUTO_GATE_EN_OFFSET 14
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00004000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC2_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_MBUS_AUTO_GATE_EN_OFFSET 13
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00002000)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC1_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_MBUS_AUTO_GATE_EN_OFFSET 12
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_MBUS_AUTO_GATE_EN_CLEAR_MASK 0x00001000
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC0_MBUS_AUTO_GATE_EN_AUTO 0b1
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC_MBUS_AUTO_GATE_EN_OFFSET 11
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC_MBUS_AUTO_GATE_EN_CLEAR_MASK (0x00000800)
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC_MBUS_AUTO_GATE_EN_NO_AUTO 0b0
#define MBUS_MAT_CLK_AUTO_GATE_EN_REG_GMAC_MBUS_AUTO_GATE_EN_AUTO 0b1
 
#define AHB_MAT_CLK_GATE_STAT_REG 0x000005f8//AHB Master Clock Gate Status Register
#define AHB_MAT_CLK_GATE_STAT_REG_SPIF_AHB_GATE_STAT_OFFSET 22
#define AHB_MAT_CLK_GATE_STAT_REG_SPIF_AHB_GATE_STAT_CLEAR_MASK (0x00400000)
#define AHB_MAT_CLK_GATE_STAT_REG_SPIF_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_SPIF_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_USB2P0_SYS_GATE_STAT_OFFSET 16
#define AHB_MAT_CLK_GATE_STAT_REG_USB2P0_SYS_GATE_STAT_CLEAR_MASK 0x00010000
#define AHB_MAT_CLK_GATE_STAT_REG_USB2P0_SYS_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_USB2P0_SYS_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC2_AHB_GATE_STAT_OFFSET 15
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC2_AHB_GATE_STAT_CLEAR_MASK (0x00008000)
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC2_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC2_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC1_AHB_GATE_STAT_OFFSET 14
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC1_AHB_GATE_STAT_CLEAR_MASK (0x00004000)
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC1_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC1_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC0_AHB_GATE_STAT_OFFSET 13
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC0_AHB_GATE_STAT_CLEAR_MASK (0x00002000)
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC0_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_GMAC0_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_MCU_SYS_AHB_GATE_STAT_OFFSET 12
#define AHB_MAT_CLK_GATE_STAT_REG_MCU_SYS_AHB_GATE_STAT_CLEAR_MASK 0x00001000
#define AHB_MAT_CLK_GATE_STAT_REG_MCU_SYS_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_MCU_SYS_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC2_AHB_GATE_STAT_OFFSET 7
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC2_AHB_GATE_STAT_CLEAR_MASK (0x00000080)
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC2_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC2_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC1_AHB_GATE_STAT_OFFSET 6
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC1_AHB_GATE_STAT_CLEAR_MASK (0x00000040)
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC1_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC1_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC0_AHB_GATE_STAT_OFFSET 5
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC0_AHB_GATE_STAT_CLEAR_MASK (0x00000020)
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC0_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_SMHC0_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_AHB_GATE_STAT_OFFSET 3
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_AHB_GATE_STAT_CLEAR_MASK (0x00000008)
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_AHB_GATE_STAT_ENABLE 0b1
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_IN_AHB_GATE_STAT_OFFSET 2
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_IN_AHB_GATE_STAT_CLEAR_MASK (0x00000004)
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_IN_AHB_GATE_STAT_DISABLE 0b0
#define AHB_MAT_CLK_GATE_STAT_REG_VIDEO_IN_AHB_GATE_STAT_ENABLE 0b1
 
#define MBUS_MAT_CLK_GATE_STAT_REG 0x000005fc//MBUS Master Clock Gate Status Register
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA1_MBUS_GATE_STAT_OFFSET 29
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA1_MBUS_GATE_STAT_CLEAR_MASK (0x20000000)
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA1_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA1_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA0_MBUS_GATE_STAT_OFFSET 28
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA0_MBUS_GATE_STAT_CLEAR_MASK 0x10000000
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA0_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_DMA0_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_LBC_MBUS_GATE_STAT_OFFSET 27
#define MBUS_MAT_CLK_GATE_STAT_REG_LBC_MBUS_GATE_STAT_CLEAR_MASK (0x08000000)
#define MBUS_MAT_CLK_GATE_STAT_REG_LBC_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_LBC_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_MBUS_GATE_STAT_OFFSET 23
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_MBUS_GATE_STAT_CLEAR_MASK (0x00800000)
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_OUT0_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_MCU_SYS_MBUS_GATE_STAT_OFFSET 21
#define MBUS_MAT_CLK_GATE_STAT_REG_MCU_SYS_MBUS_GATE_STAT_CLEAR_MASK (0x00200000)
#define MBUS_MAT_CLK_GATE_STAT_REG_MCU_SYS_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_MCU_SYS_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_IN_MBUS_GATE_STAT_OFFSET 20
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_IN_MBUS_GATE_STAT_CLEAR_MASK 0x00100000
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_IN_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_VIDEO_IN_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_CAN_MBUS_GATE_STAT_OFFSET 19
#define MBUS_MAT_CLK_GATE_STAT_REG_CAN_MBUS_GATE_STAT_CLEAR_MASK (0x00080000)
#define MBUS_MAT_CLK_GATE_STAT_REG_CAN_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_CAN_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_CE_SYS_MBUS_GATE_STAT_OFFSET 18
#define MBUS_MAT_CLK_GATE_STAT_REG_CE_SYS_MBUS_GATE_STAT_CLEAR_MASK (0x00040000)
#define MBUS_MAT_CLK_GATE_STAT_REG_CE_SYS_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_CE_SYS_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC2_MBUS_GATE_STAT_OFFSET 14
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC2_MBUS_GATE_STAT_CLEAR_MASK (0x00004000)
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC2_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC2_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC1_MBUS_GATE_STAT_OFFSET 13
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC1_MBUS_GATE_STAT_CLEAR_MASK (0x00002000)
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC1_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC1_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC0_MBUS_GATE_STAT_OFFSET 12
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC0_MBUS_GATE_STAT_CLEAR_MASK 0x00001000
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC0_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC0_MBUS_GATE_STAT_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC_MBUS_GATE_STAT_OFFSET 11
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC_MBUS_GATE_STAT_CLEAR_MASK (0x00000800)
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC_MBUS_GATE_STAT_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_STAT_REG_GMAC_MBUS_GATE_STAT_ENABLE 0b1
 
#define DMA0_GAR_REG 0x00000704//DMA0 Gating And Reset Register
#define DMA0_GAR_REG_DMA0_RST_N_OFFSET 16
#define DMA0_GAR_REG_DMA0_RST_N_CLEAR_MASK 0x00010000
#define DMA0_GAR_REG_DMA0_RST_N_ASSERT 0b0
#define DMA0_GAR_REG_DMA0_RST_N_DE_ASSERT 0b1
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_OFFSET 0
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_MASK 0x0
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_PASS 0b1
 
#define DMA1_GAR_REG 0x0000070c//DMA1 Gating And Reset Register
#define DMA1_GAR_REG_DMA1_RST_N_OFFSET 16
#define DMA1_GAR_REG_DMA1_RST_N_CLEAR_MASK 0x00010000
#define DMA1_GAR_REG_DMA1_RST_N_ASSERT 0b0
#define DMA1_GAR_REG_DMA1_RST_N_DE_ASSERT 0b1
#define DMA1_GAR_REG_DMA1_AHB_CLK_EN_OFFSET 0
#define DMA1_GAR_REG_DMA1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DMA1_GAR_REG_DMA1_AHB_CLK_EN_MASK 0x0
#define DMA1_GAR_REG_DMA1_AHB_CLK_EN_PASS 0b1
 
#define SPINLOCK_GAR_REG 0x00000724//SPINLOCK Gating And Reset Register
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_OFFSET 16
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_CLEAR_MASK 0x00010000
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_ASSERT 0b0
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_DE_ASSERT 0b1
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_OFFSET 0
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_MASK 0x0
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CPUX_GAR_REG 0x00000744//MSGBOX_CPUX Gating And Reset Register
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_OFFSET 16
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_ASSERT 0b0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_DE_ASSERT 0b1
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CORE0_GAR_REG 0x0000074c//MSGBOX_CORE0 Gating And Reset Register
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_RST_N_OFFSET 16
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_RST_N_ASSERT 0b0
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_RST_N_DE_ASSERT 0b1
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CORE0_GAR_REG_MSGBOX_CORE0_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CORE1_GAR_REG 0x00000754//MSGBOX_CORE1 Gating And Reset Register
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_RST_N_OFFSET 16
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_RST_N_ASSERT 0b0
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_RST_N_DE_ASSERT 0b1
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CORE1_GAR_REG_MSGBOX_CORE1_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CORE2_GAR_REG 0x0000075c//MSGBOX_CORE2 Gating And Reset Register
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_RST_N_OFFSET 16
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_RST_N_ASSERT 0b0
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_RST_N_DE_ASSERT 0b1
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CORE2_GAR_REG_MSGBOX_CORE2_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CORE3_GAR_REG 0x00000764//MSGBOX_CORE3 Gating And Reset Register
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_RST_N_OFFSET 16
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_RST_N_ASSERT 0b0
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_RST_N_DE_ASSERT 0b1
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CORE3_GAR_REG_MSGBOX_CORE3_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_RV_GAR_REG 0x0000076c//MSGBOX_RISCV Gating And Reset Register
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_RST_N_OFFSET 16
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_RST_N_ASSERT 0b0
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_RST_N_DE_ASSERT 0b1
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_AHB_CLK_EN_OFFSET 0
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_AHB_CLK_EN_MASK 0x0
#define MSGBOX_RV_GAR_REG_MSGBOX_RV_AHB_CLK_EN_PASS 0b1
 
#define PWM0_GAR_REG 0x00000784//PWM0 Gating And Reset Register
#define PWM0_GAR_REG_PWM0_RST_N_OFFSET 16
#define PWM0_GAR_REG_PWM0_RST_N_CLEAR_MASK 0x00010000
#define PWM0_GAR_REG_PWM0_RST_N_ASSERT 0b0
#define PWM0_GAR_REG_PWM0_RST_N_DE_ASSERT 0b1
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_OFFSET 0
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_MASK 0x0
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_PASS 0b1
 
#define PWM1_GAR_REG 0x0000078c//PWM1 Gating And Reset Register
#define PWM1_GAR_REG_PWM1_RST_N_OFFSET 16
#define PWM1_GAR_REG_PWM1_RST_N_CLEAR_MASK 0x00010000
#define PWM1_GAR_REG_PWM1_RST_N_ASSERT 0b0
#define PWM1_GAR_REG_PWM1_RST_N_DE_ASSERT 0b1
#define PWM1_GAR_REG_PWM1_APB_CLK_EN_OFFSET 0
#define PWM1_GAR_REG_PWM1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWM1_GAR_REG_PWM1_APB_CLK_EN_MASK 0x0
#define PWM1_GAR_REG_PWM1_APB_CLK_EN_PASS 0b1
 
#define PWM2_GAR_REG 0x00000794//PWM2 Gating And Reset Register
#define PWM2_GAR_REG_PWM2_RST_N_OFFSET 16
#define PWM2_GAR_REG_PWM2_RST_N_CLEAR_MASK 0x00010000
#define PWM2_GAR_REG_PWM2_RST_N_ASSERT 0b0
#define PWM2_GAR_REG_PWM2_RST_N_DE_ASSERT 0b1
#define PWM2_GAR_REG_PWM2_APB_CLK_EN_OFFSET 0
#define PWM2_GAR_REG_PWM2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWM2_GAR_REG_PWM2_APB_CLK_EN_MASK 0x0
#define PWM2_GAR_REG_PWM2_APB_CLK_EN_PASS 0b1
 
#define DCU_GAR_REG 0x000007a4//DCU Gating And Reset Register
#define DCU_GAR_REG_DCU_RST_N_OFFSET 16
#define DCU_GAR_REG_DCU_RST_N_CLEAR_MASK 0x00010000
#define DCU_GAR_REG_DCU_RST_N_ASSERT 0b0
#define DCU_GAR_REG_DCU_RST_N_DE_ASSERT 0b1
#define DCU_GAR_REG_DCU_CLK_EN_OFFSET 0
#define DCU_GAR_REG_DCU_CLK_EN_CLEAR_MASK 0x00000001
#define DCU_GAR_REG_DCU_CLK_EN_MASK 0x0
#define DCU_GAR_REG_DCU_CLK_EN_PASS 0b1
 
#define DAP_GAR_REG 0x000007ac//DAP Gating And Reset Register
#define DAP_GAR_REG_DAP_RST_N_OFFSET 16
#define DAP_GAR_REG_DAP_RST_N_CLEAR_MASK 0x00010000
#define DAP_GAR_REG_DAP_RST_N_ASSERT 0b0
#define DAP_GAR_REG_DAP_RST_N_SECURE_DEBUG 0b1
#define DAP_GAR_REG_DAP_AHB_CLK_EN_OFFSET 0
#define DAP_GAR_REG_DAP_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DAP_GAR_REG_DAP_AHB_CLK_EN_MASK 0x0
#define DAP_GAR_REG_DAP_AHB_CLK_EN_SECURE_DEBUG 0b1
 
#define PWMCS0_CLK_REG 0x000007c0//PWMCS0 Clock Register
#define PWMCS0_CLK_REG_PWMCS0_CLK_GATING_OFFSET 31
#define PWMCS0_CLK_REG_PWMCS0_CLK_GATING_CLEAR_MASK (0x80000000)
#define PWMCS0_CLK_REG_PWMCS0_CLK_GATING_CLOCK_IS_OFF 0b0
#define PWMCS0_CLK_REG_PWMCS0_CLK_GATING_CLOCK_IS_ON 0b1
#define PWMCS0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PWMCS0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define PWMCS0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define PWMCS0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define PWMCS0_CLK_REG_FACTOR_M_OFFSET 0
#define PWMCS0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define PWMCS0_GAR_REG 0x000007c4//PWMCS0 Gating And Reset Register
#define PWMCS0_GAR_REG_PWMCS0_RST_N_OFFSET 16
#define PWMCS0_GAR_REG_PWMCS0_RST_N_CLEAR_MASK 0x00010000
#define PWMCS0_GAR_REG_PWMCS0_RST_N_ASSERT 0b0
#define PWMCS0_GAR_REG_PWMCS0_RST_N_DE_ASSERT 0b1
#define PWMCS0_GAR_REG_PWMCS0_APB_CLK_EN_OFFSET 0
#define PWMCS0_GAR_REG_PWMCS0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWMCS0_GAR_REG_PWMCS0_APB_CLK_EN_MASK 0x0
#define PWMCS0_GAR_REG_PWMCS0_APB_CLK_EN_PASS 0b1
 
#define PWMCS1_CLK_REG 0x000007c8//PWMCS1 Clock Register
#define PWMCS1_CLK_REG_PWMCS1_CLK_GATING_OFFSET 31
#define PWMCS1_CLK_REG_PWMCS1_CLK_GATING_CLEAR_MASK (0x80000000)
#define PWMCS1_CLK_REG_PWMCS1_CLK_GATING_CLOCK_IS_OFF 0b0
#define PWMCS1_CLK_REG_PWMCS1_CLK_GATING_CLOCK_IS_ON 0b1
#define PWMCS1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PWMCS1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define PWMCS1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define PWMCS1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define PWMCS1_CLK_REG_FACTOR_M_OFFSET 0
#define PWMCS1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define PWMCS1_GAR_REG 0x000007cc//PWMCS1 Gating And Reset Register
#define PWMCS1_GAR_REG_PWMCS1_RST_N_OFFSET 16
#define PWMCS1_GAR_REG_PWMCS1_RST_N_CLEAR_MASK 0x00010000
#define PWMCS1_GAR_REG_PWMCS1_RST_N_ASSERT 0b0
#define PWMCS1_GAR_REG_PWMCS1_RST_N_DE_ASSERT 0b1
#define PWMCS1_GAR_REG_PWMCS1_APB_CLK_EN_OFFSET 0
#define PWMCS1_GAR_REG_PWMCS1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWMCS1_GAR_REG_PWMCS1_APB_CLK_EN_MASK 0x0
#define PWMCS1_GAR_REG_PWMCS1_APB_CLK_EN_PASS 0b1
 
#define TIMER0_0_CLK_REG 0x00000800//TIMER0_0 Clock Register
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_OFFSET 31
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_DISABLE 0b0
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_ENABLE 0b1
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_0_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_0_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_0_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_0_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_0_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_0_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_0_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_0_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_0_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_0_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_1_CLK_REG 0x00000804//TIMER0_1 Clock Register
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_OFFSET 31
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_DISABLE 0b0
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_ENABLE 0b1
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_1_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_1_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_1_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_1_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_1_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_1_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_1_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_1_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_1_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_1_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_2_CLK_REG 0x00000808//TIMER0_2 Clock Register
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_OFFSET 31
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_DISABLE 0b0
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_ENABLE 0b1
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_2_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_2_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_2_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_2_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_2_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_2_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_2_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_2_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_2_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_2_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_3_CLK_REG 0x0000080c//TIMER0_3 Clock Register
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_OFFSET 31
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_DISABLE 0b0
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_ENABLE 0b1
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_3_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_3_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_3_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_3_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_3_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_3_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_3_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_3_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_3_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_3_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_4_CLK_REG 0x00000810//TIMER0_4 Clock Register
#define TIMER0_4_CLK_REG_TIMER0_4_CLK_GATING_OFFSET 31
#define TIMER0_4_CLK_REG_TIMER0_4_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_4_CLK_REG_TIMER0_4_CLK_GATING_DISABLE 0b0
#define TIMER0_4_CLK_REG_TIMER0_4_CLK_GATING_ENABLE 0b1
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_4_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_4_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_4_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_4_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_4_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_4_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_4_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_4_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_4_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_4_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_5_CLK_REG 0x00000814//TIMER0_5 Clock Register
#define TIMER0_5_CLK_REG_TIMER0_5_CLK_GATING_OFFSET 31
#define TIMER0_5_CLK_REG_TIMER0_5_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_5_CLK_REG_TIMER0_5_CLK_GATING_DISABLE 0b0
#define TIMER0_5_CLK_REG_TIMER0_5_CLK_GATING_ENABLE 0b1
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_5_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_5_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_5_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_5_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_5_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_5_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_5_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_5_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_5_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_5_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_6_CLK_REG 0x00000818//TIMER0_6 Clock Register
#define TIMER0_6_CLK_REG_TIMER0_6_CLK_GATING_OFFSET 31
#define TIMER0_6_CLK_REG_TIMER0_6_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_6_CLK_REG_TIMER0_6_CLK_GATING_DISABLE 0b0
#define TIMER0_6_CLK_REG_TIMER0_6_CLK_GATING_ENABLE 0b1
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_6_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_6_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_6_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_6_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_6_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_6_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_6_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_6_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_6_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_6_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_7_CLK_REG 0x0000081c//TIMER0_7 Clock Register
#define TIMER0_7_CLK_REG_TIMER0_7_CLK_GATING_OFFSET 31
#define TIMER0_7_CLK_REG_TIMER0_7_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_7_CLK_REG_TIMER0_7_CLK_GATING_DISABLE 0b0
#define TIMER0_7_CLK_REG_TIMER0_7_CLK_GATING_ENABLE 0b1
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_7_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_7_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_7_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_7_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_7_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_7_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_7_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_7_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_7_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_7_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_GAR_REG 0x00000850//TIMER0 Gating And Reset Register
#define TIMER0_GAR_REG_TIMER0_RST_N_OFFSET 16
#define TIMER0_GAR_REG_TIMER0_RST_N_CLEAR_MASK 0x00010000
#define TIMER0_GAR_REG_TIMER0_RST_N_ASSERT 0b0
#define TIMER0_GAR_REG_TIMER0_RST_N_DE_ASSERT 0b1
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_OFFSET 0
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_MASK 0x0
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_PASS 0b1
 
#define TIMER0_0_RV_CLK_REG 0x00000860//TIMER0_0_RISCV Clock Register
#define TIMER0_0_RV_CLK_REG_TIMER0_0_RV_CLK_GATING_OFFSET 31
#define TIMER0_0_RV_CLK_REG_TIMER0_0_RV_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_0_RV_CLK_REG_TIMER0_0_RV_CLK_GATING_DISABLE 0b0
#define TIMER0_0_RV_CLK_REG_TIMER0_0_RV_CLK_GATING_ENABLE 0b1
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_0_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_0_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_0_RV_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_0_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_0_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_0_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_0_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_0_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_0_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_0_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_0_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_1_RV_CLK_REG 0x00000864//TIMER0_1_RISCV Clock Register
#define TIMER0_1_RV_CLK_REG_TIMER0_1_RV_CLK_GATING_OFFSET 31
#define TIMER0_1_RV_CLK_REG_TIMER0_1_RV_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_1_RV_CLK_REG_TIMER0_1_RV_CLK_GATING_DISABLE 0b0
#define TIMER0_1_RV_CLK_REG_TIMER0_1_RV_CLK_GATING_ENABLE 0b1
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_1_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_1_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_1_RV_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_1_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_1_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_1_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_1_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_1_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_1_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_1_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_1_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_2_RV_CLK_REG 0x00000868//TIMER0_2_RISCV Clock Register
#define TIMER0_2_RV_CLK_REG_TIMER0_2_RV_CLK_GATING_OFFSET 31
#define TIMER0_2_RV_CLK_REG_TIMER0_2_RV_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_2_RV_CLK_REG_TIMER0_2_RV_CLK_GATING_DISABLE 0b0
#define TIMER0_2_RV_CLK_REG_TIMER0_2_RV_CLK_GATING_ENABLE 0b1
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_2_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_2_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_2_RV_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_2_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_2_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_2_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_2_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_2_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_2_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_2_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_2_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_3_RV_CLK_REG 0x0000086c//TIMER0_3_RISCV Clock Register
#define TIMER0_3_RV_CLK_REG_TIMER0_3_RV_CLK_GATING_OFFSET 31
#define TIMER0_3_RV_CLK_REG_TIMER0_3_RV_CLK_GATING_CLEAR_MASK (0x80000000)
#define TIMER0_3_RV_CLK_REG_TIMER0_3_RV_CLK_GATING_DISABLE 0b0
#define TIMER0_3_RV_CLK_REG_TIMER0_3_RV_CLK_GATING_ENABLE 0b1
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_3_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_3_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_3_RV_CLK_REG_FACTOR_M_CLEAR_MASK (0x00000007)
#define TIMER0_3_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_3_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_3_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_3_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_3_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_3_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_3_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_3_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_RV_GAR_REG 0x00000870//TIMER0_RISCV Gating And Reset Register
#define TIMER0_RV_GAR_REG_TIMER0_RV_RST_N_OFFSET 16
#define TIMER0_RV_GAR_REG_TIMER0_RV_RST_N_CLEAR_MASK 0x00010000
#define TIMER0_RV_GAR_REG_TIMER0_RV_RST_N_ASSERT 0b0
#define TIMER0_RV_GAR_REG_TIMER0_RV_RST_N_DE_ASSERT 0b1
#define TIMER0_RV_GAR_REG_TIMER0_RV_AHB_CLK_EN_OFFSET 0
#define TIMER0_RV_GAR_REG_TIMER0_RV_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TIMER0_RV_GAR_REG_TIMER0_RV_AHB_CLK_EN_MASK 0x0
#define TIMER0_RV_GAR_REG_TIMER0_RV_AHB_CLK_EN_PASS 0b1
 
#define DE0_CLK_REG 0x00000a00//DE0 Clock Register
#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31
#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK (0x80000000)
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define DE0_CLK_REG_FACTOR_M_OFFSET 0
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define DE0_GAR_REG 0x00000a04//DE0 Gating And Reset Register
#define DE0_GAR_REG_DE0_RST_N_OFFSET 16
#define DE0_GAR_REG_DE0_RST_N_CLEAR_MASK 0x00010000
#define DE0_GAR_REG_DE0_RST_N_ASSERT 0b0
#define DE0_GAR_REG_DE0_RST_N_DE_ASSERT 0b1
#define DE0_GAR_REG_DE0_AHB_CLK_EN_OFFSET 0
#define DE0_GAR_REG_DE0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DE0_GAR_REG_DE0_AHB_CLK_EN_MASK 0x0
#define DE0_GAR_REG_DE0_AHB_CLK_EN_PASS 0b1
 
#define G2D_CLK_REG 0x00000a40//G2D Clock Register
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK (0x80000000)
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define G2D_CLK_REG_FACTOR_M_OFFSET 0
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define G2D_GAR_REG 0x00000a44//G2D Gating And Reset Register
#define G2D_GAR_REG_G2D_RST_N_OFFSET 16
#define G2D_GAR_REG_G2D_RST_N_CLEAR_MASK 0x00010000
#define G2D_GAR_REG_G2D_RST_N_ASSERT 0b0
#define G2D_GAR_REG_G2D_RST_N_DE_ASSERT 0b1
#define G2D_GAR_REG_G2D_AHB_CLK_EN_OFFSET 0
#define G2D_GAR_REG_G2D_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define G2D_GAR_REG_G2D_AHB_CLK_EN_MASK 0x0
#define G2D_GAR_REG_G2D_AHB_CLK_EN_PASS 0b1
 
#define CE_SYS_CLK_REG 0x00000ac0//CE_SYS Clock Register
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET 31
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLEAR_MASK (0x80000000)
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLOCK_IS_OFF 0b0
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_SECURE_DEBUG 0b1
#define CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CE_SYS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define CE_SYS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011
#define CE_SYS_CLK_REG_FACTOR_M_OFFSET 0
#define CE_SYS_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define CE_SYS_GAR_REG 0x00000ac4//CE_SYS Gating And Reset Register
#define CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET 17
#define CE_SYS_GAR_REG_CE_SYS_RST_N_CLEAR_MASK (0x00020000)
#define CE_SYS_GAR_REG_CE_SYS_RST_N_ASSERT 0b0
#define CE_SYS_GAR_REG_CE_SYS_RST_N_SECURE_DEBUG 0b1
#define CE_SYS_GAR_REG_CE_SYS_CLK_EN_OFFSET 1
#define CE_SYS_GAR_REG_CE_SYS_CLK_EN_CLEAR_MASK (0x00000002)
#define CE_SYS_GAR_REG_CE_SYS_CLK_EN_MASK 0x0
#define CE_SYS_GAR_REG_CE_SYS_CLK_EN_SECURE_DEBUG 0b1
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET 0
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK 0x0
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_SECURE_DEBUG 0b1
 
#define RV_CORE_CLK_REG 0x00000b80//RISCV_CORE Clock Register
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_OFFSET 31
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLEAR_MASK (0x80000000)
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_OFF 0b0
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_ON 0b1
#define RV_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define RV_CORE_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define RV_CORE_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define RV_CORE_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101
#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_OFFSET 8
#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK (0x00000300)
#define RV_CORE_CLK_REG_FACTOR_M_OFFSET 0
#define RV_CORE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define RV_TS_CLK_REG 0x00000b88//RISCV_TS Clock Register
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_OFFSET 31
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLEAR_MASK (0x80000000)
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_OFF 0b0
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_ON 0b1
#define RV_TS_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define RV_TS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define RV_TS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define RV_TS_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define RV_TS_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
 
#define RV_SYS_GAR_REG 0x00000b94//RISCV_SYS Gating And Reset Register
#define RV_SYS_GAR_REG_RV_SYS_RST_N_OFFSET 17
#define RV_SYS_GAR_REG_RV_SYS_RST_N_CLEAR_MASK (0x00020000)
#define RV_SYS_GAR_REG_RV_SYS_RST_N_ASSERT 0b0
#define RV_SYS_GAR_REG_RV_SYS_RST_N_DE_ASSERT 0b1
#define RV_SYS_GAR_REG_RV_CORE_RST_N_OFFSET 16
#define RV_SYS_GAR_REG_RV_CORE_RST_N_CLEAR_MASK 0x00010000
#define RV_SYS_GAR_REG_RV_CORE_RST_N_ASSERT 0b0
#define RV_SYS_GAR_REG_RV_CORE_RST_N_DE_ASSERT 0b1
 
#define RV_CFG_GAR_REG 0x00000b9c//RISCV_CFG Gating And Reset Register
#define RV_CFG_GAR_REG_RV_CFG_RST_N_OFFSET 16
#define RV_CFG_GAR_REG_RV_CFG_RST_N_CLEAR_MASK 0x00010000
#define RV_CFG_GAR_REG_RV_CFG_RST_N_ASSERT 0b0
#define RV_CFG_GAR_REG_RV_CFG_RST_N_DE_ASSERT 0b1
#define RV_CFG_GAR_REG_RV_CFG_CLK_EN_OFFSET 0
#define RV_CFG_GAR_REG_RV_CFG_CLK_EN_CLEAR_MASK 0x00000001
#define RV_CFG_GAR_REG_RV_CFG_CLK_EN_MASK 0x0
#define RV_CFG_GAR_REG_RV_CFG_CLK_EN_PASS 0b1
 
#define DRAMC_GAR_REG 0x00000c0c//DRAMC Gating And Reset Register
#define DRAMC_GAR_REG_DRAMC_RST_N_OFFSET 16
#define DRAMC_GAR_REG_DRAMC_RST_N_CLEAR_MASK 0x00010000
#define DRAMC_GAR_REG_DRAMC_RST_N_ASSERT 0b0
#define DRAMC_GAR_REG_DRAMC_RST_N_DE_ASSERT 0b1
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_OFFSET 0
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_MASK 0x0
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_PASS 0b1
 
#define SMHC0_CLK_REG 0x00000d00//SMHC0 Clock Register
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK (0x80000000)
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SMHC0_GAR_REG 0x00000d0c//SMHC0 Gating And Reset Register
#define SMHC0_GAR_REG_SMHC0_RST_N_OFFSET 16
#define SMHC0_GAR_REG_SMHC0_RST_N_CLEAR_MASK 0x00010000
#define SMHC0_GAR_REG_SMHC0_RST_N_ASSERT 0b0
#define SMHC0_GAR_REG_SMHC0_RST_N_DE_ASSERT 0b1
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET 0
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_MASK 0x0
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_PASS 0b1
 
#define SMHC1_CLK_REG 0x00000d10//SMHC1 Clock Register
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK (0x80000000)
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SMHC1_GAR_REG 0x00000d1c//SMHC1 Gating And Reset Register
#define SMHC1_GAR_REG_SMHC1_RST_N_OFFSET 16
#define SMHC1_GAR_REG_SMHC1_RST_N_CLEAR_MASK 0x00010000
#define SMHC1_GAR_REG_SMHC1_RST_N_ASSERT 0b0
#define SMHC1_GAR_REG_SMHC1_RST_N_DE_ASSERT 0b1
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_OFFSET 0
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_MASK 0x0
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_PASS 0b1
 
#define SMHC2_CLK_REG 0x00000d20//SMHC2 Clock Register
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK (0x80000000)
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100
#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SMHC2_GAR_REG 0x00000d2c//SMHC2 Gating And Reset Register
#define SMHC2_GAR_REG_SMHC2_RST_N_OFFSET 16
#define SMHC2_GAR_REG_SMHC2_RST_N_CLEAR_MASK 0x00010000
#define SMHC2_GAR_REG_SMHC2_RST_N_ASSERT 0b0
#define SMHC2_GAR_REG_SMHC2_RST_N_DE_ASSERT 0b1
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_OFFSET 0
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_MASK 0x0
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_PASS 0b1
 
#define UART0_GAR_REG 0x00000e00//UART0 Gating And Reset Register
#define UART0_GAR_REG_UART0_RST_N_OFFSET 16
#define UART0_GAR_REG_UART0_RST_N_CLEAR_MASK 0x00010000
#define UART0_GAR_REG_UART0_RST_N_ASSERT 0b0
#define UART0_GAR_REG_UART0_RST_N_DE_ASSERT 0b1
#define UART0_GAR_REG_UART0_APB_CLK_EN_OFFSET 0
#define UART0_GAR_REG_UART0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART0_GAR_REG_UART0_APB_CLK_EN_MASK 0x0
#define UART0_GAR_REG_UART0_APB_CLK_EN_PASS 0b1
 
#define UART1_GAR_REG 0x00000e04//UART1 Gating And Reset Register
#define UART1_GAR_REG_UART1_RST_N_OFFSET 16
#define UART1_GAR_REG_UART1_RST_N_CLEAR_MASK 0x00010000
#define UART1_GAR_REG_UART1_RST_N_ASSERT 0b0
#define UART1_GAR_REG_UART1_RST_N_DE_ASSERT 0b1
#define UART1_GAR_REG_UART1_APB_CLK_EN_OFFSET 0
#define UART1_GAR_REG_UART1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART1_GAR_REG_UART1_APB_CLK_EN_MASK 0x0
#define UART1_GAR_REG_UART1_APB_CLK_EN_PASS 0b1
 
#define UART2_GAR_REG 0x00000e08//UART2 Gating And Reset Register
#define UART2_GAR_REG_UART2_RST_N_OFFSET 16
#define UART2_GAR_REG_UART2_RST_N_CLEAR_MASK 0x00010000
#define UART2_GAR_REG_UART2_RST_N_ASSERT 0b0
#define UART2_GAR_REG_UART2_RST_N_DE_ASSERT 0b1
#define UART2_GAR_REG_UART2_APB_CLK_EN_OFFSET 0
#define UART2_GAR_REG_UART2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART2_GAR_REG_UART2_APB_CLK_EN_MASK 0x0
#define UART2_GAR_REG_UART2_APB_CLK_EN_PASS 0b1
 
#define UART3_GAR_REG 0x00000e0c//UART3 Gating And Reset Register
#define UART3_GAR_REG_UART3_RST_N_OFFSET 16
#define UART3_GAR_REG_UART3_RST_N_CLEAR_MASK 0x00010000
#define UART3_GAR_REG_UART3_RST_N_ASSERT 0b0
#define UART3_GAR_REG_UART3_RST_N_DE_ASSERT 0b1
#define UART3_GAR_REG_UART3_APB_CLK_EN_OFFSET 0
#define UART3_GAR_REG_UART3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART3_GAR_REG_UART3_APB_CLK_EN_MASK 0x0
#define UART3_GAR_REG_UART3_APB_CLK_EN_PASS 0b1
 
#define UART4_GAR_REG 0x00000e10//UART4 Gating And Reset Register
#define UART4_GAR_REG_UART4_RST_N_OFFSET 16
#define UART4_GAR_REG_UART4_RST_N_CLEAR_MASK 0x00010000
#define UART4_GAR_REG_UART4_RST_N_ASSERT 0b0
#define UART4_GAR_REG_UART4_RST_N_DE_ASSERT 0b1
#define UART4_GAR_REG_UART4_APB_CLK_EN_OFFSET 0
#define UART4_GAR_REG_UART4_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART4_GAR_REG_UART4_APB_CLK_EN_MASK 0x0
#define UART4_GAR_REG_UART4_APB_CLK_EN_PASS 0b1
 
#define UART5_GAR_REG 0x00000e14//UART5 Gating And Reset Register
#define UART5_GAR_REG_UART5_RST_N_OFFSET 16
#define UART5_GAR_REG_UART5_RST_N_CLEAR_MASK 0x00010000
#define UART5_GAR_REG_UART5_RST_N_ASSERT 0b0
#define UART5_GAR_REG_UART5_RST_N_DE_ASSERT 0b1
#define UART5_GAR_REG_UART5_APB_CLK_EN_OFFSET 0
#define UART5_GAR_REG_UART5_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART5_GAR_REG_UART5_APB_CLK_EN_MASK 0x0
#define UART5_GAR_REG_UART5_APB_CLK_EN_PASS 0b1
 
#define UART6_GAR_REG 0x00000e18//UART6 Gating And Reset Register
#define UART6_GAR_REG_UART6_RST_N_OFFSET 16
#define UART6_GAR_REG_UART6_RST_N_CLEAR_MASK 0x00010000
#define UART6_GAR_REG_UART6_RST_N_ASSERT 0b0
#define UART6_GAR_REG_UART6_RST_N_DE_ASSERT 0b1
#define UART6_GAR_REG_UART6_APB_CLK_EN_OFFSET 0
#define UART6_GAR_REG_UART6_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART6_GAR_REG_UART6_APB_CLK_EN_MASK 0x0
#define UART6_GAR_REG_UART6_APB_CLK_EN_PASS 0b1
 
#define UART7_GAR_REG 0x00000e20//UART7 Gating And Reset Register
#define UART7_GAR_REG_UART7_RST_N_OFFSET 16
#define UART7_GAR_REG_UART7_RST_N_CLEAR_MASK 0x00010000
#define UART7_GAR_REG_UART7_RST_N_ASSERT 0b0
#define UART7_GAR_REG_UART7_RST_N_DE_ASSERT 0b1
#define UART7_GAR_REG_UART7_APB_CLK_EN_OFFSET 0
#define UART7_GAR_REG_UART7_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART7_GAR_REG_UART7_APB_CLK_EN_MASK 0x0
#define UART7_GAR_REG_UART7_APB_CLK_EN_PASS 0b1
 
#define UART8_GAR_REG 0x00000e24//UART8 Gating And Reset Register
#define UART8_GAR_REG_UART8_RST_N_OFFSET 16
#define UART8_GAR_REG_UART8_RST_N_CLEAR_MASK 0x00010000
#define UART8_GAR_REG_UART8_RST_N_ASSERT 0b0
#define UART8_GAR_REG_UART8_RST_N_DE_ASSERT 0b1
#define UART8_GAR_REG_UART8_APB_CLK_EN_OFFSET 0
#define UART8_GAR_REG_UART8_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART8_GAR_REG_UART8_APB_CLK_EN_MASK 0x0
#define UART8_GAR_REG_UART8_APB_CLK_EN_PASS 0b1
 
#define UART9_GAR_REG 0x00000e28//UART9 Gating And Reset Register
#define UART9_GAR_REG_UART9_RST_N_OFFSET 16
#define UART9_GAR_REG_UART9_RST_N_CLEAR_MASK 0x00010000
#define UART9_GAR_REG_UART9_RST_N_ASSERT 0b0
#define UART9_GAR_REG_UART9_RST_N_DE_ASSERT 0b1
#define UART9_GAR_REG_UART9_APB_CLK_EN_OFFSET 0
#define UART9_GAR_REG_UART9_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART9_GAR_REG_UART9_APB_CLK_EN_MASK 0x0
#define UART9_GAR_REG_UART9_APB_CLK_EN_PASS 0b1
 
#define TWI0_GAR_REG 0x00000e80//TWI0 Gating And Reset Register
#define TWI0_GAR_REG_TWI0_RST_N_OFFSET 16
#define TWI0_GAR_REG_TWI0_RST_N_CLEAR_MASK 0x00010000
#define TWI0_GAR_REG_TWI0_RST_N_ASSERT 0b0
#define TWI0_GAR_REG_TWI0_RST_N_DE_ASSERT 0b1
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_OFFSET 0
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_MASK 0x0
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_PASS 0b1
 
#define TWI1_GAR_REG 0x00000e84//TWI1 Gating And Reset Register
#define TWI1_GAR_REG_TWI1_RST_N_OFFSET 16
#define TWI1_GAR_REG_TWI1_RST_N_CLEAR_MASK 0x00010000
#define TWI1_GAR_REG_TWI1_RST_N_ASSERT 0b0
#define TWI1_GAR_REG_TWI1_RST_N_DE_ASSERT 0b1
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_OFFSET 0
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_MASK 0x0
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_PASS 0b1
 
#define TWI2_GAR_REG 0x00000e88//TWI2 Gating And Reset Register
#define TWI2_GAR_REG_TWI2_RST_N_OFFSET 16
#define TWI2_GAR_REG_TWI2_RST_N_CLEAR_MASK 0x00010000
#define TWI2_GAR_REG_TWI2_RST_N_ASSERT 0b0
#define TWI2_GAR_REG_TWI2_RST_N_DE_ASSERT 0b1
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_OFFSET 0
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_MASK 0x0
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_PASS 0b1
 
#define TWI3_GAR_REG 0x00000e8c//TWI3 Gating And Reset Register
#define TWI3_GAR_REG_TWI3_RST_N_OFFSET 16
#define TWI3_GAR_REG_TWI3_RST_N_CLEAR_MASK 0x00010000
#define TWI3_GAR_REG_TWI3_RST_N_ASSERT 0b0
#define TWI3_GAR_REG_TWI3_RST_N_DE_ASSERT 0b1
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_OFFSET 0
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_MASK 0x0
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_PASS 0b1
 
#define TWI4_GAR_REG 0x00000e90//TWI4 Gating And Reset Register
#define TWI4_GAR_REG_TWI4_RST_N_OFFSET 16
#define TWI4_GAR_REG_TWI4_RST_N_CLEAR_MASK 0x00010000
#define TWI4_GAR_REG_TWI4_RST_N_ASSERT 0b0
#define TWI4_GAR_REG_TWI4_RST_N_DE_ASSERT 0b1
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_OFFSET 0
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_MASK 0x0
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_PASS 0b1
 
#define TWI5_GAR_REG 0x00000e94//TWI5 Gating And Reset Register
#define TWI5_GAR_REG_TWI5_RST_N_OFFSET 16
#define TWI5_GAR_REG_TWI5_RST_N_CLEAR_MASK 0x00010000
#define TWI5_GAR_REG_TWI5_RST_N_ASSERT 0b0
#define TWI5_GAR_REG_TWI5_RST_N_DE_ASSERT 0b1
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_OFFSET 0
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_MASK 0x0
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_PASS 0b1
 
#define SPI0_CLK_REG 0x00000f00//SPI0 Clock Register
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK (0x80000000)
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI0_CLK_REG_FACTOR_N_OFFSET 8
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SPI0_CLK_REG_FACTOR_M_OFFSET 0
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SPI0_GAR_REG 0x00000f04//SPI0 Gating And Reset Register
#define SPI0_GAR_REG_SPI0_RST_N_OFFSET 16
#define SPI0_GAR_REG_SPI0_RST_N_CLEAR_MASK 0x00010000
#define SPI0_GAR_REG_SPI0_RST_N_ASSERT 0b0
#define SPI0_GAR_REG_SPI0_RST_N_DE_ASSERT 0b1
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_OFFSET 0
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_MASK 0x0
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_PASS 0b1
 
#define SPI1_CLK_REG 0x00000f08//SPI1 Clock Register
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK (0x80000000)
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI1_CLK_REG_FACTOR_N_OFFSET 8
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SPI1_CLK_REG_FACTOR_M_OFFSET 0
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SPI1_GAR_REG 0x00000f0c//SPI1 Gating And Reset Register
#define SPI1_GAR_REG_SPI1_RST_N_OFFSET 16
#define SPI1_GAR_REG_SPI1_RST_N_CLEAR_MASK 0x00010000
#define SPI1_GAR_REG_SPI1_RST_N_ASSERT 0b0
#define SPI1_GAR_REG_SPI1_RST_N_DE_ASSERT 0b1
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_OFFSET 0
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_MASK 0x0
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_PASS 0b1
 
#define SPI2_CLK_REG 0x00000f10//SPI2 Clock Register
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK (0x80000000)
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI2_CLK_REG_FACTOR_N_OFFSET 8
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SPI2_CLK_REG_FACTOR_M_OFFSET 0
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SPI2_GAR_REG 0x00000f14//SPI2 Gating And Reset Register
#define SPI2_GAR_REG_SPI2_RST_N_OFFSET 16
#define SPI2_GAR_REG_SPI2_RST_N_CLEAR_MASK 0x00010000
#define SPI2_GAR_REG_SPI2_RST_N_ASSERT 0b0
#define SPI2_GAR_REG_SPI2_RST_N_DE_ASSERT 0b1
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_OFFSET 0
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_MASK 0x0
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_PASS 0b1
 
#define SPIF_CLK_REG 0x00000f18//SPIF Clock Register
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK (0x80000000)
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SPIF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b101
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b110
#define SPIF_CLK_REG_FACTOR_N_OFFSET 8
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SPIF_CLK_REG_FACTOR_M_OFFSET 0
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SPIF_GAR_REG 0x00000f1c//SPIF Gating And Reset Register
#define SPIF_GAR_REG_SPIF_RST_N_OFFSET 16
#define SPIF_GAR_REG_SPIF_RST_N_CLEAR_MASK 0x00010000
#define SPIF_GAR_REG_SPIF_RST_N_ASSERT 0b0
#define SPIF_GAR_REG_SPIF_RST_N_DE_ASSERT 0b1
#define SPIF_GAR_REG_SPIF_AHB_CLK_EN_OFFSET 0
#define SPIF_GAR_REG_SPIF_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPIF_GAR_REG_SPIF_AHB_CLK_EN_MASK 0x0
#define SPIF_GAR_REG_SPIF_AHB_CLK_EN_PASS 0b1
 
#define SPI3_CLK_REG 0x00000f20//SPI3 Clock Register
#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK (0x80000000)
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define SPI3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI3_CLK_REG_FACTOR_N_OFFSET 8
#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define SPI3_CLK_REG_FACTOR_M_OFFSET 0
#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define SPI3_GAR_REG 0x00000f24//SPI3 Gating And Reset Register
#define SPI3_GAR_REG_SPI3_RST_N_OFFSET 16
#define SPI3_GAR_REG_SPI3_RST_N_CLEAR_MASK 0x00010000
#define SPI3_GAR_REG_SPI3_RST_N_ASSERT 0b0
#define SPI3_GAR_REG_SPI3_RST_N_DE_ASSERT 0b1
#define SPI3_GAR_REG_SPI3_AHB_CLK_EN_OFFSET 0
#define SPI3_GAR_REG_SPI3_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI3_GAR_REG_SPI3_AHB_CLK_EN_MASK 0x0
#define SPI3_GAR_REG_SPI3_AHB_CLK_EN_PASS 0b1
 
#define GPADC0_CLK_REG 0x00000fc0//GPADC0 Clock Register
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET 31
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK (0x80000000)
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GPADC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC0_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GPADC0_GAR_REG 0x00000fc4//GPADC0 Gating And Reset Register
#define GPADC0_GAR_REG_GPADC0_RST_N_OFFSET 16
#define GPADC0_GAR_REG_GPADC0_RST_N_CLEAR_MASK 0x00010000
#define GPADC0_GAR_REG_GPADC0_RST_N_ASSERT 0b0
#define GPADC0_GAR_REG_GPADC0_RST_N_DE_ASSERT 0b1
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_OFFSET 0
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_MASK 0x0
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_PASS 0b1
 
#define GPADC1_CLK_REG 0x00000fc8//GPADC1 Clock Register
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_OFFSET 31
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLEAR_MASK (0x80000000)
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GPADC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GPADC1_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC1_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GPADC1_GAR_REG 0x00000fcc//GPADC1 Gating And Reset Register
#define GPADC1_GAR_REG_GPADC1_RST_N_OFFSET 16
#define GPADC1_GAR_REG_GPADC1_RST_N_CLEAR_MASK 0x00010000
#define GPADC1_GAR_REG_GPADC1_RST_N_ASSERT 0b0
#define GPADC1_GAR_REG_GPADC1_RST_N_DE_ASSERT 0b1
#define GPADC1_GAR_REG_GPADC1_APB_CLK_EN_OFFSET 0
#define GPADC1_GAR_REG_GPADC1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define GPADC1_GAR_REG_GPADC1_APB_CLK_EN_MASK 0x0
#define GPADC1_GAR_REG_GPADC1_APB_CLK_EN_PASS 0b1
 
#define GPADC2_CLK_REG 0x00000fd0//GPADC2 Clock Register
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_OFFSET 31
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLEAR_MASK (0x80000000)
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GPADC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GPADC2_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC2_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GPADC2_GAR_REG 0x00000fd4//GPADC2 Gating And Reset Register
#define GPADC2_GAR_REG_GPADC2_RST_N_OFFSET 16
#define GPADC2_GAR_REG_GPADC2_RST_N_CLEAR_MASK 0x00010000
#define GPADC2_GAR_REG_GPADC2_RST_N_ASSERT 0b0
#define GPADC2_GAR_REG_GPADC2_RST_N_DE_ASSERT 0b1
#define GPADC2_GAR_REG_GPADC2_APB_CLK_EN_OFFSET 0
#define GPADC2_GAR_REG_GPADC2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define GPADC2_GAR_REG_GPADC2_APB_CLK_EN_MASK 0x0
#define GPADC2_GAR_REG_GPADC2_APB_CLK_EN_PASS 0b1
 
#define TSENSOR_GAR_REG 0x00000fe4//TSENSOR Gating And Reset Register
#define TSENSOR_GAR_REG_TSENSOR_RST_N_OFFSET 16
#define TSENSOR_GAR_REG_TSENSOR_RST_N_CLEAR_MASK 0x00010000
#define TSENSOR_GAR_REG_TSENSOR_RST_N_ASSERT 0b0
#define TSENSOR_GAR_REG_TSENSOR_RST_N_DE_ASSERT 0b1
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_OFFSET 0
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_MASK 0x0
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_PASS 0b1
 
#define IR_RX0_CLK_REG 0x00001000//IR_RX0 Clock Register
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_OFFSET 31
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLEAR_MASK (0x80000000)
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_RX0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_RX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b000
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b001
#define IR_RX0_CLK_REG_FACTOR_M_OFFSET 0
#define IR_RX0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define IR_RX0_GAR_REG 0x00001004//IR_RX0 Gating And Reset Register
#define IR_RX0_GAR_REG_IR_RX0_RST_N_OFFSET 16
#define IR_RX0_GAR_REG_IR_RX0_RST_N_CLEAR_MASK 0x00010000
#define IR_RX0_GAR_REG_IR_RX0_RST_N_ASSERT 0b0
#define IR_RX0_GAR_REG_IR_RX0_RST_N_DE_ASSERT 0b1
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_OFFSET 0
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_MASK 0x0
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_PASS 0b1
 
#define IR_TX_CLK_REG 0x00001008//IR_TX Clock Register
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_OFFSET 31
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLEAR_MASK (0x80000000)
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define IR_TX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b0
#define IR_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b1
#define IR_TX_CLK_REG_FACTOR_M_OFFSET 0
#define IR_TX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define IR_TX_GAR_REG 0x0000100c//IR_TX Gating And Reset Register
#define IR_TX_GAR_REG_IR_TX_RST_N_OFFSET 16
#define IR_TX_GAR_REG_IR_TX_RST_N_CLEAR_MASK 0x00010000
#define IR_TX_GAR_REG_IR_TX_RST_N_ASSERT 0b0
#define IR_TX_GAR_REG_IR_TX_RST_N_DE_ASSERT 0b1
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_OFFSET 0
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_MASK 0x0
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_PASS 0b1
 
#define TPADC_CLK_REG 0x00001030//TPADC Clock Register
#define TPADC_CLK_REG_TPADC_CLK_GATING_OFFSET 31
#define TPADC_CLK_REG_TPADC_CLK_GATING_CLEAR_MASK (0x80000000)
#define TPADC_CLK_REG_TPADC_CLK_GATING_CLOCK_IS_OFF 0b0
#define TPADC_CLK_REG_TPADC_CLK_GATING_CLOCK_IS_ON 0b1
#define TPADC_CLK_REG_FACTOR_M_OFFSET 0
#define TPADC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define TPADC_GAR_REG 0x00001034//TPADC Gating And Reset Register
#define TPADC_GAR_REG_TPADC_RST_N_OFFSET 16
#define TPADC_GAR_REG_TPADC_RST_N_CLEAR_MASK 0x00010000
#define TPADC_GAR_REG_TPADC_RST_N_ASSERT 0b0
#define TPADC_GAR_REG_TPADC_RST_N_DE_ASSERT 0b1
#define TPADC_GAR_REG_TPADC_APB_CLK_EN_OFFSET 0
#define TPADC_GAR_REG_TPADC_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TPADC_GAR_REG_TPADC_APB_CLK_EN_MASK 0x0
#define TPADC_GAR_REG_TPADC_APB_CLK_EN_PASS 0b1
 
#define LBC_CLK_REG 0x00001040//LBC Clock Register
#define LBC_CLK_REG_LBC_CLK_GATING_OFFSET 31
#define LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK (0x80000000)
#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF 0b0
#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON 0b1
#define LBC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define LBC_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b011
#define LBC_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b100
#define LBC_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b110
#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b111
#define LBC_CLK_REG_FACTOR_N_OFFSET 8
#define LBC_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define LBC_CLK_REG_FACTOR_M_OFFSET 0
#define LBC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define LBC_GAR_REG 0x0000104c//LBC Gating And Reset Register
#define LBC_GAR_REG_LBC_RST_N_OFFSET 16
#define LBC_GAR_REG_LBC_RST_N_CLEAR_MASK 0x00010000
#define LBC_GAR_REG_LBC_RST_N_ASSERT 0b0
#define LBC_GAR_REG_LBC_RST_N_DE_ASSERT 0b1
#define LBC_GAR_REG_LBC_AHB_CLK_EN_OFFSET 0
#define LBC_GAR_REG_LBC_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define LBC_GAR_REG_LBC_AHB_CLK_EN_MASK 0x0
#define LBC_GAR_REG_LBC_AHB_CLK_EN_PASS 0b1
 
#define IR_RX1_CLK_REG 0x00001100//IR_RX1 Clock Register
#define IR_RX1_CLK_REG_IR_RX1_CLK_GATING_OFFSET 31
#define IR_RX1_CLK_REG_IR_RX1_CLK_GATING_CLEAR_MASK (0x80000000)
#define IR_RX1_CLK_REG_IR_RX1_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_RX1_CLK_REG_IR_RX1_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_RX1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_RX1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define IR_RX1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b000
#define IR_RX1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b001
#define IR_RX1_CLK_REG_FACTOR_M_OFFSET 0
#define IR_RX1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define IR_RX1_GAR_REG 0x00001104//IR_RX1 Gating And Reset Register
#define IR_RX1_GAR_REG_IR_RX1_RST_N_OFFSET 16
#define IR_RX1_GAR_REG_IR_RX1_RST_N_CLEAR_MASK 0x00010000
#define IR_RX1_GAR_REG_IR_RX1_RST_N_ASSERT 0b0
#define IR_RX1_GAR_REG_IR_RX1_RST_N_DE_ASSERT 0b1
#define IR_RX1_GAR_REG_IR_RX1_APB_CLK_EN_OFFSET 0
#define IR_RX1_GAR_REG_IR_RX1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_RX1_GAR_REG_IR_RX1_APB_CLK_EN_MASK 0x0
#define IR_RX1_GAR_REG_IR_RX1_APB_CLK_EN_PASS 0b1
 
#define IR_RX2_CLK_REG 0x00001108//IR_RX2 Clock Register
#define IR_RX2_CLK_REG_IR_RX2_CLK_GATING_OFFSET 31
#define IR_RX2_CLK_REG_IR_RX2_CLK_GATING_CLEAR_MASK (0x80000000)
#define IR_RX2_CLK_REG_IR_RX2_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_RX2_CLK_REG_IR_RX2_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_RX2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_RX2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define IR_RX2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b000
#define IR_RX2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b001
#define IR_RX2_CLK_REG_FACTOR_M_OFFSET 0
#define IR_RX2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define IR_RX2_GAR_REG 0x0000110c//IR_RX2 Gating And Reset Register
#define IR_RX2_GAR_REG_IR_RX2_RST_N_OFFSET 16
#define IR_RX2_GAR_REG_IR_RX2_RST_N_CLEAR_MASK 0x00010000
#define IR_RX2_GAR_REG_IR_RX2_RST_N_ASSERT 0b0
#define IR_RX2_GAR_REG_IR_RX2_RST_N_DE_ASSERT 0b1
#define IR_RX2_GAR_REG_IR_RX2_APB_CLK_EN_OFFSET 0
#define IR_RX2_GAR_REG_IR_RX2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_RX2_GAR_REG_IR_RX2_APB_CLK_EN_MASK 0x0
#define IR_RX2_GAR_REG_IR_RX2_APB_CLK_EN_PASS 0b1
 
#define IR_RX3_CLK_REG 0x00001110//IR_RX3 Clock Register
#define IR_RX3_CLK_REG_IR_RX3_CLK_GATING_OFFSET 31
#define IR_RX3_CLK_REG_IR_RX3_CLK_GATING_CLEAR_MASK (0x80000000)
#define IR_RX3_CLK_REG_IR_RX3_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_RX3_CLK_REG_IR_RX3_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_RX3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_RX3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define IR_RX3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b000
#define IR_RX3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b001
#define IR_RX3_CLK_REG_FACTOR_M_OFFSET 0
#define IR_RX3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define IR_RX3_GAR_REG 0x00001114//IR_RX3 Gating And Reset Register
#define IR_RX3_GAR_REG_IR_RX3_RST_N_OFFSET 16
#define IR_RX3_GAR_REG_IR_RX3_RST_N_CLEAR_MASK 0x00010000
#define IR_RX3_GAR_REG_IR_RX3_RST_N_ASSERT 0b0
#define IR_RX3_GAR_REG_IR_RX3_RST_N_DE_ASSERT 0b1
#define IR_RX3_GAR_REG_IR_RX3_APB_CLK_EN_OFFSET 0
#define IR_RX3_GAR_REG_IR_RX3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_RX3_GAR_REG_IR_RX3_APB_CLK_EN_MASK 0x0
#define IR_RX3_GAR_REG_IR_RX3_APB_CLK_EN_PASS 0b1
 
#define I2S0_CLK_REG 0x00001200//I2S0 Clock Register
#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET 31
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK (0x80000000)
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S0_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define I2S0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2S0_CLK_REG_FACTOR_M_OFFSET 0
#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define I2S0_GAR_REG 0x0000120c//I2S0 Gating And Reset Register
#define I2S0_GAR_REG_I2S0_RST_N_OFFSET 16
#define I2S0_GAR_REG_I2S0_RST_N_CLEAR_MASK 0x00010000
#define I2S0_GAR_REG_I2S0_RST_N_ASSERT 0b0
#define I2S0_GAR_REG_I2S0_RST_N_DE_ASSERT 0b1
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_OFFSET 0
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_MASK 0x0
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_PASS 0b1
 
#define I2S1_CLK_REG 0x00001210//I2S1 Clock Register
#define I2S1_CLK_REG_I2S1_CLK_GATING_OFFSET 31
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLEAR_MASK (0x80000000)
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S1_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define I2S1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2S1_CLK_REG_FACTOR_M_OFFSET 0
#define I2S1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define I2S1_GAR_REG 0x0000121c//I2S1 Gating And Reset Register
#define I2S1_GAR_REG_I2S1_RST_N_OFFSET 16
#define I2S1_GAR_REG_I2S1_RST_N_CLEAR_MASK 0x00010000
#define I2S1_GAR_REG_I2S1_RST_N_ASSERT 0b0
#define I2S1_GAR_REG_I2S1_RST_N_DE_ASSERT 0b1
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_OFFSET 0
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_MASK 0x0
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_PASS 0b1
 
#define I2S2_CLK_REG 0x00001220//I2S2 Clock Register
#define I2S2_CLK_REG_I2S2_CLK_GATING_OFFSET 31
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLEAR_MASK (0x80000000)
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define I2S2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2S2_CLK_REG_FACTOR_M_OFFSET 0
#define I2S2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define I2S2_GAR_REG 0x0000122c//I2S2 Gating And Reset Register
#define I2S2_GAR_REG_I2S2_RST_N_OFFSET 16
#define I2S2_GAR_REG_I2S2_RST_N_CLEAR_MASK 0x00010000
#define I2S2_GAR_REG_I2S2_RST_N_ASSERT 0b0
#define I2S2_GAR_REG_I2S2_RST_N_DE_ASSERT 0b1
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_OFFSET 0
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_MASK 0x0
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_PASS 0b1
 
#define OWA0_TX_CLK_REG 0x00001280//OWA0 TX Clock Register
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_OFFSET 31
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLEAR_MASK (0x80000000)
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define OWA0_TX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA0_TX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define OWA0_RX_CLK_REG 0x00001284//OWA0 RX Clock Register
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_OFFSET 31
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLEAR_MASK (0x80000000)
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b000
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b010
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b011
#define OWA0_RX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA0_RX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define OWA0_GAR_REG 0x0000128c//OWA0 Gating And Reset Register
#define OWA0_GAR_REG_OWA0_RST_N_OFFSET 16
#define OWA0_GAR_REG_OWA0_RST_N_CLEAR_MASK 0x00010000
#define OWA0_GAR_REG_OWA0_RST_N_ASSERT 0b0
#define OWA0_GAR_REG_OWA0_RST_N_DE_ASSERT 0b1
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_OFFSET 0
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_MASK 0x0
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_PASS 0b1
 
#define DMIC_CLK_REG 0x000012c0//DMIC Clock Register
#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK (0x80000000)
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1
#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define DMIC_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define DMIC_CLK_REG_FACTOR_M_OFFSET 0
#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define DMIC_GAR_REG 0x000012cc//DMIC Gating And Reset Register
#define DMIC_GAR_REG_DMIC_RST_N_OFFSET 16
#define DMIC_GAR_REG_DMIC_RST_N_CLEAR_MASK 0x00010000
#define DMIC_GAR_REG_DMIC_RST_N_ASSERT 0b0
#define DMIC_GAR_REG_DMIC_RST_N_DE_ASSERT 0b1
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_OFFSET 0
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_CLEAR_MASK 0x00000001
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_MASK 0x0
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_PASS 0b1
 
#define AUDIOCODEC0_DAC_CLK_REG 0x000012e0//AUDIOCODEC0 DAC Clock Register
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_OFFSET 31
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLEAR_MASK (0x80000000)
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_OFF 0b0
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_ON 0b1
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_OFFSET 0
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define AUDIOCODEC0_GAR_REG 0x000012ec//AUDIOCODEC0 Gating And Reset Register
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_OFFSET 16
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_CLEAR_MASK 0x00010000
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_ASSERT 0b0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_DE_ASSERT 0b1
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_OFFSET 0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_MASK 0x0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_PASS 0b1
 
#define USB0_CLK_REG 0x00001300//USB0 Clock Register
#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK (0x80000000)
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK (0x03000000)
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_CLK48M 0b00
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK 0b01
#define USB0_CLK_REG_USB0_CLK12M_SEL_SYS_32K_CLK 0b10
#define USB0_CLK_REG_USB0_CLK12M_SEL_RC_16M_CLK 0b11
 
#define USB0_GAR_REG 0x00001304//USB0 Gating And Reset Register
#define USB0_GAR_REG_USB0_DEV_RST_N_OFFSET 24
#define USB0_GAR_REG_USB0_DEV_RST_N_CLEAR_MASK 0x01000000
#define USB0_GAR_REG_USB0_DEV_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_DEV_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_EHCI_RST_N_OFFSET 20
#define USB0_GAR_REG_USB0_EHCI_RST_N_CLEAR_MASK 0x00100000
#define USB0_GAR_REG_USB0_EHCI_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_EHCI_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_OHCI_RST_N_OFFSET 16
#define USB0_GAR_REG_USB0_OHCI_RST_N_CLEAR_MASK 0x00010000
#define USB0_GAR_REG_USB0_OHCI_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_OHCI_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_OFFSET 8
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_CLEAR_MASK 0x00000100
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_MASK 0x0
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_PASS 0b1
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_OFFSET 4
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_CLEAR_MASK 0x00000010
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_MASK 0x0
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_PASS 0b1
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_OFFSET 0
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_MASK 0x0
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_PASS 0b1
 
#define USB1_CLK_REG 0x00001308//USB1 Clock Register
#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK (0x80000000)
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK (0x03000000)
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_CLK48M 0b00
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK 0b01
#define USB1_CLK_REG_USB1_CLK12M_SEL_SYS_32K_CLK 0b10
#define USB1_CLK_REG_USB1_CLK12M_SEL_RC_16M_CLK 0b11
 
#define USB1_GAR_REG 0x0000130c//USB1 Gating And Reset Register
#define USB1_GAR_REG_USB1_EHCI_RST_N_OFFSET 20
#define USB1_GAR_REG_USB1_EHCI_RST_N_CLEAR_MASK 0x00100000
#define USB1_GAR_REG_USB1_EHCI_RST_N_ASSERT 0b0
#define USB1_GAR_REG_USB1_EHCI_RST_N_DE_ASSERT 0b1
#define USB1_GAR_REG_USB1_OHCI_RST_N_OFFSET 16
#define USB1_GAR_REG_USB1_OHCI_RST_N_CLEAR_MASK 0x00010000
#define USB1_GAR_REG_USB1_OHCI_RST_N_ASSERT 0b0
#define USB1_GAR_REG_USB1_OHCI_RST_N_DE_ASSERT 0b1
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_OFFSET 4
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_CLEAR_MASK 0x00000010
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_MASK 0x0
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_PASS 0b1
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_OFFSET 0
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_MASK 0x0
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_PASS 0b1
 
#define USB2P0_SYS_PHY_REF_CLK_REG 0x00001340//USB2P0_SYS PHY Reference Clock Register
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_OFFSET 31
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLEAR_MASK (0x80000000)
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1
 
#define USB2P0_SYS_GAR_REG 0x00001344//USB2P0_SYS Gating And Reset Register
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_OFFSET 16
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_CLEAR_MASK 0x00010000
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_ASSERT 0b0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_DE_ASSERT 0b1
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_OFFSET 0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_MASK 0x0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_PASS 0b1
 
#define GMAC0_PHY_CLK_REG 0x00001400//GMAC0 PHY Clock Register
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC0_PTP_REF_CLK_REG 0x00001404//GMAC0 PTP Reference Clock Register
#define GMAC0_PTP_REF_CLK_REG_GMAC0_PTP_REF_CLK_GATING_OFFSET 31
#define GMAC0_PTP_REF_CLK_REG_GMAC0_PTP_REF_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC0_PTP_REF_CLK_REG_GMAC0_PTP_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC0_PTP_REF_CLK_REG_GMAC0_PTP_REF_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC0_PTP_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GMAC0_PTP_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GMAC0_PTP_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GMAC0_PTP_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define GMAC0_PTP_REF_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC0_PTP_REF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC0_GAR_REG 0x0000140c//GMAC0 Gating And Reset Register
#define GMAC0_GAR_REG_GMAC0_TOP_AHB_RST_N_OFFSET 18
#define GMAC0_GAR_REG_GMAC0_TOP_AHB_RST_N_CLEAR_MASK (0x00040000)
#define GMAC0_GAR_REG_GMAC0_TOP_AHB_RST_N_ASSERT 0b0
#define GMAC0_GAR_REG_GMAC0_TOP_AHB_RST_N_DE_ASSERT 0b1
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_OFFSET 17
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_CLEAR_MASK (0x00020000)
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_ASSERT 0b0
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_DE_ASSERT 0b1
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_OFFSET 16
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_CLEAR_MASK 0x00010000
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_ASSERT 0b0
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_DE_ASSERT 0b1
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_OFFSET 0
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_MASK 0x0
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_PASS 0b1
 
#define GMAC1_PHY_CLK_REG 0x00001410//GMAC1 PHY Clock Register
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC1_PTP_REF_CLK_REG 0x00001414//GMAC1 PTP Reference Clock Register
#define GMAC1_PTP_REF_CLK_REG_GMAC1_PTP_REF_CLK_GATING_OFFSET 31
#define GMAC1_PTP_REF_CLK_REG_GMAC1_PTP_REF_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC1_PTP_REF_CLK_REG_GMAC1_PTP_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC1_PTP_REF_CLK_REG_GMAC1_PTP_REF_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC1_PTP_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GMAC1_PTP_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GMAC1_PTP_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GMAC1_PTP_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define GMAC1_PTP_REF_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC1_PTP_REF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC1_GAR_REG 0x0000141c//GMAC1 Gating And Reset Register
#define GMAC1_GAR_REG_GMAC1_TOP_AHB_RST_N_OFFSET 18
#define GMAC1_GAR_REG_GMAC1_TOP_AHB_RST_N_CLEAR_MASK (0x00040000)
#define GMAC1_GAR_REG_GMAC1_TOP_AHB_RST_N_ASSERT 0b0
#define GMAC1_GAR_REG_GMAC1_TOP_AHB_RST_N_DE_ASSERT 0b1
#define GMAC1_GAR_REG_GMAC1_AXI_RST_N_OFFSET 17
#define GMAC1_GAR_REG_GMAC1_AXI_RST_N_CLEAR_MASK (0x00020000)
#define GMAC1_GAR_REG_GMAC1_AXI_RST_N_ASSERT 0b0
#define GMAC1_GAR_REG_GMAC1_AXI_RST_N_DE_ASSERT 0b1
#define GMAC1_GAR_REG_GMAC1_AHB_RST_N_OFFSET 16
#define GMAC1_GAR_REG_GMAC1_AHB_RST_N_CLEAR_MASK 0x00010000
#define GMAC1_GAR_REG_GMAC1_AHB_RST_N_ASSERT 0b0
#define GMAC1_GAR_REG_GMAC1_AHB_RST_N_DE_ASSERT 0b1
#define GMAC1_GAR_REG_GMAC1_AHB_CLK_EN_OFFSET 0
#define GMAC1_GAR_REG_GMAC1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define GMAC1_GAR_REG_GMAC1_AHB_CLK_EN_MASK 0x0
#define GMAC1_GAR_REG_GMAC1_AHB_CLK_EN_PASS 0b1
 
#define GMAC2_PHY_CLK_REG 0x00001420//GMAC2 PHY Clock Register
#define GMAC2_PHY_CLK_REG_GMAC2_PHY_CLK_GATING_OFFSET 31
#define GMAC2_PHY_CLK_REG_GMAC2_PHY_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC2_PHY_CLK_REG_GMAC2_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC2_PHY_CLK_REG_GMAC2_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC2_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC2_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC2_PTP_REF_CLK_REG 0x00001424//GMAC2 PTP Reference Clock Register
#define GMAC2_PTP_REF_CLK_REG_GMAC2_PTP_REF_CLK_GATING_OFFSET 31
#define GMAC2_PTP_REF_CLK_REG_GMAC2_PTP_REF_CLK_GATING_CLEAR_MASK (0x80000000)
#define GMAC2_PTP_REF_CLK_REG_GMAC2_PTP_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC2_PTP_REF_CLK_REG_GMAC2_PTP_REF_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC2_PTP_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GMAC2_PTP_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define GMAC2_PTP_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GMAC2_PTP_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define GMAC2_PTP_REF_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC2_PTP_REF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define GMAC2_GAR_REG 0x0000142c//GMAC2 Gating And Reset Register
#define GMAC2_GAR_REG_GMAC2_TOP_AHB_RST_N_OFFSET 18
#define GMAC2_GAR_REG_GMAC2_TOP_AHB_RST_N_CLEAR_MASK (0x00040000)
#define GMAC2_GAR_REG_GMAC2_TOP_AHB_RST_N_ASSERT 0b0
#define GMAC2_GAR_REG_GMAC2_TOP_AHB_RST_N_DE_ASSERT 0b1
#define GMAC2_GAR_REG_GMAC2_AXI_RST_N_OFFSET 17
#define GMAC2_GAR_REG_GMAC2_AXI_RST_N_CLEAR_MASK (0x00020000)
#define GMAC2_GAR_REG_GMAC2_AXI_RST_N_ASSERT 0b0
#define GMAC2_GAR_REG_GMAC2_AXI_RST_N_DE_ASSERT 0b1
#define GMAC2_GAR_REG_GMAC2_AHB_RST_N_OFFSET 16
#define GMAC2_GAR_REG_GMAC2_AHB_RST_N_CLEAR_MASK 0x00010000
#define GMAC2_GAR_REG_GMAC2_AHB_RST_N_ASSERT 0b0
#define GMAC2_GAR_REG_GMAC2_AHB_RST_N_DE_ASSERT 0b1
#define GMAC2_GAR_REG_GMAC2_AHB_CLK_EN_OFFSET 0
#define GMAC2_GAR_REG_GMAC2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define GMAC2_GAR_REG_GMAC2_AHB_CLK_EN_MASK 0x0
#define GMAC2_GAR_REG_GMAC2_AHB_CLK_EN_PASS 0b1
 
#define TCON_LCD0_CLK_REG 0x00001500//TCON_LCD0 Clock Register
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_OFFSET 31
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLEAR_MASK (0x80000000)
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_OFF 0b0
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_ON 0b1
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b001
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b010
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b011
#define TCON_LCD0_CLK_REG_FACTOR_M_OFFSET 0
#define TCON_LCD0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define TCON_LCD0_GAR_REG 0x00001504//TCON_LCD0 Gating And Reset Register
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_OFFSET 16
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_CLEAR_MASK 0x00010000
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_ASSERT 0b0
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_DE_ASSERT 0b1
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_OFFSET 0
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_MASK 0x0
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_PASS 0b1
 
#define LVDS0_GAR_REG 0x00001544//LVDS0 Gating And Reset Register
#define LVDS0_GAR_REG_LVDS0_RST_N_OFFSET 16
#define LVDS0_GAR_REG_LVDS0_RST_N_CLEAR_MASK 0x00010000
#define LVDS0_GAR_REG_LVDS0_RST_N_ASSERT 0b0
#define LVDS0_GAR_REG_LVDS0_RST_N_DE_ASSERT 0b1
 
#define MIPI_DSI0_CLK_REG 0x00001580//MIPI_DSI0 Clock Register
#define MIPI_DSI0_CLK_REG_MIPI_DSI0_CLK_GATING_OFFSET 31
#define MIPI_DSI0_CLK_REG_MIPI_DSI0_CLK_GATING_CLEAR_MASK (0x80000000)
#define MIPI_DSI0_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define MIPI_DSI0_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_ON 0b1
#define MIPI_DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define MIPI_DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define MIPI_DSI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define MIPI_DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define MIPI_DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010
#define MIPI_DSI0_CLK_REG_FACTOR_M_OFFSET 0
#define MIPI_DSI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define MIPI_DSI0_GAR_REG 0x00001584//MIPI_DSI0 Gating And Reset Register
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_RST_N_OFFSET 16
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_RST_N_CLEAR_MASK 0x00010000
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_RST_N_ASSERT 0b0
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_RST_N_DE_ASSERT 0b1
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_AHB_CLK_EN_OFFSET 0
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_AHB_CLK_EN_MASK 0x0
#define MIPI_DSI0_GAR_REG_MIPI_DSI0_AHB_CLK_EN_PASS 0b1
 
#define COMBOPHY0_CLK_REG 0x000015c0//COMBOPHY0 Clock Register
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_OFFSET 31
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLEAR_MASK (0x80000000)
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_OFF 0b0
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_ON 0b1
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b001
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b010
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b011
#define COMBOPHY0_CLK_REG_FACTOR_M_OFFSET 0
#define COMBOPHY0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define VO0_REG_GAR_REG 0x000016c4//VO0_REG Gating And Reset Register
#define VO0_REG_GAR_REG_VO0_REG_RST_N_OFFSET 16
#define VO0_REG_GAR_REG_VO0_REG_RST_N_CLEAR_MASK 0x00010000
#define VO0_REG_GAR_REG_VO0_REG_RST_N_ASSERT 0b0
#define VO0_REG_GAR_REG_VO0_REG_RST_N_DE_ASSERT 0b1
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_OFFSET 0
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_MASK 0x0
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_PASS 0b1
 
#define VIDEO_OUT0_GAR_REG 0x000016e4//VIDEO_OUT0 Gating And Reset Register
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_OFFSET 16
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_CLEAR_MASK 0x00010000
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_ASSERT 0b0
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_DE_ASSERT 0b1
 
#define LEDC_CLK_REG 0x00001700//LEDC Clock Register
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK (0x80000000)
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b0
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1
#define LEDC_CLK_REG_FACTOR_M_OFFSET 0
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define LEDC_GAR_REG 0x00001704//LEDC Gating And Reset Register
#define LEDC_GAR_REG_LEDC_RST_N_OFFSET 16
#define LEDC_GAR_REG_LEDC_RST_N_CLEAR_MASK 0x00010000
#define LEDC_GAR_REG_LEDC_RST_N_ASSERT 0b0
#define LEDC_GAR_REG_LEDC_RST_N_DE_ASSERT 0b1
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_OFFSET 0
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_CLEAR_MASK 0x00000001
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_MASK 0x0
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_PASS 0b1
 
#define CSI_MASTER0_CLK_REG 0x00001800//CSI Master0 Clock Register
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK (0x80000000)
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b011
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define CSI_MASTER1_CLK_REG 0x00001804//CSI Master1 Clock Register
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK (0x80000000)
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b011
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define CSI_MASTER2_CLK_REG 0x00001808//CSI Master2 Clock Register
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK (0x80000000)
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b011
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define CSI_CLK_REG 0x00001840//CSI Clock Register
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK (0x80000000)
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define CSI_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b101
#define CSI_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110
#define CSI_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define ISP_CLK_REG 0x00001860//ISP Clock Register
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK (0x80000000)
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define ISP_CLK_REG_CLK_SRC_SEL_PERI1PLL2X 0b101
#define ISP_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110
#define ISP_CLK_REG_FACTOR_M_OFFSET 0
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)
 
#define VIDEO_IN_GAR_REG 0x00001884//VIDEO_IN Gating And Reset Register
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_OFFSET 16
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_CLEAR_MASK 0x00010000
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_ASSERT 0b0
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_DE_ASSERT 0b1
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_OFFSET 0
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_MASK 0x0
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_PASS 0b1
 
#define PERI0PLL_GATE_EN_REG 0x00001908//PERI0PLL Gate Enable Register
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK (0x08000000)
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK (0x04000000)
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK (0x00000800)
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000400)
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI1PLL_GATE_EN_REG 0x0000190c//PERI1PLL Gate Enable Register
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_OFFSET 28
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK (0x08000000)
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK (0x04000000)
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET 24
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET 22
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_OFFSET 12
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00001000
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000800)
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000400)
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET 6
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define VIDEOPLL_GATE_EN_REG 0x00001910//VIDEOPLL Gate Enable Register
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET 20
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET 4
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
 
#define AUDIOPLL_GATE_EN_REG 0x0000191c//AUDIOPLL Gate Enable Register
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_OFFSET 16
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_DISABLE 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_ENABLE 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_OFFSET 0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_AUTO 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI0PLL_GATE_STAT_REG 0x00001988//PERI0PLL Gate Status Register
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 27
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK (0x08000000)
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 26
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK (0x04000000)
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 25
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK (0x02000000)
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 24
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 23
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK (0x00800000)
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 22
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK (0x00400000)
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 21
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 20
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 19
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK (0x00080000)
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 18
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 17
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK (0x00020000)
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 16
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1
 
#define PERI1PLL_GATE_STAT_REG 0x0000198c//PERI1PLL Gate Status Register
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_OFFSET 28
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_CLEAR_MASK 0x10000000
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 27
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK (0x08000000)
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 26
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK (0x04000000)
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 25
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK (0x02000000)
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET 24
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK 0x01000000
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 23
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK (0x00800000)
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET 22
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK (0x00400000)
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 21
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 20
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK 0x00100000
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 19
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK (0x00080000)
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 18
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 17
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK (0x00020000)
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 16
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK 0x00010000
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1
 
#define VIDEOPLL_GATE_STAT_REG 0x00001990//VIDEOPLL Gate Status Register
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET 20
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK 0x00100000
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET 16
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE 0b1
 
#define AUDIOPLL_GATE_STAT_REG 0x0000199c//AUDIOPLL Gate Status Register
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_OFFSET 16
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_CLEAR_MASK 0x00010000
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_DISABLE 0b0
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_ENABLE 0b1
 
#define PLL_OPG_BYPASS_REG 0x00001a20//PLL Output Gate Bypass Register
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET 0
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK 0x00000001
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE 0b0
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE 0b1
 
#define AXI_MON_GAR_REG 0x00001c00//AXI MON Gating And Reset Register
#define AXI_MON_GAR_REG_RV_AXIMON_RST_N_OFFSET 16
#define AXI_MON_GAR_REG_RV_AXIMON_RST_N_CLEAR_MASK 0x00010000
#define AXI_MON_GAR_REG_RV_AXIMON_RST_N_ASSERT 0b0
#define AXI_MON_GAR_REG_RV_AXIMON_RST_N_DE_ASSERT 0b1
#define AXI_MON_GAR_REG_RV_AXIMON_CLK_EN_OFFSET 0
#define AXI_MON_GAR_REG_RV_AXIMON_CLK_EN_CLEAR_MASK 0x00000001
#define AXI_MON_GAR_REG_RV_AXIMON_CLK_EN_MASK 0x0
#define AXI_MON_GAR_REG_RV_AXIMON_CLK_EN_PASS 0b1
 
#define AHB_MON_GAR_REG 0x00001c04//AHB MON Gating And Reset Register
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_OFFSET 17
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_CLEAR_MASK (0x00020000)
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_ASSERT 0b0
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_DE_ASSERT 0b1
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_OFFSET 16
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_CLEAR_MASK 0x00010000
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_ASSERT 0b0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_DE_ASSERT 0b1
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_OFFSET 1
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_CLEAR_MASK (0x00000002)
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_MASK 0x0
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_PASS 0b1
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_OFFSET 0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_CLEAR_MASK 0x00000001
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_MASK 0x0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_PASS 0b1
 
#define CCU_SEC_SWITCH_REG 0x00001f00//CCU Security Switch Register
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK (0x00000004)
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK (0x00000002)
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1
 
#define DAP_REQ_CTRL_REG 0x00001f10//DAP REQ Control Register
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_OFFSET 0
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_CLEAR_MASK 0x00000001
 
#define PLL_CFG0_REG 0x00001f20//PLL Configuration0 Register
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK (0xffffffff)
 
#define PLL_CFG1_REG 0x00001f24//PLL Configuration1 Register
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK (0xffffffff)
 
#define PLL_CFG2_REG 0x00001f28//PLL Configuration2 Register
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK (0xffffffff)
 
#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c//PLL Lock Debug Control Register
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK (0x80000000)
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK (0x03f00000)
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL0 0b0000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL1 0b0001
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0011
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0111
 
#define CCU_FAN_GATE_REG 0x00001f30//CCU FANOUT CLOCK GATE Register
#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET 4
#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK 0x00000010
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK (0x00000008)
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK (0x00000004)
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK (0x00000002)
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1
 
#define CLK27M_FAN_REG 0x00001f34//CLK27M FANOUT Register
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK (0x80000000)
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK (0x03000000)
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK (0x00001f00)
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK (0x0000001f)
 
#define CLK_FAN_REG 0x00001f38//CLK FANOUT Register
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK (0x80000000)
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1
#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK (0x000003e0)
#define CLK_FAN_REG_PCLK_DIV_OFFSET 0
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK (0x0000001f)
 
#define CCU_FAN_REG 0x00001f3c//CCU FANOUT Register
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_OFFSET 31
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_CLEAR_MASK (0x80000000)
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_PERI0_160M_10 0b0
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_RC_16M 0b1
#define CCU_FAN_REG_FANOUT_CLK2_EN_OFFSET 23
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLEAR_MASK (0x00800000)
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK1_EN_OFFSET 22
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLEAR_MASK (0x00400000)
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK0_EN_OFFSET 21
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLEAR_MASK (0x00200000)
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK2_SEL_OFFSET 6
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLEAR_MASK (0x000001c0)
#define CCU_FAN_REG_FANOUT_CLK2_SEL_FANOUT_32K_CLK_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK2_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_FANOUT_CLK1_SEL_OFFSET 3
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLEAR_MASK (0x00000038)
#define CCU_FAN_REG_FANOUT_CLK1_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK1_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_FANOUT_CLK0_SEL_OFFSET 0
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLEAR_MASK (0x00000007)
#define CCU_FAN_REG_FANOUT_CLK0_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK0_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK50M_FROM_PERI0_150M_3 0b111
 
#define CLK_DBG_REG 0x00001f50//Clock Debug Register
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_OFFSET 24
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_CLEAR_MASK (0x03000000)
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV1 0b00
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV2 0b01
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV4 0b10
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV8 0b11
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_OFFSET 16
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_CLEAR_MASK (0x00070000)
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_STBY_SYS_BACKDOOR_CLK 0b000
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_OFFSET 4
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CLEAR_MASK (0x000001f0)
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_0 0b0000
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_1 0b0001
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_2 0b0010
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_3 0b0011
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK (0x00000007)
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLK 0b000
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLK 0b001
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLK 0b010
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLK 0b011
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLK 0b100
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CE_SYS_CLK 0b101
 
#define FRE_DET_CTRL_REG 0x00001f60//Frequence Detect Control Register
#define FRE_DET_CTRL_REG_ERROR_FLAG_OFFSET 31
#define FRE_DET_CTRL_REG_ERROR_FLAG_CLEAR_MASK (0x80000000)
#define FRE_DET_CTRL_REG_ERROR_FLAG_WRITE_0_TO_CLEAR 0b0
#define FRE_DET_CTRL_REG_ERROR_FLAG_ERROR 0b1
#define FRE_DET_CTRL_REG_DET_TIME_OFFSET 4
#define FRE_DET_CTRL_REG_DET_TIME_CLEAR_MASK (0x000001f0)
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_OFFSET 1
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_CLEAR_MASK (0x00000002)
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_DISABLE 0b0
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_ENABLE 0b1
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_OFFSET 0
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_CLEAR_MASK 0x00000001
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_DISABLE 0b0
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_ENABLE 0b1
 
#define FRE_UP_LIM_REG 0x00001f64//Frequence Up Limit Register
#define FRE_UP_LIM_REG_FRE_UP_LIM_OFFSET 0
#define FRE_UP_LIM_REG_FRE_UP_LIM_CLEAR_MASK (0xffffffff)
 
#define FRE_DOWN_LIM_REG 0x00001f68//Frequence Down Limit Register
#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_OFFSET 0
#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_CLEAR_MASK (0xffffffff)
 
#define CCU_VERSION_REG 0x00001ff0//CCU Version Register
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK (0xffff0000)
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK (0x0000ffff)
 
#define CCMU_UART_BGR_REG (SUNXI_CCM_BASE + UART0_GAR_REG)
 
#define CCMU_SMHC0_BGR_REG (SUNXI_CCM_BASE + SMHC0_GAR_REG)
#define CCMU_SDMMC0_CLK_REG (SUNXI_CCM_BASE + SMHC0_CLK_REG)
#define CCMU_SDMMC2_CLK_REG (SUNXI_CCM_BASE + SMHC2_CLK_REG)
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET SMHC0_GAR_REG_SMHC0_RST_N_OFFSET
#define CCMU_PLL_PERI0_CTRL_REG (SUNXI_CCM_BASE + PLL_PERI0_CTRL_REG)
#define GPIO_POW_MODE_REG 0x40
 
/*gpadc gate and reset reg*/
#define CCMU_GPADC_CLK_REG (SUNXI_CCM_BASE + GPADC0_CLK_REG)
#define CCMU_GPADC_BGR_REG (SUNXI_CCM_BASE + GPADC0_GAR_REG)
 
/* ce */
#define CE_USE_PLATFORM_CLOCK_FUNC
#define SUNXI_CE_MBUS_MST_CLK_AUTO_GATE_EN_REG (SUNXI_CCM_BASE + MBUS_MAT_CLK_AUTO_GATE_EN_REG)
#define SUNXI_CE_MBUS_MAT_CLK_AUTO_GATE_OFFSET MBUS_MAT_CLK_AUTO_GATE_EN_REG_CE_SYS_MBUS_AUTO_GATE_EN_OFFSET
 
#define SUNXI_CE_MBUS_MST_CLK_GATE_EN_REG (SUNXI_CCM_BASE + MBUS_MAT_CLK_GATE_EN_REG)
#define SUNXI_CE_MBUS_MST_CLK_GATE_OFFSET MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_MBUS_GATE_SW_CFG_OFFSET
 
#define SUNXI_CE_MBUS_CLK_GATE_EN_REG (SUNXI_CCM_BASE + MBUS_CLK_GATE_EN_REG)
#define SUNXI_CE_MBUS_CLK_GATE_OFFSET MBUS_CLK_GATE_EN_REG_CE_SYS_MBUS_CLK_EN_OFFSET
 
#define SUNXI_CE_SYS_CLK_REG (SUNXI_CCM_BASE + CE_SYS_CLK_REG)
#define SUNXI_CE_SRC CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M
#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET
#define SUNXI_CE_FACTOR (0b0)
#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET CE_SYS_CLK_REG_FACTOR_M_OFFSET
#define SUNXI_CE_SYS_GATING_OFFSET CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET
 
#define SUNXI_CE_RESET_REG (SUNXI_CCM_BASE + CE_SYS_GAR_REG)
#define SUNXI_CE_RESET_OFFSET CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET
 
#define SUNXI_CE_GATING_REG (SUNXI_CCM_BASE + CE_SYS_GAR_REG)
#define SUNXI_CE_GATING_OFFSET CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET
 
/* bus */
#define CLU_CLK_REG (SUNXI_CPUX_PLL_CFG_BASE + 0x18)
#define CLU_CLK_DIV_CFG_REG (SUNXI_CPUX_PLL_CFG_BASE + 0x20)
#define CCMU_PLL_CPU_CTRL_REG (SUNXI_CCM_BASE + PLL_CPU_CTRL_REG)
#define CCMU_AHB_CLK_REG (SUNXI_CCM_BASE + AHB_CLK_REG)
#define CCMU_APB0_CLK_REG (SUNXI_CCM_BASE + APB0_CLK_REG)
#define CCMU_APB1_CLK_REG (SUNXI_CCM_BASE + APB1_CLK_REG)
#define CCMU_MBUS_CLK_REG (SUNXI_CCM_BASE + MBUS_CLK_REG)
 
 
#endif// __SUN8IW22_REG_CCU_H__