d2/d5b/chips_2sun65iw1_2reg-ncat_8h_source.html

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * (C) Copyright 2013-2025

 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>

 *

 * original from bsp uboot defines

 */


#ifndef __SUN65IW1_REG_NCAT_H__

#define __SUN65IW1_REG_NCAT_H__


#define SUNXI_FIXS_BROM_BASE 0x00000000

#define SUNXI_HS_BROM_BASE 0x00010000

#define SUNXI_NS_BROM_BASE 0x00015000

#define SUNXI_SRAM_A2_BASE 0x00044000

#define SUNXI_GPU_BASE 0x01800000

#define SUNXI_VE0_BASE 0x01C0E000

#define SUNXI_IOMMU_BASE 0x02000000

#define SUNXI_NSI_BASE 0x02400000

#define SUNXI_NSI_CPU_BASE 0x02410000

#define SUNXI_NPD_BASE 0x02430000

#define SUNXI_AXI_MONITOR_GPU_BASE 0x02500000

#define SUNXI_AXI_MONITOR_CE_SYS_BASE 0x02501000

#define SUNXI_AXI_MONITOR_HSI_BASE 0x02502000

#define SUNXI_AXI_MONITOR_GMAC0_BASE 0x02503000

#define SUNXI_AHB_MONITOR_CPU_BASE 0x02510000

#define SUNXI_AHB_MONITOR_DCU_BASE 0x02511000

#define SUNXI_IR_TX_BASE 0x02800000

#define SUNXI_IR_RX0_BASE 0x02808000

#define SUNXI_PWM0_BASE 0x02810000

#define SUNXI_TSENSOR_BASE 0x02818000

#define SUNXI_GPADC_BASE 0x02820000

#define SUNXI_LRADC_BASE 0x02828000

#define SUNXI_TPADC_BASE 0x02829000

#define SUNXI_LEDC_BASE 0x02830000

#define SUNXI_I2S0_BASE 0x02900000

#define SUNXI_I2S1_BASE 0x02901000

#define SUNXI_I2S2_BASE 0x02902000

#define SUNXI_I2S3_BASE 0x02903000

#define SUNXI_AUDIOCODEC0_BASE 0x02908000

#define SUNXI_AUDIOCODEC1_BASE 0x02909000

#define SUNXI_DMIC_BASE 0x02910000

#define SUNXI_OWA0_BASE 0x02918000

#define SUNXI_TWI0_BASE 0x02A00000

#define SUNXI_TWI1_BASE 0x02A01000

#define SUNXI_TWI2_BASE 0x02A02000

#define SUNXI_TWI3_BASE 0x02A03000

#define SUNXI_TWI4_BASE 0x02A04000

#define SUNXI_TWI5_BASE 0x02A05000

#define SUNXI_UART0_BASE 0x02B00000

#define SUNXI_UART1_BASE 0x02B01000

#define SUNXI_UART2_BASE 0x02B02000

#define SUNXI_UART3_BASE 0x02B03000

#define SUNXI_UART4_BASE 0x02B04000

#define SUNXI_UART5_BASE 0x02B05000

#define SUNXI_UART6_BASE 0x02B06000

#define SUNXI_UART7_BASE 0x02B07000

#define SUNXI_SPI0_BASE 0x02C00000

#define SUNXI_SPI1_BASE 0x02C01000

#define SUNXI_SPI2_BASE 0x02C02000

#define SUNXI_GPIO_BASE 0x03000000

#define SUNXI_CCU_BASE 0x03008000

#define SUNXI_WDT_CPUX_BASE 0x03010000

#define SUNXI_INT_GROUP_BASE 0x03018000

#define SUNXI_TIMER1_BASE 0x0320C000

#define SUNXI_SYSCTRL_BASE 0x03200000

#define SUNXI_TIMER0_BASE 0x03208000

#define SUNXI_MSGBOX_CPUX_BASE 0x03210000

#define SUNXI_MSGBOX_CPUS_BASE 0x03211000

#define SUNXI_SPINLOCK_BASE 0x03220000

#define SUNXI_DMA0_BASE 0x03228000

#define SUNXI_DCU_BASE 0x03230000

#define SUNXI_SPC_BASE 0x03400000

#define SUNXI_SID_BASE 0x03408000

#define SUNXI_CE_SYS_BASE 0x03412000

#define SUNXI_SMHC0_BASE 0x04008000

#define SUNXI_SMHC1_BASE 0x04009000

#define SUNXI_SMHC2_BASE 0x0400A000

#define SUNXI_CSIC_BASE 0x04800000

#define SUNXI_ISP_BASE 0x04900000

#define SUNXI_DE0_BASE 0x05000000

#define SUNXI_G2D_BASE 0x05440000

#define SUNXI_EINK_BASE 0x05480000

#define SUNXI_VIDEO_OUT0_SYS_BASE 0x05A00000

#define SUNXI_TCON_LCD0_BASE 0x05A08000

#define SUNXI_MIPI_DSI0_BASE 0x05A10000

#define SUNXI_VIDEO_OUT1_SYS_BASE 0x05C00000

#define SUNXI_TCON_TV0_BASE 0x05C08000

#define SUNXI_EDP0_BASE 0x05C10000

#define SUNXI_CPUIDLE_BASE 0x07000000

#define SUNXI_DVFS_AVS_BASE 0x07010000

#define SUNXI_CPUS_CFG_BASE 0x07018000

#define SUNXI_CPUS_CLIC_BASE 0x07019000

#define SUNXI_S_SPC_BASE 0x07020000

#define SUNXI_TZMA_BASE 0x07028000

#define SUNXI_S_PRCM_BASE 0x07030000

#define SUNXI_WDT_CPUS_BASE 0x07040000

#define SUNXI_TWD_BASE 0x07048000

#define SUNXI_S_GPIO_BASE 0x07058000

#define SUNXI_PPU_BASE 0x07060000

#define SUNXI_S_PWM0_BASE 0x070A0000

#define SUNXI_S_IR_RX_BASE 0x070A8000

#define SUNXI_S_UART0_BASE 0x07100000

#define SUNXI_S_UART1_BASE 0x07101000

#define SUNXI_S_TWI0_BASE 0x07108000

#define SUNXI_S_TWI1_BASE 0x07109000

#define SUNXI_S_TWI2_BASE 0x0710A000

#define SUNXI_SYSRTC_BASE 0x07200000

#define SUNXI_S_TIMER0_BASE 0x07208000

#define SUNXI_S_SPI0_BASE 0x07280000

#define SUNXI_GIC_BASE 0x08000000

#define SUNXI_CPUX_SYS_DP_BASE 0x08100000

#define SUNXI_CPUX_PLL_CFG_BASE_BASE 0x08200000

#define SUNXI_CPUX_SUBSYS_CTRL_BASE 0x08210000

#define SUNXI_CPUX_TIMESTAMP_STA_BASE 0x08220000

#define SUNXI_CPUX_TIMESTAMP_CTRL_BASE 0x08230000

#define SUNXI_CPUX_CXCTI_BASE 0x08350000

#define SUNXI_CPUX_CLU0_CFG_BASE 0x08810000

#define SUNXI_CPUX_CLU0_DEBUG_BASE_BASE 0x08C00000

#define SUNXI_CPUX_CLU1_CFG_BASE 0x09010000

#define SUNXI_CPUX_CLU1_DEBUG_BASE_BASE 0x09400000

#define SUNXI_CPUX_CLU2_CFG_BASE 0x09810000

#define SUNXI_CPUX_CLU2_DEBUG_BASE_BASE 0x09C00000

#define SUNXI_DRAMC_BASE 0x0A000000

#define SUNXI_DRAMC_SMC_BASE 0x0A000000

#define SUNXI_DRAMC_COMMON_BASE 0x0A010000

#define SUNXI_DRAMC_DDRC_BASE 0x0A020000

#define SUNXI_DRAMC_PHY_BASE 0x0A030000

#define SUNXI_HSI_SYS_BASE 0x0C000000

#define SUNXI_USB2P0_SYS_BASE 0x0C000000

#define SUNXI_USB2P0_PHY_BASE 0x0C000000

#define SUNXI_USB2P0_SYS_DIG_BASE 0x0C080000

#define SUNXI_USB0_BASE 0x0C100000

#define SUNXI_USB1_BASE 0x0C200000

#define SUNXI_USB2_BASE 0x0C400000

#define SUNXI_PCIE0_BASE 0x0C800000

#define SUNXI_HSI_SYS_DIS_APP_BASE 0x0DC80000

#define SUNXI_HSI_COMB0_PHY_BASE 0x0DD00000

#define SUNXI_GMAC0_BASE 0x0DE00000


#define CONFIG_SYS_SRAMA2_BASE (SUNXI_SRAM_A2_BASE)

#define CONFIG_SYS_SRAMA2_SIZE (0x28000)


#define SUNXI_PIO_BASE (SUNXI_GPIO_BASE)

#define SUNXI_R_PIO_BASE (SUNXI_S_GPIO_BASE)

#define SUNXI_CCM_BASE (SUNXI_CCU_BASE)

#define SUNXI_DMA_BASE (SUNXI_DMA0_BASE)

#define SUNXI_CE_BASE (SUNXI_CE_SYS_BASE)

#define SUNXI_SS_BASE (SUNXI_CE_BASE)

#define SUNXI_CPUXCFG_BASE (SUNXI_CPU_SUBSYS_CTRL_BASE)

#define SUNXI_SYSCRL_BASE (SUNXI_SYSCTRL_BASE)

#define SUNXI_KEYADC_BASE (SUNXI_LRADC_BASE)

#define SUNXI_RPRCM_BASE (SUNXI_S_PRCM_BASE)

#define SUNXI_RPWM_BASE (SUNXI_R_PWM_BASE)

#define SUNXI_RPIO_BASE (SUNXI_S_GPIO_BASE)


#define SUNXI_RTWI_BASE (SUNXI_S_TWI0_BASE)

#define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c)

#define SUNXI_RTWI0_RST_BIT (16)

#define SUNXI_RTWI0_GATING_BIT (0)

#define SUNXI_RST_BIT (16)

#define SUNXI_GATING_BIT (0)

#define SUNXI_RTC_BASE SUNXI_SYSRTC_BASE

#define SUNXI_RTC_DATA_BASE (SUNXI_SYSRTC_BASE + 0x100)

#define SUNXI_SMC_BASE (SUNXI_DRAMC_BASE)

#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE)

#define SUNXI_CCI_BASE (SUNXI_CPUX_SYS_DP_BASE)

#define SUNXI_TIMESTAMP_CTRL_BASE (SUNXI_CPUX_TIMESTAMP_CTRL_BASE)

#define SUNXI_CPU_SUBSYS_CTRL_BASE (SUNXI_CPUX_SUBSYS_CTRL_BASE)


/* use for usb correct */

#define VDD_ADDA_OFF_GATING (9)

#define CAL_ANA_EN (1)

#define CAL_EN (0)


#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x44)

#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x48)


#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0)

#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4)


#define GPIO_BIAS_MAX_LEN (32)

#define GPIO_BIAS_MAIN_NAME "gpio_bias"

#define GPIO_POW_MODE_REG (0x0380)

#define GPIO_POW_MS_CTL (0x0384)

#define GPIO_POW_MODE_VAL_REG (0x0388)

#define GPIO_3_3V_MODE 0

#define GPIO_1_8V_MODE 1


/* CCI related constants */

#define PLAT_ARM_CCI_BASE SUNXI_CCI_BASE

#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 0

#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 1

#define PLAT_ARM_CCI_CLUSTER2_SL_IFACE_IX 2


#define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)


#define SUNXI_SOC_VER_REG (SUNXI_SYSCTRL_BASE + 0x24)

#define SUNXI_SOC_VER_MASK (0x7)


#define SID_RES0_1_BASE (SUNXI_SID_BASE + 0x240)

#define RESCAL_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x160)


#define INT_DSI_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x170)

#define INT_CSI_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x174)

#define INT_USB_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x178)


#define INT_EDP_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x180)

#define INT_HS_COMBO_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x184)

#define INT_DDR_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x188)


#endif// __SUN65IW1_REG_NCAT_H__