SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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barrier.h
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1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __ARM32_BARRIER_H__
4#define __ARM32_BARRIER_H__
5
6#ifdef __cplusplus
7extern "C" {
8#endif
9
10#if __ARM32_ARCH__ == 5
11#define isb() __asm__ __volatile__("" \
12 : \
13 : \
14 : "memory")
15#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
16 : \
17 : "r"(0) \
18 : "memory")
19#define dmb() __asm__ __volatile__("" \
20 : \
21 : \
22 : "memory")
23#elif __ARM32_ARCH__ == 6
24#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
25 : \
26 : "r"(0) \
27 : "memory")
28#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
29 : \
30 : "r"(0) \
31 : "memory")
32#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
33 : \
34 : "r"(0) \
35 : "memory")
36#else
37#define isb() __asm__ __volatile__("isb sy" \
38 : \
39 : \
40 : "memory")
41#define dsb() __asm__ __volatile__("dsb sy" \
42 : \
43 : \
44 : "memory")
45#define dmb() __asm__ __volatile__("dmb sy" \
46 : \
47 : \
48 : "memory")
49#endif
50
51/* Read and write memory barrier */
52#define mb() dsb()
53/* Read memory barrier */
54#define rmb() dsb()
55/* Write memory barrier */
56#define wmb() dsb()
57
58/* SMP read and write memory barrier */
59#define smp_mb() dmb()
60/* SMP read memory barrier */
61#define smp_rmb() dmb()
62/* SMP write memory barrier */
63#define smp_wmb() dmb()
64
65#ifdef __cplusplus
66}
67#endif
68
69#endif /* __ARM32_BARRIER_H__ */
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