cache.h

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/* SPDX-License-Identifier: GPL-2.0+ */
 
#ifndef __CACHE_H__
#define __CACHE_H__
 
#include <stdint.h>
#include "barrier.h"
 
static inline void arm32_dcache_enable(void);
 
static inline void arm32_dcache_disable(void);
 
static inline void arm32_icache_enable(void);
 
static inline void arm32_icache_disable(void);
 
static inline void flush_dcache_range(uint64_t start, uint64_t end);
 
static inline void invalidate_dcache_range(uint64_t start, uint64_t end);
 
static inline void flush_dcache_all();
 
static inline void invalidate_dcache_all();
 
static inline void data_sync_barrier(void) {
    dsb();
}
 
/* Function implementations */
 
static inline void arm32_dcache_enable(void) {
    uint32_t value;
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
    value |= (1 << 2);
    __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0"
                         :
                         : "r"(value)
                         : "memory");
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
}
 
static inline void arm32_dcache_disable(void) {
    uint32_t value;
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
    value &= ~(1 << 2);
    __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0"
                         :
                         : "r"(value)
                         : "memory");
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
}
 
static inline void arm32_icache_enable(void) {
    uint32_t value;
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
    value |= (1 << 12);
    __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0"
                         :
                         : "r"(value)
                         : "memory");
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
}
 
static inline void arm32_icache_disable(void) {
    uint32_t value;
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
    value &= ~(1 << 12);
    __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0"
                         :
                         : "r"(value)
                         : "memory");
    __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0"
                         : "=r"(value)
                         :
                         : "memory");
}
 
static inline void flush_dcache_range(uint64_t start, uint64_t end) {
    /* Ensure addresses are cache line aligned */
    uint32_t line_size = 32; /* Assume 32-byte cache line size, may need adjustment for specific processors */
    uint32_t aligned_start = (uint32_t) start & ~(line_size - 1);
    uint32_t aligned_end = ((uint32_t) end + line_size - 1) & ~(line_size - 1);
    uint32_t addr;
 
    /* Iterate through cache lines and flush */
    for (addr = aligned_start; addr < aligned_end; addr += line_size) {
        __asm__ __volatile__(
                "mcr p15, 0, %0, c7, c14, 1" /* Clean data cache line */
                :
                : "r"(addr)
                : "memory");
    }
 
    /* Ensure all operations are complete */
    data_sync_barrier();
}
 
static inline void invalidate_dcache_range(uint64_t start, uint64_t end) {
    /* Ensure addresses are cache line aligned */
    uint32_t line_size = 32; /* Assume 32-byte cache line size */
    uint32_t aligned_start = (uint32_t) start & ~(line_size - 1);
    uint32_t aligned_end = ((uint32_t) end + line_size - 1) & ~(line_size - 1);
    uint32_t addr;
 
    /* Iterate through cache lines and invalidate */
    for (addr = aligned_start; addr < aligned_end; addr += line_size) {
        __asm__ __volatile__(
                "mcr p15, 0, %0, c7, c6, 1" /* Invalidate data cache line */
                :
                : "r"(addr)
                : "memory");
    }
 
    /* Ensure all operations are complete */
    data_sync_barrier();
}
 
static inline void flush_dcache_all() {
    /* Ensure all operations are complete */
    data_sync_barrier();
}
 
static inline void invalidate_dcache_all() {
    /* Ensure all operations are complete */
    data_sync_barrier();
}
 
#endif /* __CACHE_H__ */