linkage.h File Reference

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Macros
#define	ALIGN   .align 0
#define	ALIGN_STR   ".align 0"
#define	ENTRY(name)
#define	WEAK(name)
#define	END(name)   .size name, .- name
#define	ENDPROC(name)
#define	CR_M   (1 << 0) /* MMU enable */
#define	CR_A   (1 << 1) /* Alignment abort enable */
#define	CR_C   (1 << 2) /* Dcache enable */
#define	CR_W   (1 << 3) /* Write buffer enable */
#define	CR_P   (1 << 4) /* 32-bit exception handler */
#define	CR_D   (1 << 5) /* 32-bit data address range */
#define	CR_L   (1 << 6) /* Implementation defined */
#define	CR_B   (1 << 7) /* Big endian */
#define	CR_S   (1 << 8) /* System MMU protection */
#define	CR_R   (1 << 9) /* ROM MMU protection */
#define	CR_F   (1 << 10) /* Implementation defined */
#define	CR_Z   (1 << 11) /* Implementation defined */
#define	CR_I   (1 << 12) /* Icache enable */
#define	CR_V   (1 << 13) /* Vectors relocated to 0xffff0000 */
#define	CR_RR   (1 << 14) /* Round Robin cache replacement */
#define	CR_L4   (1 << 15) /* LDR pc can set T bit */
#define	CR_DT   (1 << 16)
#define	CR_IT   (1 << 18)
#define	CR_ST   (1 << 19)
#define	CR_FI   (1 << 21) /* Fast interrupt (lower latency mode) */
#define	CR_U   (1 << 22) /* Unaligned access operation */
#define	CR_XP   (1 << 23) /* Extended page tables */
#define	CR_VE   (1 << 24) /* Vectored interrupts */
#define	CR_EE   (1 << 25) /* Exception (Big) Endian */
#define	CR_TRE   (1 << 28) /* TEX remap enable */
#define	CR_AFE   (1 << 29) /* Access flag enable */
#define	CR_TE   (1 << 30) /* Thumb exception enable */
#define	R_ARM_NONE   0 /* No reloc */
#define	R_ARM_RELATIVE   23 /* Adjust by program base */

Macro Definition Documentation

ALIGN

#define ALIGN   .align 0

ALIGN_STR

#define ALIGN_STR   ".align 0"

CR_A

#define CR_A   (1 << 1) /* Alignment abort enable */

CR_AFE

#define CR_AFE   (1 << 29) /* Access flag enable */

CR_B

#define CR_B   (1 << 7) /* Big endian */

CR_C

#define CR_C   (1 << 2) /* Dcache enable */

CR_D

#define CR_D   (1 << 5) /* 32-bit data address range */

CR_DT

#define CR_DT   (1 << 16)

CR_EE

#define CR_EE   (1 << 25) /* Exception (Big) Endian */

CR_F

#define CR_F   (1 << 10) /* Implementation defined */

CR_FI

#define CR_FI   (1 << 21) /* Fast interrupt (lower latency mode) */

CR_I

#define CR_I   (1 << 12) /* Icache enable */

CR_IT

#define CR_IT   (1 << 18)

CR_L

#define CR_L   (1 << 6) /* Implementation defined */

CR_L4

#define CR_L4   (1 << 15) /* LDR pc can set T bit */

CR_M

#define CR_M   (1 << 0) /* MMU enable */

CR_P

#define CR_P   (1 << 4) /* 32-bit exception handler */

CR_R

#define CR_R   (1 << 9) /* ROM MMU protection */

CR_RR

#define CR_RR   (1 << 14) /* Round Robin cache replacement */

CR_S

#define CR_S   (1 << 8) /* System MMU protection */

CR_ST

#define CR_ST   (1 << 19)

CR_TE

#define CR_TE   (1 << 30) /* Thumb exception enable */

CR_TRE

#define CR_TRE   (1 << 28) /* TEX remap enable */

CR_U

#define CR_U   (1 << 22) /* Unaligned access operation */

CR_V

#define CR_V   (1 << 13) /* Vectors relocated to 0xffff0000 */

CR_VE

#define CR_VE   (1 << 24) /* Vectored interrupts */

CR_W

#define CR_W   (1 << 3) /* Write buffer enable */

CR_XP

#define CR_XP   (1 << 23) /* Extended page tables */

CR_Z

#define CR_Z   (1 << 11) /* Implementation defined */

END

#define END

(

name

)

.size name, .- name

ENDPROC

#define ENDPROC

(

name

)

Value:

    .type name, % function; \
    END(name)

ENTRY

#define ENTRY

(

name

)

Value:

    .globl name;    \
    ALIGN;          \
    name:

R_ARM_NONE

#define R_ARM_NONE   0 /* No reloc */

R_ARM_RELATIVE

#define R_ARM_RELATIVE   23 /* Adjust by program base */

WEAK

#define WEAK

(

name

)

Value:

    .weak name;    \
    name: