#include <reg-ncat.h>

Include dependency graph for reg-dma.h:

This graph shows which files directly or indirectly include this file:

Macros
#define	SUNXI_DMA_CHANNEL_BASE (SUNXI_DMA_BASE + 0x100)

#define	DMA_AUTO_GATE_REG (SUNXI_DMA_BASE + 0x28)

#define	SUNXI_DMA_CHANNEL_SIZE (0x40)

#define	SUNXI_DMA_LINK_NULL (0xfffff800)

#define	DMAC_DMATYPE_NORMAL 0

#define	DMAC_CFG_TYPE_DRAM (1)

#define	DMAC_CFG_TYPE_SRAM (0)

#define	DMAC_CFG_TYPE_SPI0 (22)

#define	DMAC_CFG_TYPE_SHMC0 (20)

#define	DMAC_CFG_SRC_TYPE_NAND (5)

#define	DMAC_CFG_CONTINUOUS_ENABLE (0x01)

#define	DMAC_CFG_CONTINUOUS_DISABLE (0x00)

#define	DMAC_CFG_DEST_DATA_WIDTH_8BIT (0x00)

#define	DMAC_CFG_DEST_DATA_WIDTH_16BIT (0x01)

#define	DMAC_CFG_DEST_DATA_WIDTH_32BIT (0x02)

#define	DMAC_CFG_DEST_DATA_WIDTH_64BIT (0x03)

#define	DMAC_CFG_DEST_1_BURST (0x00)

#define	DMAC_CFG_DEST_4_BURST (0x01)

#define	DMAC_CFG_DEST_8_BURST (0x02)

#define	DMAC_CFG_DEST_16_BURST (0x03)

#define	DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE (0x00)

#define	DMAC_CFG_DEST_ADDR_TYPE_IO_MODE (0x01)

#define	DMAC_CFG_SRC_DATA_WIDTH_8BIT (0x00)

#define	DMAC_CFG_SRC_DATA_WIDTH_16BIT (0x01)

#define	DMAC_CFG_SRC_DATA_WIDTH_32BIT (0x02)

#define	DMAC_CFG_SRC_DATA_WIDTH_64BIT (0x03)

#define	DMAC_CFG_SRC_1_BURST (0x00)

#define	DMAC_CFG_SRC_4_BURST (0x01)

#define	DMAC_CFG_SRC_8_BURST (0x02)

#define	DMAC_CFG_SRC_16_BURST (0x03)

#define	DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE (0x00)

#define	DMAC_CFG_SRC_ADDR_TYPE_IO_MODE (0x01)

#define	DMA_PKG_HALF_INT (1 << 0)

#define	DMA_PKG_END_INT (1 << 1)

#define	DMA_QUEUE_END_INT (1 << 2)

Macro Definition Documentation

◆ DMA_AUTO_GATE_REG

#define DMA_AUTO_GATE_REG (SUNXI_DMA_BASE + 0x28)

◆ DMA_PKG_END_INT

#define DMA_PKG_END_INT (1 << 1)

◆ DMA_PKG_HALF_INT

#define DMA_PKG_HALF_INT (1 << 0)

◆ DMA_QUEUE_END_INT

#define DMA_QUEUE_END_INT (1 << 2)

◆ DMAC_CFG_CONTINUOUS_DISABLE

#define DMAC_CFG_CONTINUOUS_DISABLE (0x00)

◆ DMAC_CFG_CONTINUOUS_ENABLE

#define DMAC_CFG_CONTINUOUS_ENABLE (0x01)

◆ DMAC_CFG_DEST_16_BURST

#define DMAC_CFG_DEST_16_BURST (0x03)

◆ DMAC_CFG_DEST_1_BURST

#define DMAC_CFG_DEST_1_BURST (0x00)

◆ DMAC_CFG_DEST_4_BURST

#define DMAC_CFG_DEST_4_BURST (0x01)

◆ DMAC_CFG_DEST_8_BURST

#define DMAC_CFG_DEST_8_BURST (0x02)

◆ DMAC_CFG_DEST_ADDR_TYPE_IO_MODE

#define DMAC_CFG_DEST_ADDR_TYPE_IO_MODE (0x01)

◆ DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE

#define DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE (0x00)

◆ DMAC_CFG_DEST_DATA_WIDTH_16BIT

#define DMAC_CFG_DEST_DATA_WIDTH_16BIT (0x01)

◆ DMAC_CFG_DEST_DATA_WIDTH_32BIT

#define DMAC_CFG_DEST_DATA_WIDTH_32BIT (0x02)

◆ DMAC_CFG_DEST_DATA_WIDTH_64BIT

#define DMAC_CFG_DEST_DATA_WIDTH_64BIT (0x03)

◆ DMAC_CFG_DEST_DATA_WIDTH_8BIT

#define DMAC_CFG_DEST_DATA_WIDTH_8BIT (0x00)

◆ DMAC_CFG_SRC_16_BURST

#define DMAC_CFG_SRC_16_BURST (0x03)

◆ DMAC_CFG_SRC_1_BURST

#define DMAC_CFG_SRC_1_BURST (0x00)

◆ DMAC_CFG_SRC_4_BURST

#define DMAC_CFG_SRC_4_BURST (0x01)

◆ DMAC_CFG_SRC_8_BURST

#define DMAC_CFG_SRC_8_BURST (0x02)

◆ DMAC_CFG_SRC_ADDR_TYPE_IO_MODE

#define DMAC_CFG_SRC_ADDR_TYPE_IO_MODE (0x01)

◆ DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE

#define DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE (0x00)

◆ DMAC_CFG_SRC_DATA_WIDTH_16BIT

#define DMAC_CFG_SRC_DATA_WIDTH_16BIT (0x01)

◆ DMAC_CFG_SRC_DATA_WIDTH_32BIT

#define DMAC_CFG_SRC_DATA_WIDTH_32BIT (0x02)

◆ DMAC_CFG_SRC_DATA_WIDTH_64BIT

#define DMAC_CFG_SRC_DATA_WIDTH_64BIT (0x03)

◆ DMAC_CFG_SRC_DATA_WIDTH_8BIT

#define DMAC_CFG_SRC_DATA_WIDTH_8BIT (0x00)

◆ DMAC_CFG_SRC_TYPE_NAND

#define DMAC_CFG_SRC_TYPE_NAND (5)

◆ DMAC_CFG_TYPE_DRAM

#define DMAC_CFG_TYPE_DRAM (1)

◆ DMAC_CFG_TYPE_SHMC0

#define DMAC_CFG_TYPE_SHMC0 (20)

◆ DMAC_CFG_TYPE_SPI0

#define DMAC_CFG_TYPE_SPI0 (22)

◆ DMAC_CFG_TYPE_SRAM

#define DMAC_CFG_TYPE_SRAM (0)

◆ DMAC_DMATYPE_NORMAL

#define DMAC_DMATYPE_NORMAL 0

◆ SUNXI_DMA_CHANNEL_BASE

#define SUNXI_DMA_CHANNEL_BASE (SUNXI_DMA_BASE + 0x100)

◆ SUNXI_DMA_CHANNEL_SIZE

#define SUNXI_DMA_CHANNEL_SIZE (0x40)

◆ SUNXI_DMA_LINK_NULL

#define SUNXI_DMA_LINK_NULL (0xfffff800)

Macros