SyterKit
0.4.0.x
SyterKit is a bare-metal framework
Loading...
Searching...
No Matches
include
drivers
chips
sun8iw20
reg-rproc.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0+ */
2
3
#ifndef __REG_RPROC_H__
4
#define __REG_RPROC_H__
5
6
/*
7
* DSP CFG Register
8
*/
9
#define DSP0_CFG_BASE (0x01700000)
10
11
/* DSP default reset vector address */
12
#define DSP_DEFAULT_RST_VEC (0x100000)
13
14
/*
15
* DSP Register define
16
*/
17
#define DSP_ALT_RESET_VEC_REG (0x0000)
/* DSP Reset Control Register */
18
#define DSP_CTRL_REG0 (0x0004)
/* DSP Control Register0 */
19
#define DSP_PRID_REG (0x000c)
/* DSP PRID Register */
20
#define DSP_STAT_REG (0x0010)
/* DSP STAT Register */
21
#define DSP_BIST_CTRL_REG (0x0014)
/* DSP BIST CTRL Register */
22
#define DSP_JTRST_REG (0x001c)
/* DSP JTAG CONFIG RESET Register */
23
#define DSP_VER_REG (0x0020)
/* DSP Version Register */
24
25
/*
26
* DSP Control Register0
27
*/
28
#define BIT_RUN_STALL (0)
29
#define BIT_START_VEC_SEL (1)
30
#define BIT_DSP_CLKEN (2)
31
32
/*
33
* DSP PRID Register
34
*/
35
#define PRID_MASK (0xff << 0)
36
37
/*
38
* DSP STAT Register
39
*/
40
#define BIT_PFAULT_INFO_VALID (0)
41
#define BIT_PFAULT_ERROR (1)
42
#define BIT_DOUBLE_EXCE_ERROR (2)
43
#define BIT_XOCD_MODE (3)
44
#define BIT_DEBUG_MODE (4)
45
#define BIT_PWAIT_MODE (5)
46
#define BIT_IRAM0_LOAD_STORE (6)
47
48
/*
49
* BIST Control Register
50
*/
51
#define BIT_BIST_EN (0)
52
#define BIST_WDATA_PAT_MASK (0x7 << 1)
53
#define BIT_BIST_ADDR_MODE_SEL (4)
54
#define BIST_REG_SEL_MASK (0x7 << 5)
55
#define BIT_BIST_BUSY (8)
56
#define BIT_BIST_STOP (9)
57
#define BIST_ERR_CYC_MASK (0x3 << 10)
58
#define BIST_ERR_PAT_MASK (0x7 << 12)
59
#define BIT_BIST_ERR_STA (15)
60
#define BIST_SELECT_MASK (0xf << 16)
61
62
/*
63
* DSP Version Register
64
*/
65
#define SMALL_VER_MASK (0x1f << 0)
66
#define LARGE_VER_MASK (0x1f << 16)
67
68
/*
69
* DSP SRAM Remap Register
70
*/
71
#define BIT_SRAM_REMAP_ENABLE (0)
72
#define SRAMC_SRAM_REMAP_REG (0x8)
73
74
/*
75
* RISC-V CFG Register
76
*/
77
#define RISCV_CFG_BASE (0x06010000)
// Base address for RISC-V configuration
78
79
/*
80
* RISC-V start address
81
*/
82
#define RISCV_STA_ADD_REG (RISCV_CFG_BASE + 0x0204)
83
#define RISCV_STA_ADD_L_REG (RISCV_CFG_BASE + 0x0004)
84
#define RISCV_STA_ADD_H_REG (RISCV_CFG_BASE + 0x0008)
85
86
#endif
// __REG_RPROC_H__
Generated by
1.9.8