Macros
#define	DSP0_CFG_BASE (0x01700000)

#define	DSP_DEFAULT_RST_VEC (0x100000)

#define	DSP_ALT_RESET_VEC_REG (0x0000) /* DSP Reset Control Register */

#define	DSP_CTRL_REG0 (0x0004) /* DSP Control Register0 */

#define	DSP_PRID_REG (0x000c) /* DSP PRID Register */

#define	DSP_STAT_REG (0x0010) /* DSP STAT Register */

#define	DSP_BIST_CTRL_REG (0x0014) /* DSP BIST CTRL Register */

#define	DSP_JTRST_REG (0x001c) /* DSP JTAG CONFIG RESET Register */

#define	DSP_VER_REG (0x0020) /* DSP Version Register */

#define	BIT_RUN_STALL (0)

#define	BIT_START_VEC_SEL (1)

#define	BIT_DSP_CLKEN (2)

#define	PRID_MASK (0xff << 0)

#define	BIT_PFAULT_INFO_VALID (0)

#define	BIT_PFAULT_ERROR (1)

#define	BIT_DOUBLE_EXCE_ERROR (2)

#define	BIT_XOCD_MODE (3)

#define	BIT_DEBUG_MODE (4)

#define	BIT_PWAIT_MODE (5)

#define	BIT_IRAM0_LOAD_STORE (6)

#define	BIT_BIST_EN (0)

#define	BIST_WDATA_PAT_MASK (0x7 << 1)

#define	BIT_BIST_ADDR_MODE_SEL (4)

#define	BIST_REG_SEL_MASK (0x7 << 5)

#define	BIT_BIST_BUSY (8)

#define	BIT_BIST_STOP (9)

#define	BIST_ERR_CYC_MASK (0x3 << 10)

#define	BIST_ERR_PAT_MASK (0x7 << 12)

#define	BIT_BIST_ERR_STA (15)

#define	BIST_SELECT_MASK (0xf << 16)

#define	SMALL_VER_MASK (0x1f << 0)

#define	LARGE_VER_MASK (0x1f << 16)

#define	BIT_SRAM_REMAP_ENABLE (0)

#define	SRAMC_SRAM_REMAP_REG (0x8)

#define	RISCV_CFG_BASE (0x06010000)

#define	RISCV_STA_ADD_REG (RISCV_CFG_BASE + 0x0204)

#define	RISCV_STA_ADD_L_REG (RISCV_CFG_BASE + 0x0004)

#define	RISCV_STA_ADD_H_REG (RISCV_CFG_BASE + 0x0008)

Macro Definition Documentation

◆ BIST_ERR_CYC_MASK

#define BIST_ERR_CYC_MASK (0x3 << 10)

◆ BIST_ERR_PAT_MASK

#define BIST_ERR_PAT_MASK (0x7 << 12)

◆ BIST_REG_SEL_MASK

#define BIST_REG_SEL_MASK (0x7 << 5)

◆ BIST_SELECT_MASK

#define BIST_SELECT_MASK (0xf << 16)

◆ BIST_WDATA_PAT_MASK

#define BIST_WDATA_PAT_MASK (0x7 << 1)

◆ BIT_BIST_ADDR_MODE_SEL

#define BIT_BIST_ADDR_MODE_SEL (4)

◆ BIT_BIST_BUSY

#define BIT_BIST_BUSY (8)

◆ BIT_BIST_EN

#define BIT_BIST_EN (0)

◆ BIT_BIST_ERR_STA

#define BIT_BIST_ERR_STA (15)

◆ BIT_BIST_STOP

#define BIT_BIST_STOP (9)

◆ BIT_DEBUG_MODE

#define BIT_DEBUG_MODE (4)

◆ BIT_DOUBLE_EXCE_ERROR

#define BIT_DOUBLE_EXCE_ERROR (2)

◆ BIT_DSP_CLKEN

#define BIT_DSP_CLKEN (2)

◆ BIT_IRAM0_LOAD_STORE

#define BIT_IRAM0_LOAD_STORE (6)

◆ BIT_PFAULT_ERROR

#define BIT_PFAULT_ERROR (1)

◆ BIT_PFAULT_INFO_VALID

#define BIT_PFAULT_INFO_VALID (0)

◆ BIT_PWAIT_MODE

#define BIT_PWAIT_MODE (5)

◆ BIT_RUN_STALL

#define BIT_RUN_STALL (0)

◆ BIT_SRAM_REMAP_ENABLE

#define BIT_SRAM_REMAP_ENABLE (0)

◆ BIT_START_VEC_SEL

#define BIT_START_VEC_SEL (1)

◆ BIT_XOCD_MODE

#define BIT_XOCD_MODE (3)

◆ DSP0_CFG_BASE

#define DSP0_CFG_BASE (0x01700000)

◆ DSP_ALT_RESET_VEC_REG

#define DSP_ALT_RESET_VEC_REG (0x0000) /* DSP Reset Control Register */

◆ DSP_BIST_CTRL_REG

#define DSP_BIST_CTRL_REG (0x0014) /* DSP BIST CTRL Register */

◆ DSP_CTRL_REG0

#define DSP_CTRL_REG0 (0x0004) /* DSP Control Register0 */

◆ DSP_DEFAULT_RST_VEC

#define DSP_DEFAULT_RST_VEC (0x100000)

◆ DSP_JTRST_REG

#define DSP_JTRST_REG (0x001c) /* DSP JTAG CONFIG RESET Register */

◆ DSP_PRID_REG

#define DSP_PRID_REG (0x000c) /* DSP PRID Register */

◆ DSP_STAT_REG

#define DSP_STAT_REG (0x0010) /* DSP STAT Register */

◆ DSP_VER_REG

#define DSP_VER_REG (0x0020) /* DSP Version Register */

◆ LARGE_VER_MASK

#define LARGE_VER_MASK (0x1f << 16)

◆ PRID_MASK

#define PRID_MASK (0xff << 0)

◆ RISCV_CFG_BASE

#define RISCV_CFG_BASE (0x06010000)

◆ RISCV_STA_ADD_H_REG

#define RISCV_STA_ADD_H_REG (RISCV_CFG_BASE + 0x0008)

◆ RISCV_STA_ADD_L_REG

#define RISCV_STA_ADD_L_REG (RISCV_CFG_BASE + 0x0004)

◆ RISCV_STA_ADD_REG

#define RISCV_STA_ADD_REG (RISCV_CFG_BASE + 0x0204)

◆ SMALL_VER_MASK

#define SMALL_VER_MASK (0x1f << 0)

◆ SRAMC_SRAM_REMAP_REG

#define SRAMC_SRAM_REMAP_REG (0x8)

Macros