12#define PLAT_SYSMAP_BASE_ADDR (SUNXI_PLAT_TCIP_BASE_ADDR + 0xFFFF000)
14#define SYSMAP_REGION_NUM 8
16#define SYSMAP_MEM_ATTR_SO 0x10
17#define SYSMAP_MEM_ATTR_CACHEABLE 0x8
18#define SYSMAP_MEM_ATTR_BUFFERABLE 0x4
20#define SYSMAP_MEM_ATTR_MASK (SYSMAP_MEM_ATTR_SO | SYSMAP_MEM_ATTR_CACHEABLE | SYSMAP_MEM_ATTR_BUFFERABLE)
22#define SYSMAP_MEM_ATTR_SO_NC_NB (SYSMAP_MEM_ATTR_SO)
23#define SYSMAP_MEM_ATTR_SO_NC_B (SYSMAP_MEM_ATTR_SO | SYSMAP_MEM_ATTR_BUFFERABLE)
25#define SYSMAP_MEM_ATTR_WO_NC_NB (0)
26#define SYSMAP_MEM_ATTR_WO_NC_B (SYSMAP_MEM_ATTR_BUFFERABLE)
27#define SYSMAP_MEM_ATTR_WO_C_NB (SYSMAP_MEM_ATTR_CACHEABLE)
28#define SYSMAP_MEM_ATTR_WO_C_B (SYSMAP_MEM_ATTR_CACHEABLE | SYSMAP_MEM_ATTR_BUFFERABLE)
30#define SYSMAP_MEM_ATTR_DEVICE (SYSMAP_MEM_ATTR_SO_NC_NB)
31#define SYSMAP_MEM_ATTR_RAM (SYSMAP_MEM_ATTR_WO_C_B)
33#define SYSMAP_ADDR_SHIFT 12
34#define SYSMAP_ADDR_ALIGN_SIZE (1 << SYSMAP_ADDR_SHIFT)
35#define IS_MEM_ADDR_ALIGNED(addr) (!(addr & (SYSMAP_ADDR_ALIGN_SIZE - 1)))
void sysmap_dump_region_info(void)
Definition cache.c:136