reg-ccu.h

Go to the documentation of this file.

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2013-2025
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * 
 * original from bsp uboot defines
 */
 
#ifndef __SUN65IW1_REG_CCU_H__
#define __SUN65IW1_REG_CCU_H__
 
#include <reg-ncat.h>
 
#define PLL_PERI0_CTRL_REG 0x000000a0//PLL_PERI0 Control Register
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8//PLL_PERI0 Pattern0 Control Register
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac//PLL_PERI0 Pattern1 Control Register
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI0_BIAS_REG 0x000000b0//PLL_PERI0 Bias Register
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_PERI1_CTRL_REG 0x000000c0//PLL_PERI1 Control Register
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8//PLL_PERI1 Pattern0 Control Register
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc//PLL_PERI1 Pattern1 Control Register
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI1_BIAS_REG 0x000000d0//PLL_PERI1 Bias Register
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_GPU_CTRL_REG 0x000000e0//PLL_GPU Control Register
#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_GPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_GPU_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_GPU_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_GPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_GPU_PAT0_CTRL_REG 0x000000e8//PLL_GPU Pattern0 Control Register
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_GPU_PAT1_CTRL_REG 0x000000ec//PLL_GPU Pattern1 Control Register
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_GPU_BIAS_REG 0x000000f0//PLL_GPU Bias Register
#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VIDEO0_CTRL_REG 0x00000120//PLL_VIDEO0 Control Register
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128//PLL_VIDEO0 Pattern0 Control Register
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c//PLL_VIDEO0 Pattern1 Control Register
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO0_BIAS_REG 0x00000130//PLL_VIDEO0 Bias Register
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VIDEO1_CTRL_REG 0x00000140//PLL_VIDEO1 Control Register
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148//PLL_VIDEO1 Pattern0 Control Register
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c//PLL_VIDEO1 Pattern1 Control Register
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO1_BIAS_REG 0x00000150//PLL_VIDEO1 Bias Register
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VIDEO2_CTRL_REG 0x00000160//PLL_VIDEO2 Control Register
#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO2_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO2_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VIDEO2_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO2_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO2_PAT0_CTRL_REG 0x00000168//PLL_VIDEO2 Pattern0 Control Register
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO2_PAT1_CTRL_REG 0x0000016c//PLL_VIDEO2 Pattern1 Control Register
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO2_BIAS_REG 0x00000170//PLL_VIDEO2 Bias Register
#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VE_CTRL_REG 0x00000220//PLL_VE Control Register
#define PLL_VE_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VE_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VE_CTRL_REG_LOCK_OFFSET 28
#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VE_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VE_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_VE_PAT0_CTRL_REG 0x00000228//PLL_VE Pattern0 Control Register
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VE_PAT1_CTRL_REG 0x0000022c//PLL_VE Pattern1 Control Register
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VE_BIAS_REG 0x00000230//PLL_VE Bias Register
#define PLL_VE_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_AUDIO0_CTRL_REG 0x00000260//PLL_AUDIO0 Control Register
#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET 16
#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000
#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268//PLL_AUDIO0 Pattern0 Control Register
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c//PLL_AUDIO0 Pattern1 Control Register
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO0_BIAS_REG 0x00000270//PLL_AUDIO0 Bias Register
#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_AUDIO1_CTRL_REG 0x00000280//PLL_AUDIO1 Control Register
#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_AUDIO1_PAT0_CTRL_REG 0x00000288//PLL_AUDIO1 Pattern0 Control Register
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO1_PAT1_CTRL_REG 0x0000028c//PLL_AUDIO1 Pattern1 Control Register
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO1_BIAS_REG 0x00000290//PLL_AUDIO1 Bias Register
#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define AHB_CLK_REG 0x00000500//AHB Clock Register
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define AHB_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define AHB_CLK_REG_FACTOR_M_OFFSET 0
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB0_CLK_REG 0x00000510//APB0 Clock Register
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define APB0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB0_CLK_REG_FACTOR_M_OFFSET 0
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB1_CLK_REG 0x00000518//APB1 Clock Register
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b01
#define APB1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b10
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB1_CLK_REG_FACTOR_M_OFFSET 0
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB_UART_CLK_REG 0x00000538//APB_UART Clock Register
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b001
#define APB_UART_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b010
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100
#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CPU_SYS_DP_CLK_REG 0x00000548//CPU_SYS_DP Clock Register
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_OFFSET 31
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLEAR_MASK 0x80000000
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_OFF 0b0
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_ON 0b1
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_OFFSET 27
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_CLEAR_MASK 0x08000000
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_INVALID 0b0
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_VALID 0b1
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_OFFSET 24
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_CLEAR_MASK 0x07000000
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_SYS_24M_CLK 0b000
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0PLL2X 0b001
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL4X 0b010
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0_800M 0b011
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL3X 0b100
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_HDR_CLK 0b101
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_OFFSET 0
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_CLEAR_MASK 0x0000001f
 
#define CPUX_GIC_CLK_REG 0x00000560//CPUX_GIC Clock Register
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_OFFSET 31
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLEAR_MASK 0x80000000
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_OFF 0b0
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_ON 0b1
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b001
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100
#define CPUX_GIC_CLK_REG_FACTOR_M_OFFSET 0
#define CPUX_GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define NSI_CLK_REG 0x00000580//NSI Clock Register
#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31
#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK 0x80000000
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1
#define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28
#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK 0x10000000
#define NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0
#define NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1
#define NSI_CLK_REG_NSI_UPD_OFFSET 27
#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK 0x08000000
#define NSI_CLK_REG_NSI_UPD_INVALID 0b0
#define NSI_CLK_REG_NSI_UPD_VALID 0b1
#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24
#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK 0x07000000
#define NSI_CLK_REG_NSI_CLK_SEL_SYS_24M_CLK 0b000
#define NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL3X 0b001
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS 0b010
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b011
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M 0b100
#define NSI_CLK_REG_NSI_CLK_SEL_HDR_CLK 0b101
#define NSI_CLK_REG_NSI_DIV1_OFFSET 0
#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK 0x0000001f
 
#define NSI_GAR_REG 0x00000584//NSI Gating And Reset Register
#define NSI_GAR_REG_NSI_CFG_RST_N_OFFSET 17
#define NSI_GAR_REG_NSI_CFG_RST_N_CLEAR_MASK 0x00020000
#define NSI_GAR_REG_NSI_CFG_RST_N_ASSERT 0b0
#define NSI_GAR_REG_NSI_CFG_RST_N_DE_ASSERT 0b1
#define NSI_GAR_REG_NSI_RST_N_OFFSET 16
#define NSI_GAR_REG_NSI_RST_N_CLEAR_MASK 0x00010000
#define NSI_GAR_REG_NSI_RST_N_ASSERT 0b0
#define NSI_GAR_REG_NSI_RST_N_DE_ASSERT 0b1
#define NSI_GAR_REG_NSI_CFG_CLK_EN_OFFSET 0
#define NSI_GAR_REG_NSI_CFG_CLK_EN_CLEAR_MASK 0x00000001
#define NSI_GAR_REG_NSI_CFG_CLK_EN_MASK 0x0
#define NSI_GAR_REG_NSI_CFG_CLK_EN_PASS 0b1
 
#define MBUS_CLK_REG 0x00000588//MBUS Clock Register
#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK 0x80000000
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1
#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28
#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK 0x10000000
#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0
#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1
#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27
#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK 0x08000000
#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0
#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1
#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24
#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK 0x07000000
#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_24M_CLK 0b000
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS 0b001
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b010
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b011
#define MBUS_CLK_REG_MBUS_CLK_SEL_HDR_CLK 0b100
#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0
#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK 0x0000001f
 
#define IOMMU_GAR_REG 0x0000058c//IOMMU Gating And Reset Register
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_OFFSET 0
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_MASK 0x0
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_PASS 0b1
 
#define AHB_MAT_CLK_GATE_EN_REG 0x000005c0//AHB Master Clock Gate Enable Register
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_OFFSET 28
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 15
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00008000
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 14
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00004000
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 13
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00002000
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_OFFSET 11
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000800
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_OFFSET 8
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000100
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_OFFSET 7
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_OFFSET 3
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_OFFSET 2
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_OFFSET 1
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_ENABLE 0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG 0x000005e0//MBUS Master Clock Gate Enable Register
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_OFFSET 28
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET 8
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_CLEAR_MASK 0x00000100
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_OFFSET 7
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_CLEAR_MASK 0x00000080
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_OFFSET 5
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00000020
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_OFFSET 2
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00000004
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_OFFSET 1
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00000002
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_ENABLE 0b1
 
#define MBUS_CLK_GATE_EN_REG 0x000005e4//MBUS Clock Gate Enable Register
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_OFFSET 11
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_CLEAR_MASK 0x00000800
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_OFFSET 9
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_CLEAR_MASK 0x00000200
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_OFFSET 8
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_CLEAR_MASK 0x00000100
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET 2
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_CLEAR_MASK 0x00000004
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_SECURE_DEBUG 0b1
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_OFFSET 1
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_CLEAR_MASK 0x00000002
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_PASS 0b1
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_OFFSET 0
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_CLEAR_MASK 0x00000001
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_MASK 0x0
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_PASS 0b1
 
#define DMA0_GAR_REG 0x00000704//DMA0 Gating And Reset Register
#define DMA0_GAR_REG_DMA0_RST_N_OFFSET 16
#define DMA0_GAR_REG_DMA0_RST_N_CLEAR_MASK 0x00010000
#define DMA0_GAR_REG_DMA0_RST_N_ASSERT 0b0
#define DMA0_GAR_REG_DMA0_RST_N_DE_ASSERT 0b1
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_OFFSET 0
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_MASK 0x0
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_PASS 0b1
 
#define SPINLOCK_GAR_REG 0x00000724//SPINLOCK Gating And Reset Register
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_OFFSET 16
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_CLEAR_MASK 0x00010000
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_ASSERT 0b0
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_DE_ASSERT 0b1
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_OFFSET 0
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_MASK 0x0
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CPUX_GAR_REG 0x00000744//MSGBOX_CPUX Gating And Reset Register
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_OFFSET 16
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_ASSERT 0b0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_DE_ASSERT 0b1
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_PASS 0b1
 
#define MSGBOX_CPUS_GAR_REG 0x0000074c//MSGBOX_CPUS Gating And Reset Register
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_OFFSET 16
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_CLEAR_MASK 0x00010000
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_ASSERT 0b0
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_DE_ASSERT 0b1
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_OFFSET 0
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_MASK 0x0
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_PASS 0b1
 
#define PWM0_GAR_REG 0x00000784//PWM0 Gating And Reset Register
#define PWM0_GAR_REG_PWM0_RST_N_OFFSET 16
#define PWM0_GAR_REG_PWM0_RST_N_CLEAR_MASK 0x00010000
#define PWM0_GAR_REG_PWM0_RST_N_ASSERT 0b0
#define PWM0_GAR_REG_PWM0_RST_N_DE_ASSERT 0b1
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_OFFSET 0
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_MASK 0x0
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_PASS 0b1
 
#define DCU_GAR_REG 0x000007a4//DCU Gating And Reset Register
#define DCU_GAR_REG_DCU_RST_N_OFFSET 16
#define DCU_GAR_REG_DCU_RST_N_CLEAR_MASK 0x00010000
#define DCU_GAR_REG_DCU_RST_N_ASSERT 0b0
#define DCU_GAR_REG_DCU_RST_N_DE_ASSERT 0b1
#define DCU_GAR_REG_DCU_CLK_EN_OFFSET 0
#define DCU_GAR_REG_DCU_CLK_EN_CLEAR_MASK 0x00000001
#define DCU_GAR_REG_DCU_CLK_EN_MASK 0x0
#define DCU_GAR_REG_DCU_CLK_EN_PASS 0b1
 
#define DAP_GAR_REG 0x000007ac//DAP Gating And Reset Register
#define DAP_GAR_REG_DAP_RST_N_OFFSET 16
#define DAP_GAR_REG_DAP_RST_N_CLEAR_MASK 0x00010000
#define DAP_GAR_REG_DAP_RST_N_ASSERT 0b0
#define DAP_GAR_REG_DAP_RST_N_SECURE_DEBUG 0b1
#define DAP_GAR_REG_DAP_AHB_CLK_EN_OFFSET 0
#define DAP_GAR_REG_DAP_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DAP_GAR_REG_DAP_AHB_CLK_EN_MASK 0x0
#define DAP_GAR_REG_DAP_AHB_CLK_EN_SECURE_DEBUG 0b1
 
#define TIMER0_0_CLK_REG 0x00000800//TIMER0_0 Clock Register
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_OFFSET 31
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_DISABLE 0b0
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_ENABLE 0b1
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_0_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_0_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_0_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_0_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_0_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_0_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_0_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_0_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_0_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_1_CLK_REG 0x00000804//TIMER0_1 Clock Register
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_OFFSET 31
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_DISABLE 0b0
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_ENABLE 0b1
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_1_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_1_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_1_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_1_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_1_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_1_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_1_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_1_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_1_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_2_CLK_REG 0x00000808//TIMER0_2 Clock Register
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_OFFSET 31
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_DISABLE 0b0
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_ENABLE 0b1
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_2_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_2_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_2_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_2_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_2_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_2_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_2_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_2_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_2_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_3_CLK_REG 0x0000080c//TIMER0_3 Clock Register
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_OFFSET 31
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_DISABLE 0b0
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_ENABLE 0b1
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_RC_16M_CLK 0b001
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b010
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_3_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_3_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_3_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_3_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_3_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_3_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_3_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_3_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_3_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER0_GAR_REG 0x00000850//TIMER0 Gating And Reset Register
#define TIMER0_GAR_REG_TIMER0_RST_N_OFFSET 16
#define TIMER0_GAR_REG_TIMER0_RST_N_CLEAR_MASK 0x00010000
#define TIMER0_GAR_REG_TIMER0_RST_N_ASSERT 0b0
#define TIMER0_GAR_REG_TIMER0_RST_N_DE_ASSERT 0b1
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_OFFSET 0
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_MASK 0x0
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_PASS 0b1
 
#define DE0_CLK_REG 0x00000a00//DE0 Clock Register
#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31
#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK 0x80000000
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define DE0_CLK_REG_CLK_SRC_SEL_VEPLL 0b011
#define DE0_CLK_REG_FACTOR_M_OFFSET 0
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DE0_GAR_REG 0x00000a04//DE0 Gating And Reset Register
#define DE0_GAR_REG_DE0_RST_N_OFFSET 16
#define DE0_GAR_REG_DE0_RST_N_CLEAR_MASK 0x00010000
#define DE0_GAR_REG_DE0_RST_N_ASSERT 0b0
#define DE0_GAR_REG_DE0_RST_N_DE_ASSERT 0b1
#define DE0_GAR_REG_DE0_AHB_CLK_EN_OFFSET 0
#define DE0_GAR_REG_DE0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DE0_GAR_REG_DE0_AHB_CLK_EN_MASK 0x0
#define DE0_GAR_REG_DE0_AHB_CLK_EN_PASS 0b1
 
#define G2D_CLK_REG 0x00000a40//G2D Clock Register
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b00
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b01
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b10
#define G2D_CLK_REG_FACTOR_M_OFFSET 0
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define G2D_GAR_REG 0x00000a44//G2D Gating And Reset Register
#define G2D_GAR_REG_G2D_RST_N_OFFSET 16
#define G2D_GAR_REG_G2D_RST_N_CLEAR_MASK 0x00010000
#define G2D_GAR_REG_G2D_RST_N_ASSERT 0b0
#define G2D_GAR_REG_G2D_RST_N_DE_ASSERT 0b1
#define G2D_GAR_REG_G2D_AHB_CLK_EN_OFFSET 0
#define G2D_GAR_REG_G2D_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define G2D_GAR_REG_G2D_AHB_CLK_EN_MASK 0x0
#define G2D_GAR_REG_G2D_AHB_CLK_EN_PASS 0b1
 
#define EINK_PANEL_CLK_REG 0x00000a64//EINK PANEL Clock Register
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET 31
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK 0x80000000
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF 0b0
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON 0b1
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100
#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET 0
#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define EINK_GAR_REG 0x00000a6c//EINK Gating And Reset Register
#define EINK_GAR_REG_EINK_RST_N_OFFSET 16
#define EINK_GAR_REG_EINK_RST_N_CLEAR_MASK 0x00010000
#define EINK_GAR_REG_EINK_RST_N_ASSERT 0b0
#define EINK_GAR_REG_EINK_RST_N_DE_ASSERT 0b1
#define EINK_GAR_REG_EINK_AHB_CLK_EN_OFFSET 0
#define EINK_GAR_REG_EINK_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define EINK_GAR_REG_EINK_AHB_CLK_EN_MASK 0x0
#define EINK_GAR_REG_EINK_AHB_CLK_EN_PASS 0b1
 
#define VE0_CLK_REG 0x00000a80//VE0 Clock Register
#define VE0_CLK_REG_VE0_CLK_GATING_OFFSET 31
#define VE0_CLK_REG_VE0_CLK_GATING_CLEAR_MASK 0x80000000
#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_OFF 0b0
#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_ON 0b1
#define VE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VE0_CLK_REG_CLK_SRC_SEL_VEPLL 0b000
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011
#define VE0_CLK_REG_FACTOR_M_OFFSET 0
#define VE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define VE0_GAR_REG 0x00000a8c//VE0 Gating And Reset Register
#define VE0_GAR_REG_VE0_RST_N_OFFSET 16
#define VE0_GAR_REG_VE0_RST_N_CLEAR_MASK 0x00010000
#define VE0_GAR_REG_VE0_RST_N_ASSERT 0b0
#define VE0_GAR_REG_VE0_RST_N_DE_ASSERT 0b1
#define VE0_GAR_REG_VE0_AHB_CLK_EN_OFFSET 0
#define VE0_GAR_REG_VE0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VE0_GAR_REG_VE0_AHB_CLK_EN_MASK 0x0
#define VE0_GAR_REG_VE0_AHB_CLK_EN_PASS 0b1
 
#define CE_SYS_CLK_REG 0x00000ac0//CE_SYS Clock Register
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET 31
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLEAR_MASK 0x80000000
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLOCK_IS_OFF 0b0
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_SECURE_DEBUG 0b1
#define CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CE_SYS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CE_SYS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011
#define CE_SYS_CLK_REG_FACTOR_M_OFFSET 0
#define CE_SYS_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CE_SYS_GAR_REG 0x00000ac4//CE_SYS Gating And Reset Register
#define CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET 16
#define CE_SYS_GAR_REG_CE_SYS_RST_N_CLEAR_MASK 0x00010000
#define CE_SYS_GAR_REG_CE_SYS_RST_N_ASSERT 0b0
#define CE_SYS_GAR_REG_CE_SYS_RST_N_SECURE_DEBUG 0b1
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET 0
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK 0x0
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_SECURE_DEBUG 0b1
 
#define GPU_CLK_REG 0x00000b20//GPU Clock Register
#define GPU_CLK_REG_GPU_CLK_GATING_OFFSET 31
#define GPU_CLK_REG_GPU_CLK_GATING_CLEAR_MASK 0x80000000
#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_ON 0b1
#define GPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPU_CLK_REG_CLK_SRC_SEL_GPUPLL 0b000
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b100
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b101
#define GPU_CLK_REG_FACTOR_M_OFFSET 0
#define GPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000000f
#define GPU_CLK_REG_FACTOR_M_NOT_MASK 0x0000
#define GPU_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES 0b0001
#define GPU_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES 0b0010
#define GPU_CLK_REG_FACTOR_M_MASK_3_CYCLES_AT_16_CYCLES 0b0011
#define GPU_CLK_REG_FACTOR_M_MASK_15_CYCLES_AT_16_CYCLES 0b1111
 
#define GPU_GAR_REG 0x00000b24//GPU Gating And Reset Register
#define GPU_GAR_REG_GPU_RST_N_OFFSET 16
#define GPU_GAR_REG_GPU_RST_N_CLEAR_MASK 0x00010000
#define GPU_GAR_REG_GPU_RST_N_ASSERT 0b0
#define GPU_GAR_REG_GPU_RST_N_DE_ASSERT 0b1
#define GPU_GAR_REG_GPU_AHB_CLK_EN_OFFSET 0
#define GPU_GAR_REG_GPU_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define GPU_GAR_REG_GPU_AHB_CLK_EN_MASK 0x0
#define GPU_GAR_REG_GPU_AHB_CLK_EN_PASS 0b1
 
#define DRAMC_GAR_REG 0x00000c0c//DRAMC Gating And Reset Register
#define DRAMC_GAR_REG_DRAMC_RST_N_OFFSET 16
#define DRAMC_GAR_REG_DRAMC_RST_N_CLEAR_MASK 0x00010000
#define DRAMC_GAR_REG_DRAMC_RST_N_ASSERT 0b0
#define DRAMC_GAR_REG_DRAMC_RST_N_DE_ASSERT 0b1
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_OFFSET 0
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_MASK 0x0
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_PASS 0b1
 
#define SMHC0_CLK_REG 0x00000d00//SMHC0 Clock Register
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC0_GAR_REG 0x00000d0c//SMHC0 Gating And Reset Register
#define SMHC0_GAR_REG_SMHC0_RST_N_OFFSET 16
#define SMHC0_GAR_REG_SMHC0_RST_N_CLEAR_MASK 0x00010000
#define SMHC0_GAR_REG_SMHC0_RST_N_ASSERT 0b0
#define SMHC0_GAR_REG_SMHC0_RST_N_DE_ASSERT 0b1
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET 0
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_MASK 0x0
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_PASS 0b1
 
#define SMHC1_CLK_REG 0x00000d10//SMHC1 Clock Register
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC1_GAR_REG 0x00000d1c//SMHC1 Gating And Reset Register
#define SMHC1_GAR_REG_SMHC1_RST_N_OFFSET 16
#define SMHC1_GAR_REG_SMHC1_RST_N_CLEAR_MASK 0x00010000
#define SMHC1_GAR_REG_SMHC1_RST_N_ASSERT 0b0
#define SMHC1_GAR_REG_SMHC1_RST_N_DE_ASSERT 0b1
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_OFFSET 0
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_MASK 0x0
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_PASS 0b1
 
#define SMHC2_CLK_REG 0x00000d20//SMHC2 Clock Register
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100
#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC2_GAR_REG 0x00000d2c//SMHC2 Gating And Reset Register
#define SMHC2_GAR_REG_SMHC2_RST_N_OFFSET 16
#define SMHC2_GAR_REG_SMHC2_RST_N_CLEAR_MASK 0x00010000
#define SMHC2_GAR_REG_SMHC2_RST_N_ASSERT 0b0
#define SMHC2_GAR_REG_SMHC2_RST_N_DE_ASSERT 0b1
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_OFFSET 0
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_MASK 0x0
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_PASS 0b1
 
#define UART0_GAR_REG 0x00000e00//UART0 Gating And Reset Register
#define UART0_GAR_REG_UART0_RST_N_OFFSET 16
#define UART0_GAR_REG_UART0_RST_N_CLEAR_MASK 0x00010000
#define UART0_GAR_REG_UART0_RST_N_ASSERT 0b0
#define UART0_GAR_REG_UART0_RST_N_DE_ASSERT 0b1
#define UART0_GAR_REG_UART0_APB_CLK_EN_OFFSET 0
#define UART0_GAR_REG_UART0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART0_GAR_REG_UART0_APB_CLK_EN_MASK 0x0
#define UART0_GAR_REG_UART0_APB_CLK_EN_PASS 0b1
 
#define UART1_GAR_REG 0x00000e04//UART1 Gating And Reset Register
#define UART1_GAR_REG_UART1_RST_N_OFFSET 16
#define UART1_GAR_REG_UART1_RST_N_CLEAR_MASK 0x00010000
#define UART1_GAR_REG_UART1_RST_N_ASSERT 0b0
#define UART1_GAR_REG_UART1_RST_N_DE_ASSERT 0b1
#define UART1_GAR_REG_UART1_APB_CLK_EN_OFFSET 0
#define UART1_GAR_REG_UART1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART1_GAR_REG_UART1_APB_CLK_EN_MASK 0x0
#define UART1_GAR_REG_UART1_APB_CLK_EN_PASS 0b1
 
#define UART2_GAR_REG 0x00000e08//UART2 Gating And Reset Register
#define UART2_GAR_REG_UART2_RST_N_OFFSET 16
#define UART2_GAR_REG_UART2_RST_N_CLEAR_MASK 0x00010000
#define UART2_GAR_REG_UART2_RST_N_ASSERT 0b0
#define UART2_GAR_REG_UART2_RST_N_DE_ASSERT 0b1
#define UART2_GAR_REG_UART2_APB_CLK_EN_OFFSET 0
#define UART2_GAR_REG_UART2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART2_GAR_REG_UART2_APB_CLK_EN_MASK 0x0
#define UART2_GAR_REG_UART2_APB_CLK_EN_PASS 0b1
 
#define UART3_GAR_REG 0x00000e0c//UART3 Gating And Reset Register
#define UART3_GAR_REG_UART3_RST_N_OFFSET 16
#define UART3_GAR_REG_UART3_RST_N_CLEAR_MASK 0x00010000
#define UART3_GAR_REG_UART3_RST_N_ASSERT 0b0
#define UART3_GAR_REG_UART3_RST_N_DE_ASSERT 0b1
#define UART3_GAR_REG_UART3_APB_CLK_EN_OFFSET 0
#define UART3_GAR_REG_UART3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART3_GAR_REG_UART3_APB_CLK_EN_MASK 0x0
#define UART3_GAR_REG_UART3_APB_CLK_EN_PASS 0b1
 
#define UART4_GAR_REG 0x00000e10//UART4 Gating And Reset Register
#define UART4_GAR_REG_UART4_RST_N_OFFSET 16
#define UART4_GAR_REG_UART4_RST_N_CLEAR_MASK 0x00010000
#define UART4_GAR_REG_UART4_RST_N_ASSERT 0b0
#define UART4_GAR_REG_UART4_RST_N_DE_ASSERT 0b1
#define UART4_GAR_REG_UART4_APB_CLK_EN_OFFSET 0
#define UART4_GAR_REG_UART4_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART4_GAR_REG_UART4_APB_CLK_EN_MASK 0x0
#define UART4_GAR_REG_UART4_APB_CLK_EN_PASS 0b1
 
#define UART5_GAR_REG 0x00000e14//UART5 Gating And Reset Register
#define UART5_GAR_REG_UART5_RST_N_OFFSET 16
#define UART5_GAR_REG_UART5_RST_N_CLEAR_MASK 0x00010000
#define UART5_GAR_REG_UART5_RST_N_ASSERT 0b0
#define UART5_GAR_REG_UART5_RST_N_DE_ASSERT 0b1
#define UART5_GAR_REG_UART5_APB_CLK_EN_OFFSET 0
#define UART5_GAR_REG_UART5_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART5_GAR_REG_UART5_APB_CLK_EN_MASK 0x0
#define UART5_GAR_REG_UART5_APB_CLK_EN_PASS 0b1
 
#define UART6_GAR_REG 0x00000e18//UART6 Gating And Reset Register
#define UART6_GAR_REG_UART6_RST_N_OFFSET 16
#define UART6_GAR_REG_UART6_RST_N_CLEAR_MASK 0x00010000
#define UART6_GAR_REG_UART6_RST_N_ASSERT 0b0
#define UART6_GAR_REG_UART6_RST_N_DE_ASSERT 0b1
#define UART6_GAR_REG_UART6_APB_CLK_EN_OFFSET 0
#define UART6_GAR_REG_UART6_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART6_GAR_REG_UART6_APB_CLK_EN_MASK 0x0
#define UART6_GAR_REG_UART6_APB_CLK_EN_PASS 0b1
 
#define UART7_GAR_REG 0x00000e1c//UART7 Gating And Reset Register
#define UART7_GAR_REG_UART7_RST_N_OFFSET 16
#define UART7_GAR_REG_UART7_RST_N_CLEAR_MASK 0x00010000
#define UART7_GAR_REG_UART7_RST_N_ASSERT 0b0
#define UART7_GAR_REG_UART7_RST_N_DE_ASSERT 0b1
#define UART7_GAR_REG_UART7_APB_CLK_EN_OFFSET 0
#define UART7_GAR_REG_UART7_APB_CLK_EN_CLEAR_MASK 0x00000001
#define UART7_GAR_REG_UART7_APB_CLK_EN_MASK 0x0
#define UART7_GAR_REG_UART7_APB_CLK_EN_PASS 0b1
 
#define TWI0_GAR_REG 0x00000e80//TWI0 Gating And Reset Register
#define TWI0_GAR_REG_TWI0_RST_N_OFFSET 16
#define TWI0_GAR_REG_TWI0_RST_N_CLEAR_MASK 0x00010000
#define TWI0_GAR_REG_TWI0_RST_N_ASSERT 0b0
#define TWI0_GAR_REG_TWI0_RST_N_DE_ASSERT 0b1
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_OFFSET 0
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_MASK 0x0
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_PASS 0b1
 
#define TWI1_GAR_REG 0x00000e84//TWI1 Gating And Reset Register
#define TWI1_GAR_REG_TWI1_RST_N_OFFSET 16
#define TWI1_GAR_REG_TWI1_RST_N_CLEAR_MASK 0x00010000
#define TWI1_GAR_REG_TWI1_RST_N_ASSERT 0b0
#define TWI1_GAR_REG_TWI1_RST_N_DE_ASSERT 0b1
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_OFFSET 0
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_MASK 0x0
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_PASS 0b1
 
#define TWI2_GAR_REG 0x00000e88//TWI2 Gating And Reset Register
#define TWI2_GAR_REG_TWI2_RST_N_OFFSET 16
#define TWI2_GAR_REG_TWI2_RST_N_CLEAR_MASK 0x00010000
#define TWI2_GAR_REG_TWI2_RST_N_ASSERT 0b0
#define TWI2_GAR_REG_TWI2_RST_N_DE_ASSERT 0b1
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_OFFSET 0
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_MASK 0x0
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_PASS 0b1
 
#define TWI3_GAR_REG 0x00000e8c//TWI3 Gating And Reset Register
#define TWI3_GAR_REG_TWI3_RST_N_OFFSET 16
#define TWI3_GAR_REG_TWI3_RST_N_CLEAR_MASK 0x00010000
#define TWI3_GAR_REG_TWI3_RST_N_ASSERT 0b0
#define TWI3_GAR_REG_TWI3_RST_N_DE_ASSERT 0b1
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_OFFSET 0
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_MASK 0x0
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_PASS 0b1
 
#define TWI4_GAR_REG 0x00000e90//TWI4 Gating And Reset Register
#define TWI4_GAR_REG_TWI4_RST_N_OFFSET 16
#define TWI4_GAR_REG_TWI4_RST_N_CLEAR_MASK 0x00010000
#define TWI4_GAR_REG_TWI4_RST_N_ASSERT 0b0
#define TWI4_GAR_REG_TWI4_RST_N_DE_ASSERT 0b1
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_OFFSET 0
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_MASK 0x0
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_PASS 0b1
 
#define TWI5_GAR_REG 0x00000e94//TWI5 Gating And Reset Register
#define TWI5_GAR_REG_TWI5_RST_N_OFFSET 16
#define TWI5_GAR_REG_TWI5_RST_N_CLEAR_MASK 0x00010000
#define TWI5_GAR_REG_TWI5_RST_N_ASSERT 0b0
#define TWI5_GAR_REG_TWI5_RST_N_DE_ASSERT 0b1
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_OFFSET 0
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_MASK 0x0
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_PASS 0b1
 
#define SPI0_CLK_REG 0x00000f00//SPI0 Clock Register
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI0_CLK_REG_FACTOR_N_OFFSET 8
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI0_CLK_REG_FACTOR_M_OFFSET 0
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI0_GAR_REG 0x00000f04//SPI0 Gating And Reset Register
#define SPI0_GAR_REG_SPI0_RST_N_OFFSET 16
#define SPI0_GAR_REG_SPI0_RST_N_CLEAR_MASK 0x00010000
#define SPI0_GAR_REG_SPI0_RST_N_ASSERT 0b0
#define SPI0_GAR_REG_SPI0_RST_N_DE_ASSERT 0b1
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_OFFSET 0
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_MASK 0x0
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_PASS 0b1
 
#define SPI1_CLK_REG 0x00000f08//SPI1 Clock Register
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI1_CLK_REG_FACTOR_N_OFFSET 8
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI1_CLK_REG_FACTOR_M_OFFSET 0
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI1_GAR_REG 0x00000f0c//SPI1 Gating And Reset Register
#define SPI1_GAR_REG_SPI1_RST_N_OFFSET 16
#define SPI1_GAR_REG_SPI1_RST_N_CLEAR_MASK 0x00010000
#define SPI1_GAR_REG_SPI1_RST_N_ASSERT 0b0
#define SPI1_GAR_REG_SPI1_RST_N_DE_ASSERT 0b1
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_OFFSET 0
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_MASK 0x0
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_PASS 0b1
 
#define SPI2_CLK_REG 0x00000f10//SPI2 Clock Register
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI2_CLK_REG_FACTOR_N_OFFSET 8
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI2_CLK_REG_FACTOR_M_OFFSET 0
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI2_GAR_REG 0x00000f14//SPI2 Gating And Reset Register
#define SPI2_GAR_REG_SPI2_RST_N_OFFSET 16
#define SPI2_GAR_REG_SPI2_RST_N_CLEAR_MASK 0x00010000
#define SPI2_GAR_REG_SPI2_RST_N_ASSERT 0b0
#define SPI2_GAR_REG_SPI2_RST_N_DE_ASSERT 0b1
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_OFFSET 0
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_MASK 0x0
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_PASS 0b1
 
#define GPADC0_CLK_REG 0x00000fc0//GPADC0 Clock Register
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET 31
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPADC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC0_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GPADC0_GAR_REG 0x00000fc4//GPADC0 Gating And Reset Register
#define GPADC0_GAR_REG_GPADC0_RST_N_OFFSET 16
#define GPADC0_GAR_REG_GPADC0_RST_N_CLEAR_MASK 0x00010000
#define GPADC0_GAR_REG_GPADC0_RST_N_ASSERT 0b0
#define GPADC0_GAR_REG_GPADC0_RST_N_DE_ASSERT 0b1
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_OFFSET 0
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_MASK 0x0
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_PASS 0b1
 
#define TSENSOR_GAR_REG 0x00000fe4//TSENSOR Gating And Reset Register
#define TSENSOR_GAR_REG_TSENSOR_RST_N_OFFSET 16
#define TSENSOR_GAR_REG_TSENSOR_RST_N_CLEAR_MASK 0x00010000
#define TSENSOR_GAR_REG_TSENSOR_RST_N_ASSERT 0b0
#define TSENSOR_GAR_REG_TSENSOR_RST_N_DE_ASSERT 0b1
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_OFFSET 0
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_CLEAR_MASK 0x00000001
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_MASK 0x0
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_PASS 0b1
 
#define IR_RX0_CLK_REG 0x00001000//IR_RX0 Clock Register
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_OFFSET 31
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLEAR_MASK 0x80000000
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_RX0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_RX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b000
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b001
#define IR_RX0_CLK_REG_FACTOR_M_OFFSET 0
#define IR_RX0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IR_RX0_GAR_REG 0x00001004//IR_RX0 Gating And Reset Register
#define IR_RX0_GAR_REG_IR_RX0_RST_N_OFFSET 16
#define IR_RX0_GAR_REG_IR_RX0_RST_N_CLEAR_MASK 0x00010000
#define IR_RX0_GAR_REG_IR_RX0_RST_N_ASSERT 0b0
#define IR_RX0_GAR_REG_IR_RX0_RST_N_DE_ASSERT 0b1
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_OFFSET 0
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_MASK 0x0
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_PASS 0b1
 
#define IR_TX_CLK_REG 0x00001008//IR_TX Clock Register
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_OFFSET 31
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLEAR_MASK 0x80000000
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_OFF 0b0
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_ON 0b1
#define IR_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IR_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define IR_TX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b0
#define IR_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b1
#define IR_TX_CLK_REG_FACTOR_M_OFFSET 0
#define IR_TX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IR_TX_GAR_REG 0x0000100c//IR_TX Gating And Reset Register
#define IR_TX_GAR_REG_IR_TX_RST_N_OFFSET 16
#define IR_TX_GAR_REG_IR_TX_RST_N_CLEAR_MASK 0x00010000
#define IR_TX_GAR_REG_IR_TX_RST_N_ASSERT 0b0
#define IR_TX_GAR_REG_IR_TX_RST_N_DE_ASSERT 0b1
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_OFFSET 0
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_CLEAR_MASK 0x00000001
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_MASK 0x0
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_PASS 0b1
 
#define I2S0_CLK_REG 0x00001200//I2S0 Clock Register
#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET 31
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK 0x80000000
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define I2S0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define I2S0_CLK_REG_FACTOR_M_OFFSET 0
#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2S0_GAR_REG 0x0000120c//I2S0 Gating And Reset Register
#define I2S0_GAR_REG_I2S0_RST_N_OFFSET 16
#define I2S0_GAR_REG_I2S0_RST_N_CLEAR_MASK 0x00010000
#define I2S0_GAR_REG_I2S0_RST_N_ASSERT 0b0
#define I2S0_GAR_REG_I2S0_RST_N_DE_ASSERT 0b1
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_OFFSET 0
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_MASK 0x0
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_PASS 0b1
 
#define I2S1_CLK_REG 0x00001210//I2S1 Clock Register
#define I2S1_CLK_REG_I2S1_CLK_GATING_OFFSET 31
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLEAR_MASK 0x80000000
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define I2S1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define I2S1_CLK_REG_FACTOR_M_OFFSET 0
#define I2S1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2S1_GAR_REG 0x0000121c//I2S1 Gating And Reset Register
#define I2S1_GAR_REG_I2S1_RST_N_OFFSET 16
#define I2S1_GAR_REG_I2S1_RST_N_CLEAR_MASK 0x00010000
#define I2S1_GAR_REG_I2S1_RST_N_ASSERT 0b0
#define I2S1_GAR_REG_I2S1_RST_N_DE_ASSERT 0b1
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_OFFSET 0
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_MASK 0x0
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_PASS 0b1
 
#define I2S2_CLK_REG 0x00001220//I2S2 Clock Register
#define I2S2_CLK_REG_I2S2_CLK_GATING_OFFSET 31
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLEAR_MASK 0x80000000
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define I2S2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define I2S2_CLK_REG_FACTOR_M_OFFSET 0
#define I2S2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2S2_GAR_REG 0x0000122c//I2S2 Gating And Reset Register
#define I2S2_GAR_REG_I2S2_RST_N_OFFSET 16
#define I2S2_GAR_REG_I2S2_RST_N_CLEAR_MASK 0x00010000
#define I2S2_GAR_REG_I2S2_RST_N_ASSERT 0b0
#define I2S2_GAR_REG_I2S2_RST_N_DE_ASSERT 0b1
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_OFFSET 0
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_MASK 0x0
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_PASS 0b1
 
#define I2S3_CLK_REG 0x00001230//I2S3 Clock Register
#define I2S3_CLK_REG_I2S3_CLK_GATING_OFFSET 31
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLEAR_MASK 0x80000000
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_OFF 0b0
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_ON 0b1
#define I2S3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2S3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define I2S3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define I2S3_CLK_REG_FACTOR_M_OFFSET 0
#define I2S3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2S3_GAR_REG 0x0000123c//I2S3 Gating And Reset Register
#define I2S3_GAR_REG_I2S3_RST_N_OFFSET 16
#define I2S3_GAR_REG_I2S3_RST_N_CLEAR_MASK 0x00010000
#define I2S3_GAR_REG_I2S3_RST_N_ASSERT 0b0
#define I2S3_GAR_REG_I2S3_RST_N_DE_ASSERT 0b1
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_OFFSET 0
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_CLEAR_MASK 0x00000001
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_MASK 0x0
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_PASS 0b1
 
#define OWA0_TX_CLK_REG 0x00001280//OWA0 TX Clock Register
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_OFFSET 31
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLEAR_MASK 0x80000000
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define OWA0_TX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA0_TX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define OWA0_RX_CLK_REG 0x00001284//OWA0 RX Clock Register
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_OFFSET 31
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLEAR_MASK 0x80000000
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b000
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b010
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b011
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b100
#define OWA0_RX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA0_RX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define OWA0_GAR_REG 0x0000128c//OWA0 Gating And Reset Register
#define OWA0_GAR_REG_OWA0_RST_N_OFFSET 16
#define OWA0_GAR_REG_OWA0_RST_N_CLEAR_MASK 0x00010000
#define OWA0_GAR_REG_OWA0_RST_N_ASSERT 0b0
#define OWA0_GAR_REG_OWA0_RST_N_DE_ASSERT 0b1
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_OFFSET 0
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_MASK 0b0
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_PASS 0b1
 
#define DMIC_CLK_REG 0x000012c0//DMIC Clock Register
#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK 0x80000000
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1
#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define DMIC_CLK_REG_FACTOR_M_OFFSET 0
#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DMIC_GAR_REG 0x000012cc//DMIC Gating And Reset Register
#define DMIC_GAR_REG_DMIC_RST_N_OFFSET 16
#define DMIC_GAR_REG_DMIC_RST_N_CLEAR_MASK 0x00010000
#define DMIC_GAR_REG_DMIC_RST_N_ASSERT 0b0
#define DMIC_GAR_REG_DMIC_RST_N_DE_ASSERT 0b1
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_OFFSET 0
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_CLEAR_MASK 0x00000001
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_MASK 0b0
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_PASS 0b1
 
#define AUDIOCODEC0_DAC_CLK_REG 0x000012e0//AUDIOCODEC0 DAC Clock Register
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_OFFSET 31
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLEAR_MASK 0x80000000
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_OFF 0b0
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_ON 0b1
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_OFFSET 0
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define AUDIOCODEC0_ADC_CLK_REG 0x000012e8//AUDIOCODEC0 ADC Clock Register
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_OFFSET 31
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLEAR_MASK 0x80000000
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_OFF 0b0
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_ON 0b1
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_OFFSET 0
#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define AUDIOCODEC0_GAR_REG 0x000012ec//AUDIOCODEC0 Gating And Reset Register
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_OFFSET 16
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_CLEAR_MASK 0x00010000
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_ASSERT 0b0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_DE_ASSERT 0b1
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_OFFSET 0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_CLEAR_MASK 0x00000001
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_MASK 0b0
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_PASS 0b1
 
#define AUDIOCODEC1_DAC_CLK_REG 0x000012f0//AUDIOCODEC1 DAC Clock Register
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_OFFSET 31
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLEAR_MASK 0x80000000
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_OFF 0b0
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_ON 0b1
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL 0b000
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X 0b001
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X 0b010
#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_OFFSET 0
#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define AUDIOCODEC1_GAR_REG 0x000012fc//AUDIOCODEC1 Gating And Reset Register
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_OFFSET 16
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_CLEAR_MASK 0x00010000
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_ASSERT 0b0
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_DE_ASSERT 0b1
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_OFFSET 0
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_CLEAR_MASK 0x00000001
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_MASK 0b0
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_PASS 0b1
 
#define USB0_CLK_REG 0x00001300//USB0 Clock Register
#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK 0b01
#define USB0_CLK_REG_USB0_CLK12M_SEL_SYS_32K_CLK 0b10
#define USB0_CLK_REG_USB0_CLK12M_SEL_RC_16M_CLK 0b11
 
#define USB0_GAR_REG 0x00001304//USB0 Gating And Reset Register
#define USB0_GAR_REG_USB0_DEV_RST_N_OFFSET 24
#define USB0_GAR_REG_USB0_DEV_RST_N_CLEAR_MASK 0x01000000
#define USB0_GAR_REG_USB0_DEV_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_DEV_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_EHCI_RST_N_OFFSET 20
#define USB0_GAR_REG_USB0_EHCI_RST_N_CLEAR_MASK 0x00100000
#define USB0_GAR_REG_USB0_EHCI_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_EHCI_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_OHCI_RST_N_OFFSET 16
#define USB0_GAR_REG_USB0_OHCI_RST_N_CLEAR_MASK 0x00010000
#define USB0_GAR_REG_USB0_OHCI_RST_N_ASSERT 0b0
#define USB0_GAR_REG_USB0_OHCI_RST_N_DE_ASSERT 0b1
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_OFFSET 8
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_CLEAR_MASK 0x00000100
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_MASK 0b0
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_PASS 0b1
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_OFFSET 4
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_CLEAR_MASK 0x00000010
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_MASK 0b0
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_PASS 0b1
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_OFFSET 0
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_MASK 0b0
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_PASS 0b1
 
#define USB1_CLK_REG 0x00001308//USB1 Clock Register
#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK 0b01
#define USB1_CLK_REG_USB1_CLK12M_SEL_SYS_32K_CLK 0b10
#define USB1_CLK_REG_USB1_CLK12M_SEL_RC_16M_CLK 0b11
 
#define USB1_GAR_REG 0x0000130c//USB1 Gating And Reset Register
#define USB1_GAR_REG_USB1_EHCI_RST_N_OFFSET 20
#define USB1_GAR_REG_USB1_EHCI_RST_N_CLEAR_MASK 0x00100000
#define USB1_GAR_REG_USB1_EHCI_RST_N_ASSERT 0b0
#define USB1_GAR_REG_USB1_EHCI_RST_N_DE_ASSERT 0b1
#define USB1_GAR_REG_USB1_OHCI_RST_N_OFFSET 16
#define USB1_GAR_REG_USB1_OHCI_RST_N_CLEAR_MASK 0x00010000
#define USB1_GAR_REG_USB1_OHCI_RST_N_ASSERT 0b0
#define USB1_GAR_REG_USB1_OHCI_RST_N_DE_ASSERT 0b1
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_OFFSET 4
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_CLEAR_MASK 0x00000010
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_MASK 0b0
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_PASS 0b1
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_OFFSET 0
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_MASK 0b0
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_PASS 0b1
 
#define USB2P0_SYS_PHY_REF_CLK_REG 0x00001340//USB2P0_SYS PHY Reference Clock Register
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_OFFSET 31
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1
 
#define USB2P0_SYS_GAR_REG 0x00001344//USB2P0_SYS Gating And Reset Register
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_OFFSET 16
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_CLEAR_MASK 0x00010000
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_ASSERT 0b0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_DE_ASSERT 0b1
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_OFFSET 0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_MASK 0b0
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_PASS 0b1
 
#define USB2_U2_PHY_REF_CLK_REG 0x00001348//USB2_U2 PHY Reference Clock Register
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_OFFSET 31
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1
 
#define USB2_SUSPEND_CLK_REG 0x00001350//USB2 SUSPEND Clock Register
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b0
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b1
#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define USB2_MF_CLK_REG 0x00001354//USB2 MF Clock Register
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b01
#define USB2_MF_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define USB2_GAR_REG 0x0000135c//USB2 Gating And Reset Register
#define USB2_GAR_REG_USB2_RST_N_OFFSET 16
#define USB2_GAR_REG_USB2_RST_N_CLEAR_MASK 0x00010000
#define USB2_GAR_REG_USB2_RST_N_ASSERT 0b0
#define USB2_GAR_REG_USB2_RST_N_DE_ASSERT 0b1
 
#define USB2_U3_ONLY_UTMI_CLK_REG 0x00001360//USB2_U3_ONLY_UTMI Clock Register
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_OFFSET 31
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001
#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define USB2_U2_ONLY_PIPE_CLK_REG 0x00001364//USB2_U2_ONLY_PIPE Clock Register
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_OFFSET 31
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define PCIe0_AUX_CLK_REG 0x00001380//PCIe0_AUX Clock Register
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET 31
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF 0b0
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON 0b1
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b0
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK 0b1
#define PCIe0_AUX_CLK_REG_FACTOR_M_OFFSET 0
#define PCIe0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define PCIe0_AXI_S_CLK_REG 0x00001384//PCIe0 AXI Slave Clock Register
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_OFFSET 31
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_OFF 0b0
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_ON 0b1
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b0
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1
#define PCIe0_AXI_S_CLK_REG_FACTOR_M_OFFSET 0
#define PCIe0_AXI_S_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define PCIe0_GAR_REG 0x0000138c//PCIe0 Gating And Reset Register
#define PCIe0_GAR_REG_PCIE0_RST_N_OFFSET 17
#define PCIe0_GAR_REG_PCIE0_RST_N_CLEAR_MASK 0x00020000
#define PCIe0_GAR_REG_PCIE0_RST_N_ASSERT 0b0
#define PCIe0_GAR_REG_PCIE0_RST_N_DE_ASSERT 0b1
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_OFFSET 16
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_CLEAR_MASK 0x00010000
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_ASSERT 0b0
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_DE_ASSERT 0b1
 
#define HSI_COMB0_PHY_CFG_CLK_REG 0x000013c0//HSI COMB0 PHY Configure Clock Register
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_OFFSET 31
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLEAR_MASK 0x80000000
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1
#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0
#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define HSI_COMB0_PHY_REF_CLK_REG 0x000013c4//HSI COMB0 PHY Reference Clock Register
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_OFFSET 31
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_OFFSET 0
#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define HSI_SYS_GAR_REG 0x000013cc//HSI_SYS Gating And Reset Register
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_OFFSET 16
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_CLEAR_MASK 0x00010000
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_ASSERT 0b0
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_DE_ASSERT 0b1
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_OFFSET 1
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_CLEAR_MASK 0x00000002
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_MASK 0b0
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_PASS 0b1
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_OFFSET 0
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_MASK 0b0
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_PASS 0b1
 
#define HSI_AXI_CLK_REG 0x000013e0//HSI AXI Clock Register
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_OFFSET 31
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLEAR_MASK 0x80000000
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_OFF 0b0
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_ON 0b1
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b00
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b01
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b10
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b11
#define HSI_AXI_CLK_REG_FACTOR_M_OFFSET 0
#define HSI_AXI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC0_PHY_CLK_REG 0x00001400//GMAC0 PHY Clock Register
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC0_GAR_REG 0x0000140c//GMAC0 Gating And Reset Register
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_OFFSET 17
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_CLEAR_MASK 0x00020000
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_ASSERT 0b0
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_DE_ASSERT 0b1
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_OFFSET 16
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_CLEAR_MASK 0x00010000
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_ASSERT 0b0
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_DE_ASSERT 0b1
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_OFFSET 0
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_MASK 0b0
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_PASS 0b1
 
#define TCON_LCD0_CLK_REG 0x00001500//TCON_LCD0 Clock Register
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_OFFSET 31
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLEAR_MASK 0x80000000
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_OFF 0b0
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_ON 0b1
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110
#define TCON_LCD0_CLK_REG_FACTOR_M_OFFSET 0
#define TCON_LCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define TCON_LCD0_GAR_REG 0x00001504//TCON_LCD0 Gating And Reset Register
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_OFFSET 16
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_CLEAR_MASK 0x00010000
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_ASSERT 0b0
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_DE_ASSERT 0b1
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_OFFSET 0
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_MASK 0b0
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_PASS 0b1
 
#define LVDS0_GAR_REG 0x00001544//LVDS0 Gating And Reset Register
#define LVDS0_GAR_REG_LVDS0_RST_N_OFFSET 16
#define LVDS0_GAR_REG_LVDS0_RST_N_CLEAR_MASK 0x00010000
#define LVDS0_GAR_REG_LVDS0_RST_N_ASSERT 0b0
#define LVDS0_GAR_REG_LVDS0_RST_N_DE_ASSERT 0b1
 
#define MIPI_DSI00_CLK_REG 0x00001580//MIPI_DSI00 Clock Register
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_OFFSET 31
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLEAR_MASK 0x80000000
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_ON 0b1
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010
#define MIPI_DSI00_CLK_REG_FACTOR_M_OFFSET 0
#define MIPI_DSI00_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define MIPI_DSI00_GAR_REG 0x00001584//MIPI_DSI00 Gating And Reset Register
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_OFFSET 16
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_CLEAR_MASK 0x00010000
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_ASSERT 0b0
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_DE_ASSERT 0b1
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_OFFSET 0
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_MASK 0b0
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_PASS 0b1
 
#define COMBOPHY0_CLK_REG 0x000015c0//COMBOPHY0 Clock Register
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_OFFSET 31
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLEAR_MASK 0x80000000
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_OFF 0b0
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_ON 0b1
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110
#define COMBOPHY0_CLK_REG_FACTOR_M_OFFSET 0
#define COMBOPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define TCON_TV0_eDP_CLK_REG 0x00001600//TCON_TV0_eDP Clock Register
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_OFFSET 31
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLEAR_MASK 0x80000000
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_OFF 0b0
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_ON 0b1
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110
#define TCON_TV0_eDP_CLK_REG_FACTOR_M_OFFSET 0
#define TCON_TV0_eDP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define TCON_TV0_GAR_REG 0x00001604//TCON_TV0 Gating And Reset Register
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_OFFSET 16
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_CLEAR_MASK 0x00010000
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_ASSERT 0b0
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_DE_ASSERT 0b1
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_OFFSET 0
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_MASK 0b0
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_PASS 0b1
 
#define eDP_GAR_REG 0x0000164c//eDP Gating And Reset Register
#define eDP_GAR_REG_EDP_RST_N_OFFSET 16
#define eDP_GAR_REG_EDP_RST_N_CLEAR_MASK 0x00010000
#define eDP_GAR_REG_EDP_RST_N_ASSERT 0b0
#define eDP_GAR_REG_EDP_RST_N_DE_ASSERT 0b1
#define eDP_GAR_REG_EDP_AHB_CLK_EN_OFFSET 0
#define eDP_GAR_REG_EDP_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define eDP_GAR_REG_EDP_AHB_CLK_EN_MASK 0b0
#define eDP_GAR_REG_EDP_AHB_CLK_EN_PASS 0b1
 
#define VO0_REG_GAR_REG 0x000016c4//VO0_REG Gating And Reset Register
#define VO0_REG_GAR_REG_VO0_REG_RST_N_OFFSET 16
#define VO0_REG_GAR_REG_VO0_REG_RST_N_CLEAR_MASK 0x00010000
#define VO0_REG_GAR_REG_VO0_REG_RST_N_ASSERT 0b0
#define VO0_REG_GAR_REG_VO0_REG_RST_N_DE_ASSERT 0b1
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_OFFSET 0
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_MASK 0b0
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_PASS 0b1
 
#define VO1_REG_GAR_REG 0x000016cc//VO1_REG Gating And Reset Register
#define VO1_REG_GAR_REG_VO1_REG_RST_N_OFFSET 16
#define VO1_REG_GAR_REG_VO1_REG_RST_N_CLEAR_MASK 0x00010000
#define VO1_REG_GAR_REG_VO1_REG_RST_N_ASSERT 0b0
#define VO1_REG_GAR_REG_VO1_REG_RST_N_DE_ASSERT 0b1
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_OFFSET 0
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_MASK 0b0
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_PASS 0b1
 
#define VIDEO_OUT0_GAR_REG 0x000016e4//VIDEO_OUT0 Gating And Reset Register
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_OFFSET 16
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_CLEAR_MASK 0x00010000
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_ASSERT 0b0
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_DE_ASSERT 0b1
 
#define LEDC_CLK_REG 0x00001700//LEDC Clock Register
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b0
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1
#define LEDC_CLK_REG_FACTOR_M_OFFSET 0
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define LEDC_GAR_REG 0x00001704//LEDC Gating And Reset Register
#define LEDC_GAR_REG_LEDC_RST_N_OFFSET 16
#define LEDC_GAR_REG_LEDC_RST_N_CLEAR_MASK 0x00010000
#define LEDC_GAR_REG_LEDC_RST_N_ASSERT 0b0
#define LEDC_GAR_REG_LEDC_RST_N_DE_ASSERT 0b1
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_OFFSET 0
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_CLEAR_MASK 0x00000001
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_MASK 0b0
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_PASS 0b1
 
#define CSI_MASTER0_CLK_REG 0x00001800//CSI Master0 Clock Register
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b011
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b100
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b110
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_MASTER1_CLK_REG 0x00001804//CSI Master1 Clock Register
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b011
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b100
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b110
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_MASTER2_CLK_REG 0x00001808//CSI Master2 Clock Register
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK 0b000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b011
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b100
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b110
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_CLK_REG 0x00001840//CSI Clock Register
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b001
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b110
#define CSI_CLK_REG_CLK_SRC_SEL_VEPLL 0b111
#define CSI_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define ISP_CLK_REG 0x00001860//ISP Clock Register
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b001
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b110
#define ISP_CLK_REG_CLK_SRC_SEL_VEPLL 0b111
#define ISP_CLK_REG_FACTOR_M_OFFSET 0
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define VIDEO_IN_GAR_REG 0x00001884//VIDEO_IN Gating And Reset Register
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_OFFSET 16
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_CLEAR_MASK 0x00010000
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_ASSERT 0b0
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_DE_ASSERT 0b1
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_OFFSET 0
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_CLEAR_MASK 0x00000001
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_MASK 0b0
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_PASS 0b1
 
#define PERI0PLL_GATE_EN_REG 0x00001908//PERI0PLL Gate Enable Register
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_OFFSET 31
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_CLEAR_MASK 0x80000000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI1PLL_GATE_EN_REG 0x0000190c//PERI1PLL Gate Enable Register
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_OFFSET 31
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_CLEAR_MASK 0x80000000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_OFFSET 28
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK 0x04000000
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET 24
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET 22
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_OFFSET 12
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00001000
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000800
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000400
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET 6
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define VIDEOPLL_GATE_EN_REG 0x00001910//VIDEOPLL Gate Enable Register
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET 22
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00200000
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET 20
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET 18
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET 6
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000040
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000020
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET 4
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET 2
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000004
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
 
#define GPUPLL_GATE_EN_REG 0x00001914//GPUPLL Gate Enable Register
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_OFFSET 16
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_DISABLE 0b0
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_ENABLE 0b1
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_OFFSET 0
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_AUTO 0b0
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_NO_AUTO 0b1
 
#define VEPLL_GATE_EN_REG 0x00001918//VEPLL Gate Enable Register
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_OFFSET 16
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_DISABLE 0b0
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_ENABLE 0b1
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_OFFSET 0
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_AUTO 0b0
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_NO_AUTO 0b1
 
#define AUDIOPLL_GATE_EN_REG 0x0000191c//AUDIOPLL Gate Enable Register
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_OFFSET 18
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_DISABLE 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_ENABLE 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_OFFSET 17
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_DISABLE 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_ENABLE 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_OFFSET 16
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_DISABLE 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_ENABLE 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_OFFSET 2
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_CLEAR_MASK 0x00000004
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_AUTO 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_NO_AUTO 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_OFFSET 1
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_AUTO 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_OFFSET 0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_AUTO 0b0
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI0PLL_GATE_STAT_REG 0x00001988//PERI0PLL Gate Status Register
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 27
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK 0x08000000
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 26
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK 0x04000000
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 25
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK 0x02000000
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 24
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 23
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK 0x00800000
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 22
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK 0x00400000
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 21
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK 0x00200000
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 20
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 19
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK 0x00080000
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 18
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK 0x00040000
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 17
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK 0x00020000
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 16
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1
 
#define PERI1PLL_GATE_STAT_REG 0x0000198c//PERI1PLL Gate Status Register
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_OFFSET 28
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_CLEAR_MASK 0x10000000
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 27
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK 0x08000000
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 26
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK 0x04000000
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 25
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK 0x02000000
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET 24
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK 0x01000000
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 23
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK 0x00800000
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET 22
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK 0x00400000
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 21
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK 0x00200000
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 20
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK 0x00100000
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 19
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK 0x00080000
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 18
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK 0x00040000
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 17
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK 0x00020000
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 16
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK 0x00010000
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1
 
#define VIDEOPLL_GATE_STAT_REG 0x00001990//VIDEOPLL Gate Status Register
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET 22
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK 0x00400000
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET 21
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK 0x00200000
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET 20
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK 0x00100000
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET 18
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK 0x00040000
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET 17
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK 0x00020000
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET 16
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE 0b1
 
#define GPUPLL_GATE_STAT_REG 0x00001994//GPUPLL Gate Status Register
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_OFFSET 16
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_CLEAR_MASK 0x00010000
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_DISABLE 0b0
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_ENABLE 0b1
 
#define VEPLL_GATE_STAT_REG 0x00001998//VEPLL Gate Status Register
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_OFFSET 16
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_CLEAR_MASK 0x00010000
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_DISABLE 0b0
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_ENABLE 0b1
 
#define AUDIOPLL_GATE_STAT_REG 0x0000199c//AUDIOPLL Gate Status Register
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_OFFSET 18
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_CLEAR_MASK 0x00040000
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_DISABLE 0b0
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_ENABLE 0b1
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_OFFSET 17
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_CLEAR_MASK 0x00020000
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_DISABLE 0b0
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_ENABLE 0b1
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_OFFSET 16
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_CLEAR_MASK 0x00010000
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_DISABLE 0b0
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_ENABLE 0b1
 
#define RES24M_GATE_EN_REG 0x00001a00//RES 24M Gate Enable Register
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_OFFSET 0
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_CLEAR_MASK 0x00000001
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_DISABLE 0b0
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_ENABLE 0b1
 
#define PLL_FO0_EN_REG 0x00001a10//PLL Fanout0 Enable Register
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_OFFSET 0
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_CLEAR_MASK 0x00000001
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_DISABLE 0b0
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_ENABLE 0b1
 
#define PLL_OPG_BYPASS_REG 0x00001a20//PLL Output Gate Bypass Register
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET 0
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK 0x00000001
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE 0b0
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE 0b1
 
#define CM_VIDEO_IN_CFG_REG 0x00001b00//CM VIDEO_IN Enable Configuration Register
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_OFFSET 16
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_CLEAR_MASK 0x00030000
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_OFF 0b01
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_ON 0b10
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_OFFSET 0
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_DISABLE 0b0
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_ENABLE 0b1
 
#define CM_VE_CFG_REG 0x00001b10//CM VE Enable Configuration Register
#define CM_VE_CFG_REG_CM_VE_STATUS_OFFSET 16
#define CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK 0x00030000
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF 0b01
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON 0b10
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET 0
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE 0b0
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE 0b1
 
#define CM_HSI_CFG_REG 0x00001b28//CM HSI Enable Configuration Register
#define CM_HSI_CFG_REG_CM_HSI_STATUS_OFFSET 16
#define CM_HSI_CFG_REG_CM_HSI_STATUS_CLEAR_MASK 0x00030000
#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_OFF 0b01
#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_ON 0b10
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_OFFSET 0
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_DISABLE 0b0
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_ENABLE 0b1
 
#define CM_VIDEO_OUT0_CFG_REG 0x00001b34//CM VIDEO_OUT0 Enable Configuration Register
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_OFFSET 16
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_CLEAR_MASK 0x00030000
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_OFF 0b01
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_ON 0b10
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_OFFSET 0
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_DISABLE 0b0
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_ENABLE 0b1
 
#define AXI_MON_GAR_REG 0x00001c00//AXI MON Gating And Reset Register
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_OFFSET 19
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_CLEAR_MASK 0x00080000
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_ASSERT 0b0
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_DE_ASSERT 0b1
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_OFFSET 18
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_CLEAR_MASK 0x00040000
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_ASSERT 0b0
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_DE_ASSERT 0b1
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_OFFSET 17
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_CLEAR_MASK 0x00020000
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_ASSERT 0b0
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_DE_ASSERT 0b1
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_OFFSET 16
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_CLEAR_MASK 0x00010000
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_ASSERT 0b0
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_DE_ASSERT 0b1
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_OFFSET 3
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_CLEAR_MASK 0x00000008
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_MASK 0b0
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_PASS 0b1
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_OFFSET 2
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_CLEAR_MASK 0x00000004
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_MASK 0b0
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_PASS 0b1
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_OFFSET 1
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_CLEAR_MASK 0x00000002
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_MASK 0b0
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_PASS 0b1
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_OFFSET 0
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_CLEAR_MASK 0x00000001
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_MASK 0b0
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_PASS 0b1
 
#define AHB_MON_GAR_REG 0x00001c04//AHB MON Gating And Reset Register
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_OFFSET 17
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_CLEAR_MASK 0x00020000
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_ASSERT 0b0
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_DE_ASSERT 0b1
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_OFFSET 16
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_CLEAR_MASK 0x00010000
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_ASSERT 0b0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_DE_ASSERT 0b1
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_OFFSET 1
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_CLEAR_MASK 0x00000002
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_MASK 0b0
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_PASS 0b1
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_OFFSET 0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_CLEAR_MASK 0x00000001
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_MASK 0b0
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_PASS 0b1
 
#define CCU_SEC_SWITCH_REG 0x00001f00//CCU Security Switch Register
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1
 
#define DAP_REQ_CTRL_REG 0x00001f10//DAP REQ Control Register
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_OFFSET 0
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_CLEAR_MASK 0x00000001
 
#define PLL_CFG0_REG 0x00001f20//PLL Configuration0 Register
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff
 
#define PLL_CFG1_REG 0x00001f24//PLL Configuration1 Register
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff
 
#define PLL_CFG2_REG 0x00001f28//PLL Configuration2 Register
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff
 
#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c//PLL Lock Debug Control Register
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x03f00000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL0 0b0000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL1 0b0001
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL2 0b0010
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0011
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0100
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL 0b0101
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL 0b0110
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0111
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b1000
 
#define CCU_FAN_GATE_REG 0x00001f30//CCU FANOUT CLOCK GATE Register
#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET 4
#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK 0x00000010
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1
 
#define CLK27M_FAN_REG 0x00001f34//CLK27M FANOUT Register
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X 0b010
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f
 
#define CLK_FAN_REG 0x00001f38//CLK FANOUT Register
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1
#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0
#define CLK_FAN_REG_PCLK_DIV_OFFSET 0
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f
 
#define CCU_FAN_REG 0x00001f3c//CCU FANOUT Register
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_OFFSET 31
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_CLEAR_MASK 0x80000000
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_PERI0_160M_10 0b0
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_RC_16M 0b1
#define CCU_FAN_REG_FANOUT_CLK2_EN_OFFSET 23
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLEAR_MASK 0x00800000
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK1_EN_OFFSET 22
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLEAR_MASK 0x00400000
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK0_EN_OFFSET 21
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLEAR_MASK 0x00200000
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_FANOUT_CLK2_SEL_OFFSET 6
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLEAR_MASK 0x000001c0
#define CCU_FAN_REG_FANOUT_CLK2_SEL_FANOUT_32K_CLK_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK2_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_FANOUT_CLK1_SEL_OFFSET 3
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLEAR_MASK 0x00000038
#define CCU_FAN_REG_FANOUT_CLK1_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK1_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_FANOUT_CLK0_SEL_OFFSET 0
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLEAR_MASK 0x00000007
#define CCU_FAN_REG_FANOUT_CLK0_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK27M 0b101
#define CCU_FAN_REG_FANOUT_CLK0_SEL_PCLK 0b110
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK50M_FROM_PERI0_150M_3 0b111
 
#define CLK_DBG_REG 0x00001f50//Clock Debug Register
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_OFFSET 24
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_CLEAR_MASK 0x03000000
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV1 0b00
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV2 0b01
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV4 0b10
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV8 0b11
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_OFFSET 16
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_CLEAR_MASK 0x00070000
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_STBY_SYS_BACKDOOR_CLK 0b000
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_DISPLL0_CK_HS 0b001
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_OFFSET 4
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CLEAR_MASK 0x000001f0
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_VE0_PSENSOR_CLK 0b0000
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_GPU_PSENSOR_CLK 0b0001
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_DRAMC_PSENSOR_CLK 0b0010
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_3 0b0011
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_0 0b0100
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_1 0b0101
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_0 0b0110
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_1 0b0111
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_0 0b1000
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_1 0b1001
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_2 0b1010
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_3 0b1011
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_0 0b1100
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_1 0b1101
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_0 0b1110
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_1 0b1111
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK 0x00000007
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLK 0b000
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLK 0b001
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLK 0b010
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLK 0b011
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLK 0b100
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLK 0b101
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CE_SYS_CLK 0b110
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CPU_SYS_DP_CLK 0b111
 
#define CCU_VERSION_REG 0x00001ff0//CCU Version Register
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK 0xffff0000
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK 0x0000ffff
 
#define APB2_CLK_SRC_OSC24M \
    (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_OSC32K \
    (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_PSI \
    (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_PLL6                    \
    (APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS \
     << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_RATE_N_1 (0x0 << 8)
#define APB2_CLK_RATE_N_2 (0x1 << 8)
#define APB2_CLK_RATE_N_4 (0x2 << 8)
#define APB2_CLK_RATE_N_8 (0x3 << 8)
#define APB2_CLK_RATE_N_MASK (3 << 8)
#define APB2_CLK_RATE_M(m) (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
#define APB2_CLK_RATE_M_MASK (3 << APB1_CLK_REG_FACTOR_M_OFFSET)
 
/* MMC clock bit field */
#define SMHC0_CLK_SRC_PERI0_400M_FREQ (400000000)
#define SMHC2_CLK_SRC_PERI0_800M_FREQ (800000000)
 
#define CCM_MMC_CTRL_M(x) ((x) -1)
#define CCM_MMC_CTRL_N(x) ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
#define CCM_MMC_CTRL_OSCM24 \
    (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCM_MMC_CTRL_PLL6X2               \
    (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M \
     << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCM_MMC_CTRL_PLL_PERIPH2X2        \
    (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M \
     << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCM_MMC_CTRL_ENABLE                     \
    (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON \
     << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
/* if doesn't have these delays */
#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
 
/* Module gate/reset shift*/
#define RESET_SHIFT (16)
#define GATING_SHIFT (0)
 
/* pll list */
#define CCU_PLL_CPUX_CTRL_REG (SUNXI_CCU_BASE + 0x00)
#define CCU_PLL_DDR0_CTRL_REG (SUNXI_CCU_BASE + 0x10)
#define CCU_PLL_DDR1_CTRL_REG (SUNXI_CCU_BASE + 0x18)
#define CCU_PLL_PERI0_CTRL_REG (SUNXI_CCU_BASE + 0x20)
#define CCU_PLL_PERI1_CTRL_REG (SUNXI_CCU_BASE + 0x28)
#define CCU_PLL_GPU_CTRL_REG (SUNXI_CCU_BASE + 0x30)
#define CCU_PLL_VIDE00_CTRL_REG (SUNXI_CCU_BASE + 0x40)
#define CCU_PLL_VIDE01_CTRL_REG (SUNXI_CCU_BASE + 0x48)
#define CCU_PLL_VIDE02_CTRL_REG (SUNXI_CCU_BASE + 0x50)
#define CCU_PLL_VIDE03_CTRL_REG (SUNXI_CCU_BASE + 0x68)
#define CCU_PLL_VE_CTRL_REG (SUNXI_CCU_BASE + 0x58)
#define CCU_PLL_COM_CTRL_REG (SUNXI_CCU_BASE + 0x60)
#define CCU_PLL_AUDIO_CTRL_REG (SUNXI_CCU_BASE + 0x78)
 
#define CCU_PLL_HSIC_CTRL_REG (SUNXI_CCU_BASE + 0x70)
 
/* cfg list */
#define CCU_AHB0_CFG_REG (SUNXI_CCU_BASE + AHB_CLK_REG)
#define CCU_CPUX_AXI_CFG_REG (SUNXI_CCU_BASE + 0x500)
 
#define CCU_VE_CLK_REG (SUNXI_CCU_BASE + 0x690)
#define CCU_VE_BGR_REG (SUNXI_CCU_BASE + 0x69C)
 
/*SYS*/
#define CCU_DMA_BGR_REG (SUNXI_CCU_BASE + 0x70C)
#define CCU_AVS_CLK_REG (SUNXI_CCU_BASE + 0x750)
#define CCU_AVS_BGR_REG (SUNXI_CCU_BASE + 0x74C)
 
/*IOMMU*/
#define CCU_IOMMU_BGR_REG (SUNXI_CCU_BASE + 0x7bc)
// #define IOMMU_AUTO_GATING_REG              (SUNXI_IOMMU_BASE + 0X40)
 
/* storage */
#define CCU_MBUS_GATE_ENABLE_REG (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)
 
#define CCU_NAND_CLK_REG (SUNXI_CCU_BASE + 0x810)
#define CCU_NAND_BGR_REG (SUNXI_CCU_BASE + 0x82C)
 
#define CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG)
#define CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG)
#define CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG)
#define CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_GAR_REG)
 
/*normal interface*/
#define CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_GAR_REG)
#define CCU_TWI_BGR_REG (SUNXI_CCU_BASE + 0x91C)
 
#define CCU_SCR_BGR_REG (SUNXI_CCU_BASE + 0x93C)
 
#define CCU_SPI0_CLK_REG (SUNXI_CCU_BASE + 0x940)
#define CCU_SPI1_CLK_REG (SUNXI_CCU_BASE + 0x944)
#define CCU_SPI_BGR_CLK_REG (SUNXI_CCU_BASE + 0x96C)
#define CCU_USB0_CLK_REG (SUNXI_CCU_BASE + 0xA70)
#define CCU_USB_BGR_REG (SUNXI_CCU_BASE + 0xA8C)
 
/*DMA*/
#define DMA_GATING_BASE CCU_DMA_BGR_REG
#define DMA_GATING_PASS (1)
#define DMA_GATING_BIT (0)
 
/* CE CLK Register */
#define CE_USE_PLATFORM_CLOCK_FUNC
#define SUNXI_CE_MBUS_MAT_CLK_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATE_EN_REG)
#define SUNXI_CE_GATING_ON 1
#define SUNXI_CE_MBUS_MAT_CLK_GATE_OFFSET MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET
 
#define SUNXI_CE_MBUS_CLK_REG (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)
#define SUNXI_CE_MBUS_CLK_GATE_OFFSET MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET
 
#define SUNXI_CE_SYS_CLK_REG (SUNXI_CCU_BASE + CE_SYS_CLK_REG)
#define SUNXI_CE_SYS_GATING_OFFSET CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET
#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET
#define SUNXI_CE_SRC_600M CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M
#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET CE_SYS_CLK_REG_FACTOR_M_OFFSET
#define SUNXI_CE_FACTOR_0 0b0
 
#define SUNXI_CE_SYS_GATING_RESET_REG (SUNXI_CCU_BASE + CE_SYS_GAR_REG)
#define SUNXI_CE_GATING_OFFSET CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK
#define SUNXI_CE_SYS_GATING_RESET_OFFSET CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET
 
/*gpadc gate and reset reg*/
#define CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC0_GAR_REG)
#define CCU_GPADC_CLK_REG (SUNXI_CCU_BASE + GPADC0_CLK_REG)
 
/*lpadc gate and reset reg*/
#define CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + 0x0A9C)
 
/* ehci */
#define BUS_CLK_GATING_REG 0x60
#define BUS_SOFTWARE_RESET_REG 0x2c0
#define USBPHY_CONFIG_REG 0xcc
 
#define USBEHCI0_RST_BIT 24
#define USBEHCI0_GATIING_BIT 24
#define USBPHY0_RST_BIT 0
#define USBPHY0_SCLK_GATING_BIT 8
 
#define USBEHCI1_RST_BIT 25
#define USBEHCI1_GATIING_BIT 25
#define USBPHY1_RST_BIT 1
#define USBPHY1_SCLK_GATING_BIT 9
 
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET \
    (SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET (SMHC0_GAR_REG_SMHC0_RST_N_OFFSET)
 
 
#endif// __SUN65IW1_REG_CCU_H__