SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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Macros
reg-ccu.h File Reference
#include <reg-ncat.h>
Include dependency graph for reg-ccu.h:

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Macros

#define PLL_PERI0_CTRL_REG   0x000000a0
 
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_PERI0_PAT0_CTRL_REG   0x000000a8
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI0_PAT1_CTRL_REG   0x000000ac
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI0_BIAS_REG   0x000000b0
 
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_PERI1_CTRL_REG   0x000000c0
 
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_PERI1_PAT0_CTRL_REG   0x000000c8
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI1_PAT1_CTRL_REG   0x000000cc
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI1_BIAS_REG   0x000000d0
 
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_GPU_CTRL_REG   0x000000e0
 
#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_GPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_GPU_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_GPU_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_GPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_GPU_PAT0_CTRL_REG   0x000000e8
 
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_GPU_PAT1_CTRL_REG   0x000000ec
 
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_GPU_BIAS_REG   0x000000f0
 
#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO0_CTRL_REG   0x00000120
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET   16
 
#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000128
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO0_PAT1_CTRL_REG   0x0000012c
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO0_BIAS_REG   0x00000130
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO1_CTRL_REG   0x00000140
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET   16
 
#define PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO1_BIAS_REG   0x00000150
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO2_CTRL_REG   0x00000160
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_VIDEO2_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_VIDEO2_CTRL_REG_PLL_P1_OFFSET   16
 
#define PLL_VIDEO2_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000168
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO2_PAT1_CTRL_REG   0x0000016c
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO2_BIAS_REG   0x00000170
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VE_CTRL_REG   0x00000220
 
#define PLL_VE_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VE_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VE_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VE_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VE_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VE_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_VE_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VE_PAT0_CTRL_REG   0x00000228
 
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VE_PAT1_CTRL_REG   0x0000022c
 
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VE_BIAS_REG   0x00000230
 
#define PLL_VE_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_AUDIO0_CTRL_REG   0x00000260
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET   16
 
#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK   0x003f0000
 
#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_AUDIO0_PAT0_CTRL_REG   0x00000268
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO0_PAT1_CTRL_REG   0x0000026c
 
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO0_BIAS_REG   0x00000270
 
#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_AUDIO1_CTRL_REG   0x00000280
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000
 
#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET   16
 
#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000
 
#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_AUDIO1_PAT0_CTRL_REG   0x00000288
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO1_PAT1_CTRL_REG   0x0000028c
 
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO1_BIAS_REG   0x00000290
 
#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define AHB_CLK_REG   0x00000500
 
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01
 
#define AHB_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10
 
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define AHB_CLK_REG_FACTOR_M_OFFSET   0
 
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB0_CLK_REG   0x00000510
 
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01
 
#define APB0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10
 
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define APB0_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB1_CLK_REG   0x00000518
 
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01
 
#define APB1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10
 
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define APB1_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB_UART_CLK_REG   0x00000538
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b001
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b010
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b011
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS   0b100
 
#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CPU_SYS_DP_CLK_REG   0x00000548
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_OFFSET   31
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_OFFSET   27
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_CLEAR_MASK   0x08000000
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_INVALID   0b0
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_VALID   0b1
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_OFFSET   24
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_CLEAR_MASK   0x07000000
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_SYS_24M_CLK   0b000
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0PLL2X   0b001
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL4X   0b010
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0_800M   0b011
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL3X   0b100
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_HDR_CLK   0b101
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_OFFSET   0
 
#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_CLEAR_MASK   0x0000001f
 
#define CPUX_GIC_CLK_REG   0x00000560
 
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_OFFSET   31
 
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b001
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define CPUX_GIC_CLK_REG_FACTOR_M_OFFSET   0
 
#define CPUX_GIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define NSI_CLK_REG   0x00000580
 
#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET   31
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NSI_CLK_REG_NSI_DFS_EN_OFFSET   28
 
#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK   0x10000000
 
#define NSI_CLK_REG_NSI_DFS_EN_DISABLE   0b0
 
#define NSI_CLK_REG_NSI_DFS_EN_ENABLE   0b1
 
#define NSI_CLK_REG_NSI_UPD_OFFSET   27
 
#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK   0x08000000
 
#define NSI_CLK_REG_NSI_UPD_INVALID   0b0
 
#define NSI_CLK_REG_NSI_UPD_VALID   0b1
 
#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET   24
 
#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK   0x07000000
 
#define NSI_CLK_REG_NSI_CLK_SEL_SYS_24M_CLK   0b000
 
#define NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL3X   0b001
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS   0b010
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M   0b011
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M   0b100
 
#define NSI_CLK_REG_NSI_CLK_SEL_HDR_CLK   0b101
 
#define NSI_CLK_REG_NSI_DIV1_OFFSET   0
 
#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK   0x0000001f
 
#define NSI_GAR_REG   0x00000584
 
#define NSI_GAR_REG_NSI_CFG_RST_N_OFFSET   17
 
#define NSI_GAR_REG_NSI_CFG_RST_N_CLEAR_MASK   0x00020000
 
#define NSI_GAR_REG_NSI_CFG_RST_N_ASSERT   0b0
 
#define NSI_GAR_REG_NSI_CFG_RST_N_DE_ASSERT   0b1
 
#define NSI_GAR_REG_NSI_RST_N_OFFSET   16
 
#define NSI_GAR_REG_NSI_RST_N_CLEAR_MASK   0x00010000
 
#define NSI_GAR_REG_NSI_RST_N_ASSERT   0b0
 
#define NSI_GAR_REG_NSI_RST_N_DE_ASSERT   0b1
 
#define NSI_GAR_REG_NSI_CFG_CLK_EN_OFFSET   0
 
#define NSI_GAR_REG_NSI_CFG_CLK_EN_CLEAR_MASK   0x00000001
 
#define NSI_GAR_REG_NSI_CFG_CLK_EN_MASK   0x0
 
#define NSI_GAR_REG_NSI_CFG_CLK_EN_PASS   0b1
 
#define MBUS_CLK_REG   0x00000588
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET   31
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK   0x80000000
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON   0b1
 
#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET   28
 
#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK   0x10000000
 
#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE   0b0
 
#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE   0b1
 
#define MBUS_CLK_REG_MBUS_UPD_OFFSET   27
 
#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK   0x08000000
 
#define MBUS_CLK_REG_MBUS_UPD_INVALID   0b0
 
#define MBUS_CLK_REG_MBUS_UPD_VALID   0b1
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET   24
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK   0x07000000
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_24M_CLK   0b000
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS   0b001
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M   0b010
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M   0b011
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_HDR_CLK   0b100
 
#define MBUS_CLK_REG_MBUS_DIV1_OFFSET   0
 
#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK   0x0000001f
 
#define IOMMU_GAR_REG   0x0000058c
 
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_OFFSET   0
 
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_MASK   0x0
 
#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_PASS   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG   0x000005c0
 
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31
 
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000
 
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29
 
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000
 
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_OFFSET   28
 
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_CLEAR_MASK   0x10000000
 
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   15
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00008000
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   14
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00004000
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   13
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00002000
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_OFFSET   11
 
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000800
 
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_OFFSET   8
 
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100
 
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_OFFSET   7
 
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080
 
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_OFFSET   3
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_OFFSET   2
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_OFFSET   1
 
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002
 
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG   0x000005e0
 
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_OFFSET   28
 
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_CLEAR_MASK   0x10000000
 
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET   8
 
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_CLEAR_MASK   0x00000100
 
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_OFFSET   7
 
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_CLEAR_MASK   0x00000080
 
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_OFFSET   5
 
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000020
 
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_OFFSET   2
 
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000004
 
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_OFFSET   1
 
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000002
 
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_CLK_GATE_EN_REG   0x000005e4
 
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_OFFSET   11
 
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_CLEAR_MASK   0x00000800
 
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_PASS   0b1
 
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_OFFSET   9
 
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_CLEAR_MASK   0x00000200
 
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_PASS   0b1
 
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_OFFSET   8
 
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_CLEAR_MASK   0x00000100
 
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_PASS   0b1
 
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET   2
 
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_CLEAR_MASK   0x00000004
 
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_SECURE_DEBUG   0b1
 
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_OFFSET   1
 
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_CLEAR_MASK   0x00000002
 
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_PASS   0b1
 
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_OFFSET   0
 
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_CLEAR_MASK   0x00000001
 
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_MASK   0x0
 
#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_PASS   0b1
 
#define DMA0_GAR_REG   0x00000704
 
#define DMA0_GAR_REG_DMA0_RST_N_OFFSET   16
 
#define DMA0_GAR_REG_DMA0_RST_N_CLEAR_MASK   0x00010000
 
#define DMA0_GAR_REG_DMA0_RST_N_ASSERT   0b0
 
#define DMA0_GAR_REG_DMA0_RST_N_DE_ASSERT   0b1
 
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_OFFSET   0
 
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_MASK   0x0
 
#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_PASS   0b1
 
#define SPINLOCK_GAR_REG   0x00000724
 
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_OFFSET   16
 
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_CLEAR_MASK   0x00010000
 
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_ASSERT   0b0
 
#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_DE_ASSERT   0b1
 
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_OFFSET   0
 
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_MASK   0x0
 
#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_PASS   0b1
 
#define MSGBOX_CPUX_GAR_REG   0x00000744
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_OFFSET   16
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_CLEAR_MASK   0x00010000
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_ASSERT   0b0
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_DE_ASSERT   0b1
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_OFFSET   0
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_MASK   0x0
 
#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_PASS   0b1
 
#define MSGBOX_CPUS_GAR_REG   0x0000074c
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_OFFSET   16
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_CLEAR_MASK   0x00010000
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_ASSERT   0b0
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_DE_ASSERT   0b1
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_OFFSET   0
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_MASK   0x0
 
#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_PASS   0b1
 
#define PWM0_GAR_REG   0x00000784
 
#define PWM0_GAR_REG_PWM0_RST_N_OFFSET   16
 
#define PWM0_GAR_REG_PWM0_RST_N_CLEAR_MASK   0x00010000
 
#define PWM0_GAR_REG_PWM0_RST_N_ASSERT   0b0
 
#define PWM0_GAR_REG_PWM0_RST_N_DE_ASSERT   0b1
 
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_OFFSET   0
 
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_MASK   0x0
 
#define PWM0_GAR_REG_PWM0_APB_CLK_EN_PASS   0b1
 
#define DCU_GAR_REG   0x000007a4
 
#define DCU_GAR_REG_DCU_RST_N_OFFSET   16
 
#define DCU_GAR_REG_DCU_RST_N_CLEAR_MASK   0x00010000
 
#define DCU_GAR_REG_DCU_RST_N_ASSERT   0b0
 
#define DCU_GAR_REG_DCU_RST_N_DE_ASSERT   0b1
 
#define DCU_GAR_REG_DCU_CLK_EN_OFFSET   0
 
#define DCU_GAR_REG_DCU_CLK_EN_CLEAR_MASK   0x00000001
 
#define DCU_GAR_REG_DCU_CLK_EN_MASK   0x0
 
#define DCU_GAR_REG_DCU_CLK_EN_PASS   0b1
 
#define DAP_GAR_REG   0x000007ac
 
#define DAP_GAR_REG_DAP_RST_N_OFFSET   16
 
#define DAP_GAR_REG_DAP_RST_N_CLEAR_MASK   0x00010000
 
#define DAP_GAR_REG_DAP_RST_N_ASSERT   0b0
 
#define DAP_GAR_REG_DAP_RST_N_SECURE_DEBUG   0b1
 
#define DAP_GAR_REG_DAP_AHB_CLK_EN_OFFSET   0
 
#define DAP_GAR_REG_DAP_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define DAP_GAR_REG_DAP_AHB_CLK_EN_MASK   0x0
 
#define DAP_GAR_REG_DAP_AHB_CLK_EN_SECURE_DEBUG   0b1
 
#define TIMER0_0_CLK_REG   0x00000800
 
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_OFFSET   31
 
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_DISABLE   0b0
 
#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_ENABLE   0b1
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010
 
#define TIMER0_0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_0_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER0_0_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER0_0_CLK_REG_FACTOR_M__1   0b000
 
#define TIMER0_0_CLK_REG_FACTOR_M__2   0b001
 
#define TIMER0_0_CLK_REG_FACTOR_M__4   0b010
 
#define TIMER0_0_CLK_REG_FACTOR_M__8   0b011
 
#define TIMER0_0_CLK_REG_FACTOR_M__16   0b100
 
#define TIMER0_0_CLK_REG_FACTOR_M__32   0b101
 
#define TIMER0_0_CLK_REG_FACTOR_M__64   0b110
 
#define TIMER0_0_CLK_REG_FACTOR_M__128   0b111
 
#define TIMER0_1_CLK_REG   0x00000804
 
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_OFFSET   31
 
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_DISABLE   0b0
 
#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_ENABLE   0b1
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010
 
#define TIMER0_1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_1_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER0_1_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER0_1_CLK_REG_FACTOR_M__1   0b000
 
#define TIMER0_1_CLK_REG_FACTOR_M__2   0b001
 
#define TIMER0_1_CLK_REG_FACTOR_M__4   0b010
 
#define TIMER0_1_CLK_REG_FACTOR_M__8   0b011
 
#define TIMER0_1_CLK_REG_FACTOR_M__16   0b100
 
#define TIMER0_1_CLK_REG_FACTOR_M__32   0b101
 
#define TIMER0_1_CLK_REG_FACTOR_M__64   0b110
 
#define TIMER0_1_CLK_REG_FACTOR_M__128   0b111
 
#define TIMER0_2_CLK_REG   0x00000808
 
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_OFFSET   31
 
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_DISABLE   0b0
 
#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_ENABLE   0b1
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010
 
#define TIMER0_2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_2_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER0_2_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER0_2_CLK_REG_FACTOR_M__1   0b000
 
#define TIMER0_2_CLK_REG_FACTOR_M__2   0b001
 
#define TIMER0_2_CLK_REG_FACTOR_M__4   0b010
 
#define TIMER0_2_CLK_REG_FACTOR_M__8   0b011
 
#define TIMER0_2_CLK_REG_FACTOR_M__16   0b100
 
#define TIMER0_2_CLK_REG_FACTOR_M__32   0b101
 
#define TIMER0_2_CLK_REG_FACTOR_M__64   0b110
 
#define TIMER0_2_CLK_REG_FACTOR_M__128   0b111
 
#define TIMER0_3_CLK_REG   0x0000080c
 
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_OFFSET   31
 
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_DISABLE   0b0
 
#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_ENABLE   0b1
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010
 
#define TIMER0_3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_3_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER0_3_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER0_3_CLK_REG_FACTOR_M__1   0b000
 
#define TIMER0_3_CLK_REG_FACTOR_M__2   0b001
 
#define TIMER0_3_CLK_REG_FACTOR_M__4   0b010
 
#define TIMER0_3_CLK_REG_FACTOR_M__8   0b011
 
#define TIMER0_3_CLK_REG_FACTOR_M__16   0b100
 
#define TIMER0_3_CLK_REG_FACTOR_M__32   0b101
 
#define TIMER0_3_CLK_REG_FACTOR_M__64   0b110
 
#define TIMER0_3_CLK_REG_FACTOR_M__128   0b111
 
#define TIMER0_GAR_REG   0x00000850
 
#define TIMER0_GAR_REG_TIMER0_RST_N_OFFSET   16
 
#define TIMER0_GAR_REG_TIMER0_RST_N_CLEAR_MASK   0x00010000
 
#define TIMER0_GAR_REG_TIMER0_RST_N_ASSERT   0b0
 
#define TIMER0_GAR_REG_TIMER0_RST_N_DE_ASSERT   0b1
 
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_OFFSET   0
 
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_MASK   0x0
 
#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_PASS   0b1
 
#define DE0_CLK_REG   0x00000a00
 
#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET   31
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010
 
#define DE0_CLK_REG_CLK_SRC_SEL_VEPLL   0b011
 
#define DE0_CLK_REG_FACTOR_M_OFFSET   0
 
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DE0_GAR_REG   0x00000a04
 
#define DE0_GAR_REG_DE0_RST_N_OFFSET   16
 
#define DE0_GAR_REG_DE0_RST_N_CLEAR_MASK   0x00010000
 
#define DE0_GAR_REG_DE0_RST_N_ASSERT   0b0
 
#define DE0_GAR_REG_DE0_RST_N_DE_ASSERT   0b1
 
#define DE0_GAR_REG_DE0_AHB_CLK_EN_OFFSET   0
 
#define DE0_GAR_REG_DE0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define DE0_GAR_REG_DE0_AHB_CLK_EN_MASK   0x0
 
#define DE0_GAR_REG_DE0_AHB_CLK_EN_PASS   0b1
 
#define G2D_CLK_REG   0x00000a40
 
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1
 
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b00
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b01
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b10
 
#define G2D_CLK_REG_FACTOR_M_OFFSET   0
 
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define G2D_GAR_REG   0x00000a44
 
#define G2D_GAR_REG_G2D_RST_N_OFFSET   16
 
#define G2D_GAR_REG_G2D_RST_N_CLEAR_MASK   0x00010000
 
#define G2D_GAR_REG_G2D_RST_N_ASSERT   0b0
 
#define G2D_GAR_REG_G2D_RST_N_DE_ASSERT   0b1
 
#define G2D_GAR_REG_G2D_AHB_CLK_EN_OFFSET   0
 
#define G2D_GAR_REG_G2D_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define G2D_GAR_REG_G2D_AHB_CLK_EN_MASK   0x0
 
#define G2D_GAR_REG_G2D_AHB_CLK_EN_PASS   0b1
 
#define EINK_PANEL_CLK_REG   0x00000a64
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET   31
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK   0x80000000
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON   0b1
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100
 
#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET   0
 
#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define EINK_GAR_REG   0x00000a6c
 
#define EINK_GAR_REG_EINK_RST_N_OFFSET   16
 
#define EINK_GAR_REG_EINK_RST_N_CLEAR_MASK   0x00010000
 
#define EINK_GAR_REG_EINK_RST_N_ASSERT   0b0
 
#define EINK_GAR_REG_EINK_RST_N_DE_ASSERT   0b1
 
#define EINK_GAR_REG_EINK_AHB_CLK_EN_OFFSET   0
 
#define EINK_GAR_REG_EINK_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define EINK_GAR_REG_EINK_AHB_CLK_EN_MASK   0x0
 
#define EINK_GAR_REG_EINK_AHB_CLK_EN_PASS   0b1
 
#define VE0_CLK_REG   0x00000a80
 
#define VE0_CLK_REG_VE0_CLK_GATING_OFFSET   31
 
#define VE0_CLK_REG_VE0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VE0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VE0_CLK_REG_CLK_SRC_SEL_VEPLL   0b000
 
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define VE0_CLK_REG_FACTOR_M_OFFSET   0
 
#define VE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VE0_GAR_REG   0x00000a8c
 
#define VE0_GAR_REG_VE0_RST_N_OFFSET   16
 
#define VE0_GAR_REG_VE0_RST_N_CLEAR_MASK   0x00010000
 
#define VE0_GAR_REG_VE0_RST_N_ASSERT   0b0
 
#define VE0_GAR_REG_VE0_RST_N_DE_ASSERT   0b1
 
#define VE0_GAR_REG_VE0_AHB_CLK_EN_OFFSET   0
 
#define VE0_GAR_REG_VE0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define VE0_GAR_REG_VE0_AHB_CLK_EN_MASK   0x0
 
#define VE0_GAR_REG_VE0_AHB_CLK_EN_PASS   0b1
 
#define CE_SYS_CLK_REG   0x00000ac0
 
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET   31
 
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_SECURE_DEBUG   0b1
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010
 
#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011
 
#define CE_SYS_CLK_REG_FACTOR_M_OFFSET   0
 
#define CE_SYS_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CE_SYS_GAR_REG   0x00000ac4
 
#define CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET   16
 
#define CE_SYS_GAR_REG_CE_SYS_RST_N_CLEAR_MASK   0x00010000
 
#define CE_SYS_GAR_REG_CE_SYS_RST_N_ASSERT   0b0
 
#define CE_SYS_GAR_REG_CE_SYS_RST_N_SECURE_DEBUG   0b1
 
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET   0
 
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK   0x0
 
#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_SECURE_DEBUG   0b1
 
#define GPU_CLK_REG   0x00000b20
 
#define GPU_CLK_REG_GPU_CLK_GATING_OFFSET   31
 
#define GPU_CLK_REG_GPU_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GPU_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define GPU_CLK_REG_CLK_SRC_SEL_GPUPLL   0b000
 
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011
 
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100
 
#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b101
 
#define GPU_CLK_REG_FACTOR_M_OFFSET   0
 
#define GPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define GPU_CLK_REG_FACTOR_M_NOT_MASK   0x0000
 
#define GPU_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES   0b0001
 
#define GPU_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES   0b0010
 
#define GPU_CLK_REG_FACTOR_M_MASK_3_CYCLES_AT_16_CYCLES   0b0011
 
#define GPU_CLK_REG_FACTOR_M_MASK_15_CYCLES_AT_16_CYCLES   0b1111
 
#define GPU_GAR_REG   0x00000b24
 
#define GPU_GAR_REG_GPU_RST_N_OFFSET   16
 
#define GPU_GAR_REG_GPU_RST_N_CLEAR_MASK   0x00010000
 
#define GPU_GAR_REG_GPU_RST_N_ASSERT   0b0
 
#define GPU_GAR_REG_GPU_RST_N_DE_ASSERT   0b1
 
#define GPU_GAR_REG_GPU_AHB_CLK_EN_OFFSET   0
 
#define GPU_GAR_REG_GPU_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define GPU_GAR_REG_GPU_AHB_CLK_EN_MASK   0x0
 
#define GPU_GAR_REG_GPU_AHB_CLK_EN_PASS   0b1
 
#define DRAMC_GAR_REG   0x00000c0c
 
#define DRAMC_GAR_REG_DRAMC_RST_N_OFFSET   16
 
#define DRAMC_GAR_REG_DRAMC_RST_N_CLEAR_MASK   0x00010000
 
#define DRAMC_GAR_REG_DRAMC_RST_N_ASSERT   0b0
 
#define DRAMC_GAR_REG_DRAMC_RST_N_DE_ASSERT   0b1
 
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_OFFSET   0
 
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_MASK   0x0
 
#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_PASS   0b1
 
#define SMHC0_CLK_REG   0x00000d00
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC0_GAR_REG   0x00000d0c
 
#define SMHC0_GAR_REG_SMHC0_RST_N_OFFSET   16
 
#define SMHC0_GAR_REG_SMHC0_RST_N_CLEAR_MASK   0x00010000
 
#define SMHC0_GAR_REG_SMHC0_RST_N_ASSERT   0b0
 
#define SMHC0_GAR_REG_SMHC0_RST_N_DE_ASSERT   0b1
 
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET   0
 
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_MASK   0x0
 
#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_PASS   0b1
 
#define SMHC1_CLK_REG   0x00000d10
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC1_GAR_REG   0x00000d1c
 
#define SMHC1_GAR_REG_SMHC1_RST_N_OFFSET   16
 
#define SMHC1_GAR_REG_SMHC1_RST_N_CLEAR_MASK   0x00010000
 
#define SMHC1_GAR_REG_SMHC1_RST_N_ASSERT   0b0
 
#define SMHC1_GAR_REG_SMHC1_RST_N_DE_ASSERT   0b1
 
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_OFFSET   0
 
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_MASK   0x0
 
#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_PASS   0b1
 
#define SMHC2_CLK_REG   0x00000d20
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100
 
#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC2_GAR_REG   0x00000d2c
 
#define SMHC2_GAR_REG_SMHC2_RST_N_OFFSET   16
 
#define SMHC2_GAR_REG_SMHC2_RST_N_CLEAR_MASK   0x00010000
 
#define SMHC2_GAR_REG_SMHC2_RST_N_ASSERT   0b0
 
#define SMHC2_GAR_REG_SMHC2_RST_N_DE_ASSERT   0b1
 
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_OFFSET   0
 
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_MASK   0x0
 
#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_PASS   0b1
 
#define UART0_GAR_REG   0x00000e00
 
#define UART0_GAR_REG_UART0_RST_N_OFFSET   16
 
#define UART0_GAR_REG_UART0_RST_N_CLEAR_MASK   0x00010000
 
#define UART0_GAR_REG_UART0_RST_N_ASSERT   0b0
 
#define UART0_GAR_REG_UART0_RST_N_DE_ASSERT   0b1
 
#define UART0_GAR_REG_UART0_APB_CLK_EN_OFFSET   0
 
#define UART0_GAR_REG_UART0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART0_GAR_REG_UART0_APB_CLK_EN_MASK   0x0
 
#define UART0_GAR_REG_UART0_APB_CLK_EN_PASS   0b1
 
#define UART1_GAR_REG   0x00000e04
 
#define UART1_GAR_REG_UART1_RST_N_OFFSET   16
 
#define UART1_GAR_REG_UART1_RST_N_CLEAR_MASK   0x00010000
 
#define UART1_GAR_REG_UART1_RST_N_ASSERT   0b0
 
#define UART1_GAR_REG_UART1_RST_N_DE_ASSERT   0b1
 
#define UART1_GAR_REG_UART1_APB_CLK_EN_OFFSET   0
 
#define UART1_GAR_REG_UART1_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART1_GAR_REG_UART1_APB_CLK_EN_MASK   0x0
 
#define UART1_GAR_REG_UART1_APB_CLK_EN_PASS   0b1
 
#define UART2_GAR_REG   0x00000e08
 
#define UART2_GAR_REG_UART2_RST_N_OFFSET   16
 
#define UART2_GAR_REG_UART2_RST_N_CLEAR_MASK   0x00010000
 
#define UART2_GAR_REG_UART2_RST_N_ASSERT   0b0
 
#define UART2_GAR_REG_UART2_RST_N_DE_ASSERT   0b1
 
#define UART2_GAR_REG_UART2_APB_CLK_EN_OFFSET   0
 
#define UART2_GAR_REG_UART2_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART2_GAR_REG_UART2_APB_CLK_EN_MASK   0x0
 
#define UART2_GAR_REG_UART2_APB_CLK_EN_PASS   0b1
 
#define UART3_GAR_REG   0x00000e0c
 
#define UART3_GAR_REG_UART3_RST_N_OFFSET   16
 
#define UART3_GAR_REG_UART3_RST_N_CLEAR_MASK   0x00010000
 
#define UART3_GAR_REG_UART3_RST_N_ASSERT   0b0
 
#define UART3_GAR_REG_UART3_RST_N_DE_ASSERT   0b1
 
#define UART3_GAR_REG_UART3_APB_CLK_EN_OFFSET   0
 
#define UART3_GAR_REG_UART3_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART3_GAR_REG_UART3_APB_CLK_EN_MASK   0x0
 
#define UART3_GAR_REG_UART3_APB_CLK_EN_PASS   0b1
 
#define UART4_GAR_REG   0x00000e10
 
#define UART4_GAR_REG_UART4_RST_N_OFFSET   16
 
#define UART4_GAR_REG_UART4_RST_N_CLEAR_MASK   0x00010000
 
#define UART4_GAR_REG_UART4_RST_N_ASSERT   0b0
 
#define UART4_GAR_REG_UART4_RST_N_DE_ASSERT   0b1
 
#define UART4_GAR_REG_UART4_APB_CLK_EN_OFFSET   0
 
#define UART4_GAR_REG_UART4_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART4_GAR_REG_UART4_APB_CLK_EN_MASK   0x0
 
#define UART4_GAR_REG_UART4_APB_CLK_EN_PASS   0b1
 
#define UART5_GAR_REG   0x00000e14
 
#define UART5_GAR_REG_UART5_RST_N_OFFSET   16
 
#define UART5_GAR_REG_UART5_RST_N_CLEAR_MASK   0x00010000
 
#define UART5_GAR_REG_UART5_RST_N_ASSERT   0b0
 
#define UART5_GAR_REG_UART5_RST_N_DE_ASSERT   0b1
 
#define UART5_GAR_REG_UART5_APB_CLK_EN_OFFSET   0
 
#define UART5_GAR_REG_UART5_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART5_GAR_REG_UART5_APB_CLK_EN_MASK   0x0
 
#define UART5_GAR_REG_UART5_APB_CLK_EN_PASS   0b1
 
#define UART6_GAR_REG   0x00000e18
 
#define UART6_GAR_REG_UART6_RST_N_OFFSET   16
 
#define UART6_GAR_REG_UART6_RST_N_CLEAR_MASK   0x00010000
 
#define UART6_GAR_REG_UART6_RST_N_ASSERT   0b0
 
#define UART6_GAR_REG_UART6_RST_N_DE_ASSERT   0b1
 
#define UART6_GAR_REG_UART6_APB_CLK_EN_OFFSET   0
 
#define UART6_GAR_REG_UART6_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART6_GAR_REG_UART6_APB_CLK_EN_MASK   0x0
 
#define UART6_GAR_REG_UART6_APB_CLK_EN_PASS   0b1
 
#define UART7_GAR_REG   0x00000e1c
 
#define UART7_GAR_REG_UART7_RST_N_OFFSET   16
 
#define UART7_GAR_REG_UART7_RST_N_CLEAR_MASK   0x00010000
 
#define UART7_GAR_REG_UART7_RST_N_ASSERT   0b0
 
#define UART7_GAR_REG_UART7_RST_N_DE_ASSERT   0b1
 
#define UART7_GAR_REG_UART7_APB_CLK_EN_OFFSET   0
 
#define UART7_GAR_REG_UART7_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define UART7_GAR_REG_UART7_APB_CLK_EN_MASK   0x0
 
#define UART7_GAR_REG_UART7_APB_CLK_EN_PASS   0b1
 
#define TWI0_GAR_REG   0x00000e80
 
#define TWI0_GAR_REG_TWI0_RST_N_OFFSET   16
 
#define TWI0_GAR_REG_TWI0_RST_N_CLEAR_MASK   0x00010000
 
#define TWI0_GAR_REG_TWI0_RST_N_ASSERT   0b0
 
#define TWI0_GAR_REG_TWI0_RST_N_DE_ASSERT   0b1
 
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_OFFSET   0
 
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_MASK   0x0
 
#define TWI0_GAR_REG_TWI0_APB_CLK_EN_PASS   0b1
 
#define TWI1_GAR_REG   0x00000e84
 
#define TWI1_GAR_REG_TWI1_RST_N_OFFSET   16
 
#define TWI1_GAR_REG_TWI1_RST_N_CLEAR_MASK   0x00010000
 
#define TWI1_GAR_REG_TWI1_RST_N_ASSERT   0b0
 
#define TWI1_GAR_REG_TWI1_RST_N_DE_ASSERT   0b1
 
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_OFFSET   0
 
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_MASK   0x0
 
#define TWI1_GAR_REG_TWI1_APB_CLK_EN_PASS   0b1
 
#define TWI2_GAR_REG   0x00000e88
 
#define TWI2_GAR_REG_TWI2_RST_N_OFFSET   16
 
#define TWI2_GAR_REG_TWI2_RST_N_CLEAR_MASK   0x00010000
 
#define TWI2_GAR_REG_TWI2_RST_N_ASSERT   0b0
 
#define TWI2_GAR_REG_TWI2_RST_N_DE_ASSERT   0b1
 
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_OFFSET   0
 
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_MASK   0x0
 
#define TWI2_GAR_REG_TWI2_APB_CLK_EN_PASS   0b1
 
#define TWI3_GAR_REG   0x00000e8c
 
#define TWI3_GAR_REG_TWI3_RST_N_OFFSET   16
 
#define TWI3_GAR_REG_TWI3_RST_N_CLEAR_MASK   0x00010000
 
#define TWI3_GAR_REG_TWI3_RST_N_ASSERT   0b0
 
#define TWI3_GAR_REG_TWI3_RST_N_DE_ASSERT   0b1
 
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_OFFSET   0
 
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_MASK   0x0
 
#define TWI3_GAR_REG_TWI3_APB_CLK_EN_PASS   0b1
 
#define TWI4_GAR_REG   0x00000e90
 
#define TWI4_GAR_REG_TWI4_RST_N_OFFSET   16
 
#define TWI4_GAR_REG_TWI4_RST_N_CLEAR_MASK   0x00010000
 
#define TWI4_GAR_REG_TWI4_RST_N_ASSERT   0b0
 
#define TWI4_GAR_REG_TWI4_RST_N_DE_ASSERT   0b1
 
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_OFFSET   0
 
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_MASK   0x0
 
#define TWI4_GAR_REG_TWI4_APB_CLK_EN_PASS   0b1
 
#define TWI5_GAR_REG   0x00000e94
 
#define TWI5_GAR_REG_TWI5_RST_N_OFFSET   16
 
#define TWI5_GAR_REG_TWI5_RST_N_CLEAR_MASK   0x00010000
 
#define TWI5_GAR_REG_TWI5_RST_N_ASSERT   0b0
 
#define TWI5_GAR_REG_TWI5_RST_N_DE_ASSERT   0b1
 
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_OFFSET   0
 
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_MASK   0x0
 
#define TWI5_GAR_REG_TWI5_APB_CLK_EN_PASS   0b1
 
#define SPI0_CLK_REG   0x00000f00
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110
 
#define SPI0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SPI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI0_GAR_REG   0x00000f04
 
#define SPI0_GAR_REG_SPI0_RST_N_OFFSET   16
 
#define SPI0_GAR_REG_SPI0_RST_N_CLEAR_MASK   0x00010000
 
#define SPI0_GAR_REG_SPI0_RST_N_ASSERT   0b0
 
#define SPI0_GAR_REG_SPI0_RST_N_DE_ASSERT   0b1
 
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_OFFSET   0
 
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_MASK   0x0
 
#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_PASS   0b1
 
#define SPI1_CLK_REG   0x00000f08
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110
 
#define SPI1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SPI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI1_GAR_REG   0x00000f0c
 
#define SPI1_GAR_REG_SPI1_RST_N_OFFSET   16
 
#define SPI1_GAR_REG_SPI1_RST_N_CLEAR_MASK   0x00010000
 
#define SPI1_GAR_REG_SPI1_RST_N_ASSERT   0b0
 
#define SPI1_GAR_REG_SPI1_RST_N_DE_ASSERT   0b1
 
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_OFFSET   0
 
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_MASK   0x0
 
#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_PASS   0b1
 
#define SPI2_CLK_REG   0x00000f10
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110
 
#define SPI2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SPI2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI2_GAR_REG   0x00000f14
 
#define SPI2_GAR_REG_SPI2_RST_N_OFFSET   16
 
#define SPI2_GAR_REG_SPI2_RST_N_CLEAR_MASK   0x00010000
 
#define SPI2_GAR_REG_SPI2_RST_N_ASSERT   0b0
 
#define SPI2_GAR_REG_SPI2_RST_N_DE_ASSERT   0b1
 
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_OFFSET   0
 
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_MASK   0x0
 
#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_PASS   0b1
 
#define GPADC0_CLK_REG   0x00000fc0
 
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET   31
 
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define GPADC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M   0b001
 
#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010
 
#define GPADC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define GPADC0_GAR_REG   0x00000fc4
 
#define GPADC0_GAR_REG_GPADC0_RST_N_OFFSET   16
 
#define GPADC0_GAR_REG_GPADC0_RST_N_CLEAR_MASK   0x00010000
 
#define GPADC0_GAR_REG_GPADC0_RST_N_ASSERT   0b0
 
#define GPADC0_GAR_REG_GPADC0_RST_N_DE_ASSERT   0b1
 
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_OFFSET   0
 
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_MASK   0x0
 
#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_PASS   0b1
 
#define TSENSOR_GAR_REG   0x00000fe4
 
#define TSENSOR_GAR_REG_TSENSOR_RST_N_OFFSET   16
 
#define TSENSOR_GAR_REG_TSENSOR_RST_N_CLEAR_MASK   0x00010000
 
#define TSENSOR_GAR_REG_TSENSOR_RST_N_ASSERT   0b0
 
#define TSENSOR_GAR_REG_TSENSOR_RST_N_DE_ASSERT   0b1
 
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_OFFSET   0
 
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_MASK   0x0
 
#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_PASS   0b1
 
#define IR_RX0_CLK_REG   0x00001000
 
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_OFFSET   31
 
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define IR_RX0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IR_RX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b000
 
#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b001
 
#define IR_RX0_CLK_REG_FACTOR_M_OFFSET   0
 
#define IR_RX0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define IR_RX0_GAR_REG   0x00001004
 
#define IR_RX0_GAR_REG_IR_RX0_RST_N_OFFSET   16
 
#define IR_RX0_GAR_REG_IR_RX0_RST_N_CLEAR_MASK   0x00010000
 
#define IR_RX0_GAR_REG_IR_RX0_RST_N_ASSERT   0b0
 
#define IR_RX0_GAR_REG_IR_RX0_RST_N_DE_ASSERT   0b1
 
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_OFFSET   0
 
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_MASK   0x0
 
#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_PASS   0b1
 
#define IR_TX_CLK_REG   0x00001008
 
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_OFFSET   31
 
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define IR_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IR_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define IR_TX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0
 
#define IR_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b1
 
#define IR_TX_CLK_REG_FACTOR_M_OFFSET   0
 
#define IR_TX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define IR_TX_GAR_REG   0x0000100c
 
#define IR_TX_GAR_REG_IR_TX_RST_N_OFFSET   16
 
#define IR_TX_GAR_REG_IR_TX_RST_N_CLEAR_MASK   0x00010000
 
#define IR_TX_GAR_REG_IR_TX_RST_N_ASSERT   0b0
 
#define IR_TX_GAR_REG_IR_TX_RST_N_DE_ASSERT   0b1
 
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_OFFSET   0
 
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_MASK   0x0
 
#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_PASS   0b1
 
#define I2S0_CLK_REG   0x00001200
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET   31
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define I2S0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2S0_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define I2S0_GAR_REG   0x0000120c
 
#define I2S0_GAR_REG_I2S0_RST_N_OFFSET   16
 
#define I2S0_GAR_REG_I2S0_RST_N_CLEAR_MASK   0x00010000
 
#define I2S0_GAR_REG_I2S0_RST_N_ASSERT   0b0
 
#define I2S0_GAR_REG_I2S0_RST_N_DE_ASSERT   0b1
 
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_OFFSET   0
 
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_MASK   0x0
 
#define I2S0_GAR_REG_I2S0_APB_CLK_EN_PASS   0b1
 
#define I2S1_CLK_REG   0x00001210
 
#define I2S1_CLK_REG_I2S1_CLK_GATING_OFFSET   31
 
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2S1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2S1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define I2S1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2S1_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2S1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define I2S1_GAR_REG   0x0000121c
 
#define I2S1_GAR_REG_I2S1_RST_N_OFFSET   16
 
#define I2S1_GAR_REG_I2S1_RST_N_CLEAR_MASK   0x00010000
 
#define I2S1_GAR_REG_I2S1_RST_N_ASSERT   0b0
 
#define I2S1_GAR_REG_I2S1_RST_N_DE_ASSERT   0b1
 
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_OFFSET   0
 
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_MASK   0x0
 
#define I2S1_GAR_REG_I2S1_APB_CLK_EN_PASS   0b1
 
#define I2S2_CLK_REG   0x00001220
 
#define I2S2_CLK_REG_I2S2_CLK_GATING_OFFSET   31
 
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2S2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2S2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define I2S2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2S2_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2S2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define I2S2_GAR_REG   0x0000122c
 
#define I2S2_GAR_REG_I2S2_RST_N_OFFSET   16
 
#define I2S2_GAR_REG_I2S2_RST_N_CLEAR_MASK   0x00010000
 
#define I2S2_GAR_REG_I2S2_RST_N_ASSERT   0b0
 
#define I2S2_GAR_REG_I2S2_RST_N_DE_ASSERT   0b1
 
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_OFFSET   0
 
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_MASK   0x0
 
#define I2S2_GAR_REG_I2S2_APB_CLK_EN_PASS   0b1
 
#define I2S3_CLK_REG   0x00001230
 
#define I2S3_CLK_REG_I2S3_CLK_GATING_OFFSET   31
 
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLEAR_MASK   0x80000000
 
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2S3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2S3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define I2S3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2S3_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2S3_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define I2S3_GAR_REG   0x0000123c
 
#define I2S3_GAR_REG_I2S3_RST_N_OFFSET   16
 
#define I2S3_GAR_REG_I2S3_RST_N_CLEAR_MASK   0x00010000
 
#define I2S3_GAR_REG_I2S3_RST_N_ASSERT   0b0
 
#define I2S3_GAR_REG_I2S3_RST_N_DE_ASSERT   0b1
 
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_OFFSET   0
 
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_MASK   0x0
 
#define I2S3_GAR_REG_I2S3_APB_CLK_EN_PASS   0b1
 
#define OWA0_TX_CLK_REG   0x00001280
 
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_OFFSET   31
 
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define OWA0_TX_CLK_REG_FACTOR_M_OFFSET   0
 
#define OWA0_TX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define OWA0_RX_CLK_REG   0x00001284
 
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_OFFSET   31
 
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b000
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b010
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b011
 
#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b100
 
#define OWA0_RX_CLK_REG_FACTOR_M_OFFSET   0
 
#define OWA0_RX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define OWA0_GAR_REG   0x0000128c
 
#define OWA0_GAR_REG_OWA0_RST_N_OFFSET   16
 
#define OWA0_GAR_REG_OWA0_RST_N_CLEAR_MASK   0x00010000
 
#define OWA0_GAR_REG_OWA0_RST_N_ASSERT   0b0
 
#define OWA0_GAR_REG_OWA0_RST_N_DE_ASSERT   0b1
 
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_OFFSET   0
 
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_MASK   0b0
 
#define OWA0_GAR_REG_OWA0_APB_CLK_EN_PASS   0b1
 
#define DMIC_CLK_REG   0x000012c0
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET   31
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define DMIC_CLK_REG_FACTOR_M_OFFSET   0
 
#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DMIC_GAR_REG   0x000012cc
 
#define DMIC_GAR_REG_DMIC_RST_N_OFFSET   16
 
#define DMIC_GAR_REG_DMIC_RST_N_CLEAR_MASK   0x00010000
 
#define DMIC_GAR_REG_DMIC_RST_N_ASSERT   0b0
 
#define DMIC_GAR_REG_DMIC_RST_N_DE_ASSERT   0b1
 
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_OFFSET   0
 
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_MASK   0b0
 
#define DMIC_GAR_REG_DMIC_APB_CLK_EN_PASS   0b1
 
#define AUDIOCODEC0_DAC_CLK_REG   0x000012e0
 
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_OFFSET   31
 
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_OFFSET   0
 
#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define AUDIOCODEC0_ADC_CLK_REG   0x000012e8
 
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_OFFSET   31
 
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_OFFSET   0
 
#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define AUDIOCODEC0_GAR_REG   0x000012ec
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_OFFSET   16
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_CLEAR_MASK   0x00010000
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_ASSERT   0b0
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_DE_ASSERT   0b1
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_OFFSET   0
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_MASK   0b0
 
#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_PASS   0b1
 
#define AUDIOCODEC1_DAC_CLK_REG   0x000012f0
 
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_OFFSET   31
 
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000
 
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001
 
#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010
 
#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_OFFSET   0
 
#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define AUDIOCODEC1_GAR_REG   0x000012fc
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_OFFSET   16
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_CLEAR_MASK   0x00010000
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_ASSERT   0b0
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_DE_ASSERT   0b1
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_OFFSET   0
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_MASK   0b0
 
#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_PASS   0b1
 
#define USB0_CLK_REG   0x00001300
 
#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31
 
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK   0b01
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_SYS_32K_CLK   0b10
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_RC_16M_CLK   0b11
 
#define USB0_GAR_REG   0x00001304
 
#define USB0_GAR_REG_USB0_DEV_RST_N_OFFSET   24
 
#define USB0_GAR_REG_USB0_DEV_RST_N_CLEAR_MASK   0x01000000
 
#define USB0_GAR_REG_USB0_DEV_RST_N_ASSERT   0b0
 
#define USB0_GAR_REG_USB0_DEV_RST_N_DE_ASSERT   0b1
 
#define USB0_GAR_REG_USB0_EHCI_RST_N_OFFSET   20
 
#define USB0_GAR_REG_USB0_EHCI_RST_N_CLEAR_MASK   0x00100000
 
#define USB0_GAR_REG_USB0_EHCI_RST_N_ASSERT   0b0
 
#define USB0_GAR_REG_USB0_EHCI_RST_N_DE_ASSERT   0b1
 
#define USB0_GAR_REG_USB0_OHCI_RST_N_OFFSET   16
 
#define USB0_GAR_REG_USB0_OHCI_RST_N_CLEAR_MASK   0x00010000
 
#define USB0_GAR_REG_USB0_OHCI_RST_N_ASSERT   0b0
 
#define USB0_GAR_REG_USB0_OHCI_RST_N_DE_ASSERT   0b1
 
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_OFFSET   8
 
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_CLEAR_MASK   0x00000100
 
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_MASK   0b0
 
#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_PASS   0b1
 
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_OFFSET   4
 
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_CLEAR_MASK   0x00000010
 
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_MASK   0b0
 
#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_PASS   0b1
 
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_OFFSET   0
 
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_MASK   0b0
 
#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_PASS   0b1
 
#define USB1_CLK_REG   0x00001308
 
#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31
 
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   0x80000000
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0b0
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0b1
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   0x03000000
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK   0b01
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_SYS_32K_CLK   0b10
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_RC_16M_CLK   0b11
 
#define USB1_GAR_REG   0x0000130c
 
#define USB1_GAR_REG_USB1_EHCI_RST_N_OFFSET   20
 
#define USB1_GAR_REG_USB1_EHCI_RST_N_CLEAR_MASK   0x00100000
 
#define USB1_GAR_REG_USB1_EHCI_RST_N_ASSERT   0b0
 
#define USB1_GAR_REG_USB1_EHCI_RST_N_DE_ASSERT   0b1
 
#define USB1_GAR_REG_USB1_OHCI_RST_N_OFFSET   16
 
#define USB1_GAR_REG_USB1_OHCI_RST_N_CLEAR_MASK   0x00010000
 
#define USB1_GAR_REG_USB1_OHCI_RST_N_ASSERT   0b0
 
#define USB1_GAR_REG_USB1_OHCI_RST_N_DE_ASSERT   0b1
 
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_OFFSET   4
 
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_CLEAR_MASK   0x00000010
 
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_MASK   0b0
 
#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_PASS   0b1
 
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_OFFSET   0
 
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_MASK   0b0
 
#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_PASS   0b1
 
#define USB2P0_SYS_PHY_REF_CLK_REG   0x00001340
 
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_OFFSET   31
 
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2P0_SYS_GAR_REG   0x00001344
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_OFFSET   16
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_CLEAR_MASK   0x00010000
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_ASSERT   0b0
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_DE_ASSERT   0b1
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_OFFSET   0
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_MASK   0b0
 
#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_PASS   0b1
 
#define USB2_U2_PHY_REF_CLK_REG   0x00001348
 
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_OFFSET   31
 
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_SUSPEND_CLK_REG   0x00001350
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b0
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b1
 
#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define USB2_MF_CLK_REG   0x00001354
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET   31
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b01
 
#define USB2_MF_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define USB2_GAR_REG   0x0000135c
 
#define USB2_GAR_REG_USB2_RST_N_OFFSET   16
 
#define USB2_GAR_REG_USB2_RST_N_CLEAR_MASK   0x00010000
 
#define USB2_GAR_REG_USB2_RST_N_ASSERT   0b0
 
#define USB2_GAR_REG_USB2_RST_N_DE_ASSERT   0b1
 
#define USB2_U3_ONLY_UTMI_CLK_REG   0x00001360
 
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_OFFSET   31
 
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define USB2_U2_ONLY_PIPE_CLK_REG   0x00001364
 
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_OFFSET   31
 
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define PCIe0_AUX_CLK_REG   0x00001380
 
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET   31
 
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0
 
#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b1
 
#define PCIe0_AUX_CLK_REG_FACTOR_M_OFFSET   0
 
#define PCIe0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define PCIe0_AXI_S_CLK_REG   0x00001384
 
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_OFFSET   31
 
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b0
 
#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b1
 
#define PCIe0_AXI_S_CLK_REG_FACTOR_M_OFFSET   0
 
#define PCIe0_AXI_S_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define PCIe0_GAR_REG   0x0000138c
 
#define PCIe0_GAR_REG_PCIE0_RST_N_OFFSET   17
 
#define PCIe0_GAR_REG_PCIE0_RST_N_CLEAR_MASK   0x00020000
 
#define PCIe0_GAR_REG_PCIE0_RST_N_ASSERT   0b0
 
#define PCIe0_GAR_REG_PCIE0_RST_N_DE_ASSERT   0b1
 
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_OFFSET   16
 
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_CLEAR_MASK   0x00010000
 
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_ASSERT   0b0
 
#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_DE_ASSERT   0b1
 
#define HSI_COMB0_PHY_CFG_CLK_REG   0x000013c0
 
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_OFFSET   31
 
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLEAR_MASK   0x80000000
 
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b0
 
#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b1
 
#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_OFFSET   0
 
#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define HSI_COMB0_PHY_REF_CLK_REG   0x000013c4
 
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_OFFSET   31
 
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_OFFSET   0
 
#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define HSI_SYS_GAR_REG   0x000013cc
 
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_OFFSET   16
 
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_CLEAR_MASK   0x00010000
 
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_ASSERT   0b0
 
#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_DE_ASSERT   0b1
 
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_OFFSET   1
 
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_CLEAR_MASK   0x00000002
 
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_MASK   0b0
 
#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_PASS   0b1
 
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_OFFSET   0
 
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_MASK   0b0
 
#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_PASS   0b1
 
#define HSI_AXI_CLK_REG   0x000013e0
 
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_OFFSET   31
 
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b01
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b10
 
#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b11
 
#define HSI_AXI_CLK_REG_FACTOR_M_OFFSET   0
 
#define HSI_AXI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define GMAC0_PHY_CLK_REG   0x00001400
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET   31
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET   0
 
#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define GMAC0_GAR_REG   0x0000140c
 
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_OFFSET   17
 
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_CLEAR_MASK   0x00020000
 
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_ASSERT   0b0
 
#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_DE_ASSERT   0b1
 
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_OFFSET   16
 
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_CLEAR_MASK   0x00010000
 
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_ASSERT   0b0
 
#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_DE_ASSERT   0b1
 
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_OFFSET   0
 
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_MASK   0b0
 
#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_PASS   0b1
 
#define TCON_LCD0_CLK_REG   0x00001500
 
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_OFFSET   31
 
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101
 
#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define TCON_LCD0_CLK_REG_FACTOR_M_OFFSET   0
 
#define TCON_LCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define TCON_LCD0_GAR_REG   0x00001504
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_OFFSET   16
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_CLEAR_MASK   0x00010000
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_ASSERT   0b0
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_DE_ASSERT   0b1
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_OFFSET   0
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_MASK   0b0
 
#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_PASS   0b1
 
#define LVDS0_GAR_REG   0x00001544
 
#define LVDS0_GAR_REG_LVDS0_RST_N_OFFSET   16
 
#define LVDS0_GAR_REG_LVDS0_RST_N_CLEAR_MASK   0x00010000
 
#define LVDS0_GAR_REG_LVDS0_RST_N_ASSERT   0b0
 
#define LVDS0_GAR_REG_LVDS0_RST_N_DE_ASSERT   0b1
 
#define MIPI_DSI00_CLK_REG   0x00001580
 
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_OFFSET   31
 
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010
 
#define MIPI_DSI00_CLK_REG_FACTOR_M_OFFSET   0
 
#define MIPI_DSI00_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define MIPI_DSI00_GAR_REG   0x00001584
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_OFFSET   16
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_CLEAR_MASK   0x00010000
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_ASSERT   0b0
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_DE_ASSERT   0b1
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_OFFSET   0
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_MASK   0b0
 
#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_PASS   0b1
 
#define COMBOPHY0_CLK_REG   0x000015c0
 
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_OFFSET   31
 
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101
 
#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define COMBOPHY0_CLK_REG_FACTOR_M_OFFSET   0
 
#define COMBOPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define TCON_TV0_eDP_CLK_REG   0x00001600
 
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_OFFSET   31
 
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101
 
#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define TCON_TV0_eDP_CLK_REG_FACTOR_M_OFFSET   0
 
#define TCON_TV0_eDP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define TCON_TV0_GAR_REG   0x00001604
 
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_OFFSET   16
 
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_CLEAR_MASK   0x00010000
 
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_ASSERT   0b0
 
#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_DE_ASSERT   0b1
 
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_OFFSET   0
 
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_MASK   0b0
 
#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_PASS   0b1
 
#define eDP_GAR_REG   0x0000164c
 
#define eDP_GAR_REG_EDP_RST_N_OFFSET   16
 
#define eDP_GAR_REG_EDP_RST_N_CLEAR_MASK   0x00010000
 
#define eDP_GAR_REG_EDP_RST_N_ASSERT   0b0
 
#define eDP_GAR_REG_EDP_RST_N_DE_ASSERT   0b1
 
#define eDP_GAR_REG_EDP_AHB_CLK_EN_OFFSET   0
 
#define eDP_GAR_REG_EDP_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define eDP_GAR_REG_EDP_AHB_CLK_EN_MASK   0b0
 
#define eDP_GAR_REG_EDP_AHB_CLK_EN_PASS   0b1
 
#define VO0_REG_GAR_REG   0x000016c4
 
#define VO0_REG_GAR_REG_VO0_REG_RST_N_OFFSET   16
 
#define VO0_REG_GAR_REG_VO0_REG_RST_N_CLEAR_MASK   0x00010000
 
#define VO0_REG_GAR_REG_VO0_REG_RST_N_ASSERT   0b0
 
#define VO0_REG_GAR_REG_VO0_REG_RST_N_DE_ASSERT   0b1
 
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_OFFSET   0
 
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_MASK   0b0
 
#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_PASS   0b1
 
#define VO1_REG_GAR_REG   0x000016cc
 
#define VO1_REG_GAR_REG_VO1_REG_RST_N_OFFSET   16
 
#define VO1_REG_GAR_REG_VO1_REG_RST_N_CLEAR_MASK   0x00010000
 
#define VO1_REG_GAR_REG_VO1_REG_RST_N_ASSERT   0b0
 
#define VO1_REG_GAR_REG_VO1_REG_RST_N_DE_ASSERT   0b1
 
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_OFFSET   0
 
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_MASK   0b0
 
#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_PASS   0b1
 
#define VIDEO_OUT0_GAR_REG   0x000016e4
 
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_OFFSET   16
 
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_CLEAR_MASK   0x00010000
 
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_ASSERT   0b0
 
#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_DE_ASSERT   0b1
 
#define LEDC_CLK_REG   0x00001700
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0
 
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b1
 
#define LEDC_CLK_REG_FACTOR_M_OFFSET   0
 
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define LEDC_GAR_REG   0x00001704
 
#define LEDC_GAR_REG_LEDC_RST_N_OFFSET   16
 
#define LEDC_GAR_REG_LEDC_RST_N_CLEAR_MASK   0x00010000
 
#define LEDC_GAR_REG_LEDC_RST_N_ASSERT   0b0
 
#define LEDC_GAR_REG_LEDC_RST_N_DE_ASSERT   0b1
 
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_OFFSET   0
 
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_CLEAR_MASK   0x00000001
 
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_MASK   0b0
 
#define LEDC_GAR_REG_LEDC_APB_CLK_EN_PASS   0b1
 
#define CSI_MASTER0_CLK_REG   0x00001800
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER1_CLK_REG   0x00001804
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER2_CLK_REG   0x00001808
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_CLK_REG   0x00001840
 
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b001
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110
 
#define CSI_CLK_REG_CLK_SRC_SEL_VEPLL   0b111
 
#define CSI_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define ISP_CLK_REG   0x00001860
 
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   0x80000000
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0b1
 
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b001
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110
 
#define ISP_CLK_REG_CLK_SRC_SEL_VEPLL   0b111
 
#define ISP_CLK_REG_FACTOR_M_OFFSET   0
 
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VIDEO_IN_GAR_REG   0x00001884
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_OFFSET   16
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_CLEAR_MASK   0x00010000
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_ASSERT   0b0
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_DE_ASSERT   0b1
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_OFFSET   0
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_CLEAR_MASK   0x00000001
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_MASK   0b0
 
#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_PASS   0b1
 
#define PERI0PLL_GATE_EN_REG   0x00001908
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_OFFSET   31
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_CLEAR_MASK   0x80000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG   0x0000190c
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_OFFSET   31
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_CLEAR_MASK   0x80000000
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_OFFSET   28
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_CLEAR_MASK   0x10000000
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET   27
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK   0x08000000
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET   26
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK   0x04000000
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET   25
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET   23
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET   22
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET   20
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET   19
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET   17
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET   16
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_OFFSET   12
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00001000
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET   11
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000800
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET   10
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000400
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG   0x00001910
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET   22
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET   21
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00200000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET   20
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET   18
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET   17
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET   16
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET   6
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000040
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET   5
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000020
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET   4
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET   2
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET   1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET   0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define GPUPLL_GATE_EN_REG   0x00001914
 
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_OFFSET   16
 
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_DISABLE   0b0
 
#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_ENABLE   0b1
 
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_OFFSET   0
 
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_AUTO   0b0
 
#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VEPLL_GATE_EN_REG   0x00001918
 
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_OFFSET   16
 
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_DISABLE   0b0
 
#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_ENABLE   0b1
 
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_OFFSET   0
 
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_AUTO   0b0
 
#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG   0x0000191c
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_OFFSET   18
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_OFFSET   17
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_OFFSET   16
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_OFFSET   2
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_OFFSET   1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_OFFSET   0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_STAT_REG   0x00001988
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET   27
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK   0x08000000
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET   26
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK   0x04000000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET   25
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK   0x02000000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET   24
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET   23
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK   0x00800000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET   22
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK   0x00400000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET   21
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET   20
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK   0x00100000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET   19
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK   0x00080000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET   18
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET   17
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK   0x00020000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET   16
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK   0x00010000
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG   0x0000198c
 
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_OFFSET   28
 
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_CLEAR_MASK   0x10000000
 
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET   27
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK   0x08000000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET   26
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK   0x04000000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET   25
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK   0x02000000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET   24
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET   23
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK   0x00800000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET   22
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK   0x00400000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET   21
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET   20
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK   0x00100000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET   19
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK   0x00080000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET   18
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET   17
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK   0x00020000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET   16
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK   0x00010000
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG   0x00001990
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET   22
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK   0x00400000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET   21
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK   0x00200000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET   20
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK   0x00100000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET   18
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK   0x00040000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET   17
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK   0x00020000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET   16
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK   0x00010000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE   0b1
 
#define GPUPLL_GATE_STAT_REG   0x00001994
 
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_OFFSET   16
 
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_CLEAR_MASK   0x00010000
 
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_DISABLE   0b0
 
#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_ENABLE   0b1
 
#define VEPLL_GATE_STAT_REG   0x00001998
 
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_OFFSET   16
 
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_CLEAR_MASK   0x00010000
 
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_DISABLE   0b0
 
#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG   0x0000199c
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_OFFSET   18
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_CLEAR_MASK   0x00040000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_OFFSET   17
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_CLEAR_MASK   0x00020000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_OFFSET   16
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_CLEAR_MASK   0x00010000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_ENABLE   0b1
 
#define RES24M_GATE_EN_REG   0x00001a00
 
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_OFFSET   0
 
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_CLEAR_MASK   0x00000001
 
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_DISABLE   0b0
 
#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_ENABLE   0b1
 
#define PLL_FO0_EN_REG   0x00001a10
 
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_OFFSET   0
 
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_CLEAR_MASK   0x00000001
 
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_DISABLE   0b0
 
#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_ENABLE   0b1
 
#define PLL_OPG_BYPASS_REG   0x00001a20
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET   0
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK   0x00000001
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE   0b0
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE   0b1
 
#define CM_VIDEO_IN_CFG_REG   0x00001b00
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_OFFSET   16
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_CLEAR_MASK   0x00030000
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_OFF   0b01
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_ON   0b10
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_OFFSET   0
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_CLEAR_MASK   0x00000001
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_DISABLE   0b0
 
#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_ENABLE   0b1
 
#define CM_VE_CFG_REG   0x00001b10
 
#define CM_VE_CFG_REG_CM_VE_STATUS_OFFSET   16
 
#define CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK   0x00030000
 
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF   0b01
 
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON   0b10
 
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET   0
 
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK   0x00000001
 
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE   0b0
 
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE   0b1
 
#define CM_HSI_CFG_REG   0x00001b28
 
#define CM_HSI_CFG_REG_CM_HSI_STATUS_OFFSET   16
 
#define CM_HSI_CFG_REG_CM_HSI_STATUS_CLEAR_MASK   0x00030000
 
#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_OFF   0b01
 
#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_ON   0b10
 
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_OFFSET   0
 
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_CLEAR_MASK   0x00000001
 
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_DISABLE   0b0
 
#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_ENABLE   0b1
 
#define CM_VIDEO_OUT0_CFG_REG   0x00001b34
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_OFFSET   16
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_CLEAR_MASK   0x00030000
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_OFF   0b01
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_ON   0b10
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_OFFSET   0
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_CLEAR_MASK   0x00000001
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_DISABLE   0b0
 
#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_ENABLE   0b1
 
#define AXI_MON_GAR_REG   0x00001c00
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_OFFSET   19
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_CLEAR_MASK   0x00080000
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_ASSERT   0b0
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_DE_ASSERT   0b1
 
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_OFFSET   18
 
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_CLEAR_MASK   0x00040000
 
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_ASSERT   0b0
 
#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_DE_ASSERT   0b1
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_OFFSET   17
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_CLEAR_MASK   0x00020000
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_ASSERT   0b0
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_DE_ASSERT   0b1
 
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_OFFSET   16
 
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_CLEAR_MASK   0x00010000
 
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_ASSERT   0b0
 
#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_DE_ASSERT   0b1
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_OFFSET   3
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_CLEAR_MASK   0x00000008
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_MASK   0b0
 
#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_PASS   0b1
 
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_OFFSET   2
 
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_CLEAR_MASK   0x00000004
 
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_MASK   0b0
 
#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_PASS   0b1
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_OFFSET   1
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_CLEAR_MASK   0x00000002
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_MASK   0b0
 
#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_PASS   0b1
 
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_OFFSET   0
 
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_CLEAR_MASK   0x00000001
 
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_MASK   0b0
 
#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_PASS   0b1
 
#define AHB_MON_GAR_REG   0x00001c04
 
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_OFFSET   17
 
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_CLEAR_MASK   0x00020000
 
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_ASSERT   0b0
 
#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_DE_ASSERT   0b1
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_OFFSET   16
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_CLEAR_MASK   0x00010000
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_ASSERT   0b0
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_DE_ASSERT   0b1
 
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_OFFSET   1
 
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_CLEAR_MASK   0x00000002
 
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_MASK   0b0
 
#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_PASS   0b1
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_OFFSET   0
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_CLEAR_MASK   0x00000001
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_MASK   0b0
 
#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_PASS   0b1
 
#define CCU_SEC_SWITCH_REG   0x00001f00
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1
 
#define DAP_REQ_CTRL_REG   0x00001f10
 
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_OFFSET   0
 
#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_CLEAR_MASK   0x00000001
 
#define PLL_CFG0_REG   0x00001f20
 
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0
 
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   0xffffffff
 
#define PLL_CFG1_REG   0x00001f24
 
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0
 
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   0xffffffff
 
#define PLL_CFG2_REG   0x00001f28
 
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0
 
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   0xffffffff
 
#define PLL_LOCK_DBG_CTRL_REG   0x00001f2c
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   0x80000000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0b0
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0b1
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   0x03f00000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL0   0b0000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL1   0b0001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL2   0b0010
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL   0b0011
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL   0b0100
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL   0b0101
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL   0b0110
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL   0b0111
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL   0b1000
 
#define CCU_FAN_GATE_REG   0x00001f30
 
#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET   4
 
#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK   0x00000010
 
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG   0x00001f34
 
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31
 
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X   0b000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X   0b001
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X   0b010
 
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8
 
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00001f00
 
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0
 
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f
 
#define CLK_FAN_REG   0x00001f38
 
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1
 
#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5
 
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0
 
#define CLK_FAN_REG_PCLK_DIV_OFFSET   0
 
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f
 
#define CCU_FAN_REG   0x00001f3c
 
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_OFFSET   31
 
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_CLEAR_MASK   0x80000000
 
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_PERI0_160M_10   0b0
 
#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_RC_16M   0b1
 
#define CCU_FAN_REG_FANOUT_CLK2_EN_OFFSET   23
 
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLEAR_MASK   0x00800000
 
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_FANOUT_CLK1_EN_OFFSET   22
 
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLEAR_MASK   0x00400000
 
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_FANOUT_CLK0_EN_OFFSET   21
 
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLEAR_MASK   0x00200000
 
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_OFFSET   6
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLEAR_MASK   0x000001c0
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_FANOUT_32K_CLK_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_PCLK   0b110
 
#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK50M_FROM_PERI0_150M_3   0b111
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_OFFSET   3
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLEAR_MASK   0x00000038
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_PCLK   0b110
 
#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK50M_FROM_PERI0_150M_3   0b111
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_OFFSET   0
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLEAR_MASK   0x00000007
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_PCLK   0b110
 
#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK50M_FROM_PERI0_150M_3   0b111
 
#define CLK_DBG_REG   0x00001f50
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_OFFSET   24
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_CLEAR_MASK   0x03000000
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV1   0b00
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV2   0b01
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV4   0b10
 
#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV8   0b11
 
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_OFFSET   16
 
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_CLEAR_MASK   0x00070000
 
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_STBY_SYS_BACKDOOR_CLK   0b000
 
#define CLK_DBG_REG_MDL_CLK_DBG_SEL_DISPLL0_CK_HS   0b001
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_OFFSET   4
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CLEAR_MASK   0x000001f0
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_VE0_PSENSOR_CLK   0b0000
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_GPU_PSENSOR_CLK   0b0001
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_DRAMC_PSENSOR_CLK   0b0010
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_3   0b0011
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_0   0b0100
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_1   0b0101
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_0   0b0110
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_1   0b0111
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_0   0b1000
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_1   0b1001
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_2   0b1010
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_3   0b1011
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_0   0b1100
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_1   0b1101
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_0   0b1110
 
#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_1   0b1111
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET   0
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK   0x00000007
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLK   0b000
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLK   0b001
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLK   0b010
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLK   0b011
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLK   0b100
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLK   0b101
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CE_SYS_CLK   0b110
 
#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CPU_SYS_DP_CLK   0b111
 
#define CCU_VERSION_REG   0x00001ff0
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff
 
#define APB2_CLK_SRC_OSC24M    (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_OSC32K    (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_PSI    (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_PLL6
 
#define APB2_CLK_RATE_N_1   (0x0 << 8)
 
#define APB2_CLK_RATE_N_2   (0x1 << 8)
 
#define APB2_CLK_RATE_N_4   (0x2 << 8)
 
#define APB2_CLK_RATE_N_8   (0x3 << 8)
 
#define APB2_CLK_RATE_N_MASK   (3 << 8)
 
#define APB2_CLK_RATE_M(m)   (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define SMHC0_CLK_SRC_PERI0_400M_FREQ   (400000000)
 
#define SMHC2_CLK_SRC_PERI0_800M_FREQ   (800000000)
 
#define CCM_MMC_CTRL_M(x)   ((x) -1)
 
#define CCM_MMC_CTRL_N(x)   ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
 
#define CCM_MMC_CTRL_OSCM24    (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCM_MMC_CTRL_PLL6X2
 
#define CCM_MMC_CTRL_PLL_PERIPH2X2
 
#define CCM_MMC_CTRL_ENABLE
 
#define CCM_MMC_CTRL_OCLK_DLY(a)   ((void) (a), 0)
 
#define CCM_MMC_CTRL_SCLK_DLY(a)   ((void) (a), 0)
 
#define RESET_SHIFT   (16)
 
#define GATING_SHIFT   (0)
 
#define CCU_PLL_CPUX_CTRL_REG   (SUNXI_CCU_BASE + 0x00)
 
#define CCU_PLL_DDR0_CTRL_REG   (SUNXI_CCU_BASE + 0x10)
 
#define CCU_PLL_DDR1_CTRL_REG   (SUNXI_CCU_BASE + 0x18)
 
#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + 0x20)
 
#define CCU_PLL_PERI1_CTRL_REG   (SUNXI_CCU_BASE + 0x28)
 
#define CCU_PLL_GPU_CTRL_REG   (SUNXI_CCU_BASE + 0x30)
 
#define CCU_PLL_VIDE00_CTRL_REG   (SUNXI_CCU_BASE + 0x40)
 
#define CCU_PLL_VIDE01_CTRL_REG   (SUNXI_CCU_BASE + 0x48)
 
#define CCU_PLL_VIDE02_CTRL_REG   (SUNXI_CCU_BASE + 0x50)
 
#define CCU_PLL_VIDE03_CTRL_REG   (SUNXI_CCU_BASE + 0x68)
 
#define CCU_PLL_VE_CTRL_REG   (SUNXI_CCU_BASE + 0x58)
 
#define CCU_PLL_COM_CTRL_REG   (SUNXI_CCU_BASE + 0x60)
 
#define CCU_PLL_AUDIO_CTRL_REG   (SUNXI_CCU_BASE + 0x78)
 
#define CCU_PLL_HSIC_CTRL_REG   (SUNXI_CCU_BASE + 0x70)
 
#define CCU_AHB0_CFG_REG   (SUNXI_CCU_BASE + AHB_CLK_REG)
 
#define CCU_CPUX_AXI_CFG_REG   (SUNXI_CCU_BASE + 0x500)
 
#define CCU_VE_CLK_REG   (SUNXI_CCU_BASE + 0x690)
 
#define CCU_VE_BGR_REG   (SUNXI_CCU_BASE + 0x69C)
 
#define CCU_DMA_BGR_REG   (SUNXI_CCU_BASE + 0x70C)
 
#define CCU_AVS_CLK_REG   (SUNXI_CCU_BASE + 0x750)
 
#define CCU_AVS_BGR_REG   (SUNXI_CCU_BASE + 0x74C)
 
#define CCU_IOMMU_BGR_REG   (SUNXI_CCU_BASE + 0x7bc)
 
#define CCU_MBUS_GATE_ENABLE_REG   (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)
 
#define CCU_NAND_CLK_REG   (SUNXI_CCU_BASE + 0x810)
 
#define CCU_NAND_BGR_REG   (SUNXI_CCU_BASE + 0x82C)
 
#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)
 
#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)
 
#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + SMHC2_CLK_REG)
 
#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC0_GAR_REG)
 
#define CCU_UART_BGR_REG   (SUNXI_CCU_BASE + UART0_GAR_REG)
 
#define CCU_TWI_BGR_REG   (SUNXI_CCU_BASE + 0x91C)
 
#define CCU_SCR_BGR_REG   (SUNXI_CCU_BASE + 0x93C)
 
#define CCU_SPI0_CLK_REG   (SUNXI_CCU_BASE + 0x940)
 
#define CCU_SPI1_CLK_REG   (SUNXI_CCU_BASE + 0x944)
 
#define CCU_SPI_BGR_CLK_REG   (SUNXI_CCU_BASE + 0x96C)
 
#define CCU_USB0_CLK_REG   (SUNXI_CCU_BASE + 0xA70)
 
#define CCU_USB_BGR_REG   (SUNXI_CCU_BASE + 0xA8C)
 
#define DMA_GATING_BASE   CCU_DMA_BGR_REG
 
#define DMA_GATING_PASS   (1)
 
#define DMA_GATING_BIT   (0)
 
#define CE_USE_PLATFORM_CLOCK_FUNC
 
#define SUNXI_CE_MBUS_MAT_CLK_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATE_EN_REG)
 
#define SUNXI_CE_GATING_ON   1
 
#define SUNXI_CE_MBUS_MAT_CLK_GATE_OFFSET   MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET
 
#define SUNXI_CE_MBUS_CLK_REG   (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)
 
#define SUNXI_CE_MBUS_CLK_GATE_OFFSET   MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET
 
#define SUNXI_CE_SYS_CLK_REG   (SUNXI_CCU_BASE + CE_SYS_CLK_REG)
 
#define SUNXI_CE_SYS_GATING_OFFSET   CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET
 
#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET   CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET
 
#define SUNXI_CE_SRC_600M   CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M
 
#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET   CE_SYS_CLK_REG_FACTOR_M_OFFSET
 
#define SUNXI_CE_FACTOR_0   0b0
 
#define SUNXI_CE_SYS_GATING_RESET_REG   (SUNXI_CCU_BASE + CE_SYS_GAR_REG)
 
#define SUNXI_CE_GATING_OFFSET   CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK
 
#define SUNXI_CE_SYS_GATING_RESET_OFFSET   CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET
 
#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC0_GAR_REG)
 
#define CCU_GPADC_CLK_REG   (SUNXI_CCU_BASE + GPADC0_CLK_REG)
 
#define CCU_LRADC_BGR_REG   (SUNXI_CCU_BASE + 0x0A9C)
 
#define BUS_CLK_GATING_REG   0x60
 
#define BUS_SOFTWARE_RESET_REG   0x2c0
 
#define USBPHY_CONFIG_REG   0xcc
 
#define USBEHCI0_RST_BIT   24
 
#define USBEHCI0_GATIING_BIT   24
 
#define USBPHY0_RST_BIT   0
 
#define USBPHY0_SCLK_GATING_BIT   8
 
#define USBEHCI1_RST_BIT   25
 
#define USBEHCI1_GATIING_BIT   25
 
#define USBPHY1_RST_BIT   1
 
#define USBPHY1_SCLK_GATING_BIT   9
 
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET    (SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
 
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   (SMHC0_GAR_REG_SMHC0_RST_N_OFFSET)
 

Macro Definition Documentation

◆ AHB_CLK_REG

#define AHB_CLK_REG   0x00000500

◆ AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ AHB_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define AHB_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10

◆ AHB_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define AHB_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ AHB_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define AHB_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01

◆ AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AHB_CLK_REG_FACTOR_M_OFFSET

#define AHB_CLK_REG_FACTOR_M_OFFSET   0

◆ AHB_MAT_CLK_GATE_EN_REG

#define AHB_MAT_CLK_GATE_EN_REG   0x000005c0

◆ AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000

◆ AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31

◆ AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080

◆ AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_GPU_AHB_GATE_SW_CFG_OFFSET   7

◆ AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000800

◆ AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_HSI_AHB_GATE_SW_CFG_OFFSET   11

◆ AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000

◆ AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29

◆ AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100

◆ AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_SECURE_SYS_AHB_GATE_SW_CFG_OFFSET   8

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00002000

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   13

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00004000

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   14

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00008000

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   15

◆ AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_CLEAR_MASK   0x10000000

◆ AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_STBY_SYS_PERI0PLL_CLK_GATE_SW_CFG_OFFSET   28

◆ AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002

◆ AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_VE0_AHB_GATE_SW_CFG_OFFSET   1

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_IN_AHB_GATE_SW_CFG_OFFSET   2

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATE_EN_REG_VIDEO_OUT0_AHB_GATE_SW_CFG_OFFSET   3

◆ AHB_MON_GAR_REG

#define AHB_MON_GAR_REG   0x00001c04

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_CLEAR_MASK

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_CLEAR_MASK   0x00000001

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_MASK

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_MASK   0b0

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_OFFSET

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_OFFSET   0

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_PASS

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_CLK_EN_PASS   0b1

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_ASSERT

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_ASSERT   0b0

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_CLEAR_MASK

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_CLEAR_MASK   0x00010000

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_DE_ASSERT

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_DE_ASSERT   0b1

◆ AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_OFFSET

#define AHB_MON_GAR_REG_CPU_SYS_AHBMON_RST_N_OFFSET   16

◆ AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_CLEAR_MASK

#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_CLEAR_MASK   0x00000002

◆ AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_MASK

#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_MASK   0b0

◆ AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_OFFSET

#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_OFFSET   1

◆ AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_PASS

#define AHB_MON_GAR_REG_DCU_AHBMON_CLK_EN_PASS   0b1

◆ AHB_MON_GAR_REG_DCU_AHBMON_RST_N_ASSERT

#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_ASSERT   0b0

◆ AHB_MON_GAR_REG_DCU_AHBMON_RST_N_CLEAR_MASK

#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_CLEAR_MASK   0x00020000

◆ AHB_MON_GAR_REG_DCU_AHBMON_RST_N_DE_ASSERT

#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_DE_ASSERT   0b1

◆ AHB_MON_GAR_REG_DCU_AHBMON_RST_N_OFFSET

#define AHB_MON_GAR_REG_DCU_AHBMON_RST_N_OFFSET   17

◆ APB0_CLK_REG

#define APB0_CLK_REG   0x00000510

◆ APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB0_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ APB0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define APB0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10

◆ APB0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define APB0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ APB0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define APB0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01

◆ APB0_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB0_CLK_REG_FACTOR_M_OFFSET

#define APB0_CLK_REG_FACTOR_M_OFFSET   0

◆ APB1_CLK_REG

#define APB1_CLK_REG   0x00000518

◆ APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB1_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ APB1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define APB1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b10

◆ APB1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define APB1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ APB1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define APB1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b01

◆ APB1_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB1_CLK_REG_FACTOR_M_OFFSET

#define APB1_CLK_REG_FACTOR_M_OFFSET   0

◆ APB2_CLK_RATE_M

#define APB2_CLK_RATE_M (   m)    (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_M_MASK

#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_N_1

#define APB2_CLK_RATE_N_1   (0x0 << 8)

◆ APB2_CLK_RATE_N_2

#define APB2_CLK_RATE_N_2   (0x1 << 8)

◆ APB2_CLK_RATE_N_4

#define APB2_CLK_RATE_N_4   (0x2 << 8)

◆ APB2_CLK_RATE_N_8

#define APB2_CLK_RATE_N_8   (0x3 << 8)

◆ APB2_CLK_RATE_N_MASK

#define APB2_CLK_RATE_N_MASK   (3 << 8)

◆ APB2_CLK_SRC_OSC24M

#define APB2_CLK_SRC_OSC24M    (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB2_CLK_SRC_OSC32K

#define APB2_CLK_SRC_OSC32K    (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB2_CLK_SRC_PLL6

#define APB2_CLK_SRC_PLL6
Value:
(APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS \
<< APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
APB1_CLK_REG_CLK_SRC_SEL_OFFSET
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET
Definition reg-ccu.h:754
APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS
Definition reg-ccu.h:759

◆ APB2_CLK_SRC_PSI

#define APB2_CLK_SRC_PSI    (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB_UART_CLK_REG

#define APB_UART_CLK_REG   0x00000538

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS   0b100

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b011

◆ APB_UART_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define APB_UART_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b010

◆ APB_UART_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b001

◆ APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB_UART_CLK_REG_FACTOR_M_OFFSET

#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOCODEC0_ADC_CLK_REG

#define AUDIOCODEC0_ADC_CLK_REG   0x000012e8

◆ AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLEAR_MASK

#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLEAR_MASK   0x80000000

◆ AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_OFF

#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_ON

#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_CLOCK_IS_ON   0b1

◆ AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_OFFSET

#define AUDIOCODEC0_ADC_CLK_REG_AUDIOCODEC0_ADC_CLK_GATING_OFFSET   31

◆ AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIOCODEC0_ADC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_OFFSET

#define AUDIOCODEC0_ADC_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOCODEC0_DAC_CLK_REG

#define AUDIOCODEC0_DAC_CLK_REG   0x000012e0

◆ AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLEAR_MASK

#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLEAR_MASK   0x80000000

◆ AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_OFF

#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_ON

#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_CLOCK_IS_ON   0b1

◆ AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_OFFSET

#define AUDIOCODEC0_DAC_CLK_REG_AUDIOCODEC0_DAC_CLK_GATING_OFFSET   31

◆ AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIOCODEC0_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_OFFSET

#define AUDIOCODEC0_DAC_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOCODEC0_GAR_REG

#define AUDIOCODEC0_GAR_REG   0x000012ec

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_CLEAR_MASK

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_MASK

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_MASK   0b0

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_OFFSET

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_OFFSET   0

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_PASS

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_APB_CLK_EN_PASS   0b1

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_ASSERT

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_ASSERT   0b0

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_CLEAR_MASK

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_CLEAR_MASK   0x00010000

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_DE_ASSERT

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_DE_ASSERT   0b1

◆ AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_OFFSET

#define AUDIOCODEC0_GAR_REG_AUDIOCODEC0_RST_N_OFFSET   16

◆ AUDIOCODEC1_DAC_CLK_REG

#define AUDIOCODEC1_DAC_CLK_REG   0x000012f0

◆ AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLEAR_MASK

#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLEAR_MASK   0x80000000

◆ AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_OFF

#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_ON

#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_CLOCK_IS_ON   0b1

◆ AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_OFFSET

#define AUDIOCODEC1_DAC_CLK_REG_AUDIOCODEC1_DAC_CLK_GATING_OFFSET   31

◆ AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIOCODEC1_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_OFFSET

#define AUDIOCODEC1_DAC_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOCODEC1_GAR_REG

#define AUDIOCODEC1_GAR_REG   0x000012fc

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_CLEAR_MASK

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_MASK

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_MASK   0b0

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_OFFSET

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_OFFSET   0

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_PASS

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_APB_CLK_EN_PASS   0b1

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_ASSERT

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_ASSERT   0b0

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_CLEAR_MASK

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_CLEAR_MASK   0x00010000

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_DE_ASSERT

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_DE_ASSERT   0b1

◆ AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_OFFSET

#define AUDIOCODEC1_GAR_REG_AUDIOCODEC1_RST_N_OFFSET   16

◆ AUDIOPLL_GATE_EN_REG

#define AUDIOPLL_GATE_EN_REG   0x0000191c

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_AUTO_GATE_EN_OFFSET   0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL_GATE_SW_CFG_OFFSET   16

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_AUTO_GATE_EN_OFFSET   1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL2X_GATE_SW_CFG_OFFSET   17

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_AUTO_GATE_EN_OFFSET   2

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL5X_GATE_SW_CFG_OFFSET   18

◆ AUDIOPLL_GATE_STAT_REG

#define AUDIOPLL_GATE_STAT_REG   0x0000199c

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_CLEAR_MASK   0x00010000

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL_GATE_STAT_OFFSET   16

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_CLEAR_MASK   0x00020000

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL2X_GATE_STAT_OFFSET   17

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_CLEAR_MASK   0x00040000

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL5X_GATE_STAT_OFFSET   18

◆ AXI_MON_GAR_REG

#define AXI_MON_GAR_REG   0x00001c00

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_CLEAR_MASK

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_CLEAR_MASK   0x00000002

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_MASK

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_MASK   0b0

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_OFFSET

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_OFFSET   1

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_PASS

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_CLK_EN_PASS   0b1

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_ASSERT

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_ASSERT   0b0

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_CLEAR_MASK

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_CLEAR_MASK   0x00020000

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_DE_ASSERT

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_DE_ASSERT   0b1

◆ AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_OFFSET

#define AXI_MON_GAR_REG_CE_SYS_AXIMON_RST_N_OFFSET   17

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_CLEAR_MASK

#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_CLEAR_MASK   0x00000008

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_MASK

#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_MASK   0b0

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_OFFSET

#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_OFFSET   3

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_PASS

#define AXI_MON_GAR_REG_GMAC0_AXIMON_CLK_EN_PASS   0b1

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_ASSERT

#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_ASSERT   0b0

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_CLEAR_MASK

#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_CLEAR_MASK   0x00080000

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_DE_ASSERT

#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_DE_ASSERT   0b1

◆ AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_OFFSET

#define AXI_MON_GAR_REG_GMAC0_AXIMON_RST_N_OFFSET   19

◆ AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_CLEAR_MASK

#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_CLEAR_MASK   0x00000001

◆ AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_MASK

#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_MASK   0b0

◆ AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_OFFSET

#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_OFFSET   0

◆ AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_PASS

#define AXI_MON_GAR_REG_GPU_AXIMON_CLK_EN_PASS   0b1

◆ AXI_MON_GAR_REG_GPU_AXIMON_RST_N_ASSERT

#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_ASSERT   0b0

◆ AXI_MON_GAR_REG_GPU_AXIMON_RST_N_CLEAR_MASK

#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_CLEAR_MASK   0x00010000

◆ AXI_MON_GAR_REG_GPU_AXIMON_RST_N_DE_ASSERT

#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_DE_ASSERT   0b1

◆ AXI_MON_GAR_REG_GPU_AXIMON_RST_N_OFFSET

#define AXI_MON_GAR_REG_GPU_AXIMON_RST_N_OFFSET   16

◆ AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_CLEAR_MASK

#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_CLEAR_MASK   0x00000004

◆ AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_MASK

#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_MASK   0b0

◆ AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_OFFSET

#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_OFFSET   2

◆ AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_PASS

#define AXI_MON_GAR_REG_HSI_AXIMON_CLK_EN_PASS   0b1

◆ AXI_MON_GAR_REG_HSI_AXIMON_RST_N_ASSERT

#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_ASSERT   0b0

◆ AXI_MON_GAR_REG_HSI_AXIMON_RST_N_CLEAR_MASK

#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_CLEAR_MASK   0x00040000

◆ AXI_MON_GAR_REG_HSI_AXIMON_RST_N_DE_ASSERT

#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_DE_ASSERT   0b1

◆ AXI_MON_GAR_REG_HSI_AXIMON_RST_N_OFFSET

#define AXI_MON_GAR_REG_HSI_AXIMON_RST_N_OFFSET   18

◆ BUS_CLK_GATING_REG

#define BUS_CLK_GATING_REG   0x60

◆ BUS_SOFTWARE_RESET_REG

#define BUS_SOFTWARE_RESET_REG   0x2c0

◆ CCM_MMC_CTRL_ENABLE

#define CCM_MMC_CTRL_ENABLE
Value:
(SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON \
<< SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET
Definition reg-ccu.h:1308
SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON
Definition reg-ccu.h:1311

◆ CCM_MMC_CTRL_M

#define CCM_MMC_CTRL_M (   x)    ((x) -1)

◆ CCM_MMC_CTRL_N

#define CCM_MMC_CTRL_N (   x)    ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)

◆ CCM_MMC_CTRL_OCLK_DLY

#define CCM_MMC_CTRL_OCLK_DLY (   a)    ((void) (a), 0)

◆ CCM_MMC_CTRL_OSCM24

#define CCM_MMC_CTRL_OSCM24    (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCM_MMC_CTRL_PLL6X2

#define CCM_MMC_CTRL_PLL6X2
Value:
(SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M \
<< SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M
Definition reg-ccu.h:1315
SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET
Definition reg-ccu.h:1312

◆ CCM_MMC_CTRL_PLL_PERIPH2X2

#define CCM_MMC_CTRL_PLL_PERIPH2X2
Value:
(SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M \
<< SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M
Definition reg-ccu.h:1316

◆ CCM_MMC_CTRL_SCLK_DLY

#define CCM_MMC_CTRL_SCLK_DLY (   a)    ((void) (a), 0)

◆ CCU_AHB0_CFG_REG

#define CCU_AHB0_CFG_REG   (SUNXI_CCU_BASE + AHB_CLK_REG)

◆ CCU_AVS_BGR_REG

#define CCU_AVS_BGR_REG   (SUNXI_CCU_BASE + 0x74C)

◆ CCU_AVS_CLK_REG

#define CCU_AVS_CLK_REG   (SUNXI_CCU_BASE + 0x750)

◆ CCU_CPUX_AXI_CFG_REG

#define CCU_CPUX_AXI_CFG_REG   (SUNXI_CCU_BASE + 0x500)

◆ CCU_DMA_BGR_REG

#define CCU_DMA_BGR_REG   (SUNXI_CCU_BASE + 0x70C)

◆ CCU_FAN_GATE_REG

#define CCU_FAN_GATE_REG   0x00001f30

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK12M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK16M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK24M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK25M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK   0x00000010

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK50M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET   4

◆ CCU_FAN_REG

#define CCU_FAN_REG   0x00001f3c

◆ CCU_FAN_REG_FANOUT_CLK0_EN_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK0_EN_CLEAR_MASK   0x00200000

◆ CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_ON

#define CCU_FAN_REG_FANOUT_CLK0_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_FANOUT_CLK0_EN_OFFSET

#define CCU_FAN_REG_FANOUT_CLK0_EN_OFFSET   21

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLEAR_MASK   0x00000007

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK27M

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK27M   0b101

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_FANOUT_CLK0_SEL_CLK50M_FROM_PERI0_150M_3   0b111

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_OFFSET

#define CCU_FAN_REG_FANOUT_CLK0_SEL_OFFSET   0

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_PCLK

#define CCU_FAN_REG_FANOUT_CLK0_SEL_PCLK   0b110

◆ CCU_FAN_REG_FANOUT_CLK0_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_FANOUT_CLK0_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_FANOUT_CLK1_EN_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK1_EN_CLEAR_MASK   0x00400000

◆ CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_ON

#define CCU_FAN_REG_FANOUT_CLK1_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_FANOUT_CLK1_EN_OFFSET

#define CCU_FAN_REG_FANOUT_CLK1_EN_OFFSET   22

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLEAR_MASK   0x00000038

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK27M

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK27M   0b101

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_FANOUT_CLK1_SEL_CLK50M_FROM_PERI0_150M_3   0b111

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_OFFSET

#define CCU_FAN_REG_FANOUT_CLK1_SEL_OFFSET   3

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_PCLK

#define CCU_FAN_REG_FANOUT_CLK1_SEL_PCLK   0b110

◆ CCU_FAN_REG_FANOUT_CLK1_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_FANOUT_CLK1_SEL_SYS_32K_CLK_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_FANOUT_CLK2_EN_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK2_EN_CLEAR_MASK   0x00800000

◆ CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_ON

#define CCU_FAN_REG_FANOUT_CLK2_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_FANOUT_CLK2_EN_OFFSET

#define CCU_FAN_REG_FANOUT_CLK2_EN_OFFSET   23

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLEAR_MASK   0x000001c0

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK27M

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK27M   0b101

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_FANOUT_CLK2_SEL_CLK50M_FROM_PERI0_150M_3   0b111

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_FANOUT_32K_CLK_FROM_SYSRTC

#define CCU_FAN_REG_FANOUT_CLK2_SEL_FANOUT_32K_CLK_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_OFFSET

#define CCU_FAN_REG_FANOUT_CLK2_SEL_OFFSET   6

◆ CCU_FAN_REG_FANOUT_CLK2_SEL_PCLK

#define CCU_FAN_REG_FANOUT_CLK2_SEL_PCLK   0b110

◆ CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_CLEAR_MASK

#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_CLEAR_MASK   0x80000000

◆ CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_PERI0_160M_10

#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_PERI0_160M_10   0b0

◆ CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_RC_16M

#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_FROM_RC_16M   0b1

◆ CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_OFFSET

#define CCU_FAN_REG_FANOUT_RC_16M_CLK_SEL_OFFSET   31

◆ CCU_GPADC_BGR_REG

#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC0_GAR_REG)

◆ CCU_GPADC_CLK_REG

#define CCU_GPADC_CLK_REG   (SUNXI_CCU_BASE + GPADC0_CLK_REG)

◆ CCU_IOMMU_BGR_REG

#define CCU_IOMMU_BGR_REG   (SUNXI_CCU_BASE + 0x7bc)

◆ CCU_LRADC_BGR_REG

#define CCU_LRADC_BGR_REG   (SUNXI_CCU_BASE + 0x0A9C)

◆ CCU_MBUS_GATE_ENABLE_REG

#define CCU_MBUS_GATE_ENABLE_REG   (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)

◆ CCU_NAND_BGR_REG

#define CCU_NAND_BGR_REG   (SUNXI_CCU_BASE + 0x82C)

◆ CCU_NAND_CLK_REG

#define CCU_NAND_CLK_REG   (SUNXI_CCU_BASE + 0x810)

◆ CCU_PLL_AUDIO_CTRL_REG

#define CCU_PLL_AUDIO_CTRL_REG   (SUNXI_CCU_BASE + 0x78)

◆ CCU_PLL_COM_CTRL_REG

#define CCU_PLL_COM_CTRL_REG   (SUNXI_CCU_BASE + 0x60)

◆ CCU_PLL_CPUX_CTRL_REG

#define CCU_PLL_CPUX_CTRL_REG   (SUNXI_CCU_BASE + 0x00)

◆ CCU_PLL_DDR0_CTRL_REG

#define CCU_PLL_DDR0_CTRL_REG   (SUNXI_CCU_BASE + 0x10)

◆ CCU_PLL_DDR1_CTRL_REG

#define CCU_PLL_DDR1_CTRL_REG   (SUNXI_CCU_BASE + 0x18)

◆ CCU_PLL_GPU_CTRL_REG

#define CCU_PLL_GPU_CTRL_REG   (SUNXI_CCU_BASE + 0x30)

◆ CCU_PLL_HSIC_CTRL_REG

#define CCU_PLL_HSIC_CTRL_REG   (SUNXI_CCU_BASE + 0x70)

◆ CCU_PLL_PERI0_CTRL_REG

#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + 0x20)

◆ CCU_PLL_PERI1_CTRL_REG

#define CCU_PLL_PERI1_CTRL_REG   (SUNXI_CCU_BASE + 0x28)

◆ CCU_PLL_VE_CTRL_REG

#define CCU_PLL_VE_CTRL_REG   (SUNXI_CCU_BASE + 0x58)

◆ CCU_PLL_VIDE00_CTRL_REG

#define CCU_PLL_VIDE00_CTRL_REG   (SUNXI_CCU_BASE + 0x40)

◆ CCU_PLL_VIDE01_CTRL_REG

#define CCU_PLL_VIDE01_CTRL_REG   (SUNXI_CCU_BASE + 0x48)

◆ CCU_PLL_VIDE02_CTRL_REG

#define CCU_PLL_VIDE02_CTRL_REG   (SUNXI_CCU_BASE + 0x50)

◆ CCU_PLL_VIDE03_CTRL_REG

#define CCU_PLL_VIDE03_CTRL_REG   (SUNXI_CCU_BASE + 0x68)

◆ CCU_SCR_BGR_REG

#define CCU_SCR_BGR_REG   (SUNXI_CCU_BASE + 0x93C)

◆ CCU_SDMMC0_CLK_REG

#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)

◆ CCU_SDMMC1_CLK_REG

#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)

◆ CCU_SDMMC2_CLK_REG

#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + SMHC2_CLK_REG)

◆ CCU_SEC_SWITCH_REG

#define CCU_SEC_SWITCH_REG   0x00001f00

◆ CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002

◆ CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001

◆ CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0

◆ CCU_SMHC0_BGR_REG

#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC0_GAR_REG)

◆ CCU_SPI0_CLK_REG

#define CCU_SPI0_CLK_REG   (SUNXI_CCU_BASE + 0x940)

◆ CCU_SPI1_CLK_REG

#define CCU_SPI1_CLK_REG   (SUNXI_CCU_BASE + 0x944)

◆ CCU_SPI_BGR_CLK_REG

#define CCU_SPI_BGR_CLK_REG   (SUNXI_CCU_BASE + 0x96C)

◆ CCU_TWI_BGR_REG

#define CCU_TWI_BGR_REG   (SUNXI_CCU_BASE + 0x91C)

◆ CCU_UART_BGR_REG

#define CCU_UART_BGR_REG   (SUNXI_CCU_BASE + UART0_GAR_REG)

◆ CCU_USB0_CLK_REG

#define CCU_USB0_CLK_REG   (SUNXI_CCU_BASE + 0xA70)

◆ CCU_USB_BGR_REG

#define CCU_USB_BGR_REG   (SUNXI_CCU_BASE + 0xA8C)

◆ CCU_VE_BGR_REG

#define CCU_VE_BGR_REG   (SUNXI_CCU_BASE + 0x69C)

◆ CCU_VE_CLK_REG

#define CCU_VE_CLK_REG   (SUNXI_CCU_BASE + 0x690)

◆ CCU_VERSION_REG

#define CCU_VERSION_REG   0x00001ff0

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16

◆ CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff

◆ CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0

◆ CE_SYS_CLK_REG

#define CE_SYS_CLK_REG   0x00000ac0

◆ CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLEAR_MASK

#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLEAR_MASK   0x80000000

◆ CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLOCK_IS_OFF

#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET

#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET   31

◆ CE_SYS_CLK_REG_CE_SYS_CLK_GATING_SECURE_DEBUG

#define CE_SYS_CLK_REG_CE_SYS_CLK_GATING_SECURE_DEBUG   0b1

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CE_SYS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET

#define CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011

◆ CE_SYS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define CE_SYS_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ CE_SYS_CLK_REG_FACTOR_M_CLEAR_MASK

#define CE_SYS_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CE_SYS_CLK_REG_FACTOR_M_OFFSET

#define CE_SYS_CLK_REG_FACTOR_M_OFFSET   0

◆ CE_SYS_GAR_REG

#define CE_SYS_GAR_REG   0x00000ac4

◆ CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_CLEAR_MASK

#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK

#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK   0x0

◆ CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET

#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_OFFSET   0

◆ CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_SECURE_DEBUG

#define CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_SECURE_DEBUG   0b1

◆ CE_SYS_GAR_REG_CE_SYS_RST_N_ASSERT

#define CE_SYS_GAR_REG_CE_SYS_RST_N_ASSERT   0b0

◆ CE_SYS_GAR_REG_CE_SYS_RST_N_CLEAR_MASK

#define CE_SYS_GAR_REG_CE_SYS_RST_N_CLEAR_MASK   0x00010000

◆ CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET

#define CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET   16

◆ CE_SYS_GAR_REG_CE_SYS_RST_N_SECURE_DEBUG

#define CE_SYS_GAR_REG_CE_SYS_RST_N_SECURE_DEBUG   0b1

◆ CE_USE_PLATFORM_CLOCK_FUNC

#define CE_USE_PLATFORM_CLOCK_FUNC

◆ CLK27M_FAN_REG

#define CLK27M_FAN_REG   0x00001f34

◆ CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f

◆ CLK27M_FAN_REG_CLK27M_DIV0_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0

◆ CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00001f00

◆ CLK27M_FAN_REG_CLK27M_DIV1_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8

◆ CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1

◆ CLK27M_FAN_REG_CLK27M_EN_OFFSET

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X   0b000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X   0b001

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X   0b010

◆ CLK_DBG_REG

#define CLK_DBG_REG   0x00001f50

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLK   0b000

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLK   0b001

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLK   0b010

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLK   0b011

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_CE_SYS_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CE_SYS_CLK   0b110

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK   0x00000007

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_CPU_SYS_DP_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_CPU_SYS_DP_CLK   0b111

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLK   0b100

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLK

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLK   0b101

◆ CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET

#define CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET   0

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_CLEAR_MASK

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_CLEAR_MASK   0x03000000

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV1

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV1   0b00

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV2

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV2   0b01

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV4

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV4   0b10

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV8

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_DIV8   0b11

◆ CLK_DBG_REG_MDL_CLK_DBG_DIV_OFFSET

#define CLK_DBG_REG_MDL_CLK_DBG_DIV_OFFSET   24

◆ CLK_DBG_REG_MDL_CLK_DBG_SEL_CLEAR_MASK

#define CLK_DBG_REG_MDL_CLK_DBG_SEL_CLEAR_MASK   0x00070000

◆ CLK_DBG_REG_MDL_CLK_DBG_SEL_DISPLL0_CK_HS

#define CLK_DBG_REG_MDL_CLK_DBG_SEL_DISPLL0_CK_HS   0b001

◆ CLK_DBG_REG_MDL_CLK_DBG_SEL_OFFSET

#define CLK_DBG_REG_MDL_CLK_DBG_SEL_OFFSET   16

◆ CLK_DBG_REG_MDL_CLK_DBG_SEL_STBY_SYS_BACKDOOR_CLK

#define CLK_DBG_REG_MDL_CLK_DBG_SEL_STBY_SYS_BACKDOOR_CLK   0b000

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CLEAR_MASK

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CLEAR_MASK   0x000001f0

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_0

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_0   0b1000

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_1

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_1   0b1001

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_2

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_2   0b1010

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_3

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_FSENSOR_CLK_3   0b1011

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_3

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU0_PSENSOR_CLK_3   0b0011

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_0

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_0   0b1100

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_1

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_FSENSOR_CLK_1   0b1101

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_0

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_0   0b0100

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_1

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU1_PSENSOR_CLK_1   0b0101

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_0

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_0   0b1110

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_1

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_FSENSOR_CLK_1   0b1111

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_0

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_0   0b0110

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_1

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_CPU_CLU2_PSENSOR_CLK_1   0b0111

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_DRAMC_PSENSOR_CLK

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_DRAMC_PSENSOR_CLK   0b0010

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_GPU_PSENSOR_CLK

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_GPU_PSENSOR_CLK   0b0001

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_OFFSET

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_OFFSET   4

◆ CLK_DBG_REG_PSR_CLK_DBG_SEL_VE0_PSENSOR_CLK

#define CLK_DBG_REG_PSR_CLK_DBG_SEL_VE0_PSENSOR_CLK   0b0000

◆ CLK_FAN_REG

#define CLK_FAN_REG   0x00001f38

◆ CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0

◆ CLK_FAN_REG_PCLK_DIV1_OFFSET

#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5

◆ CLK_FAN_REG_PCLK_DIV_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f

◆ CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1

◆ CLK_FAN_REG_PCLK_DIV_EN_OFFSET

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31

◆ CLK_FAN_REG_PCLK_DIV_OFFSET

#define CLK_FAN_REG_PCLK_DIV_OFFSET   0

◆ CM_HSI_CFG_REG

#define CM_HSI_CFG_REG   0x00001b28

◆ CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_CLEAR_MASK

#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_CLEAR_MASK   0x00000001

◆ CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_DISABLE

#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_DISABLE   0b0

◆ CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_ENABLE

#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_ENABLE   0b1

◆ CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_OFFSET

#define CM_HSI_CFG_REG_CM_HSI_MODULE_MODE_OFFSET   0

◆ CM_HSI_CFG_REG_CM_HSI_STATUS_CLEAR_MASK

#define CM_HSI_CFG_REG_CM_HSI_STATUS_CLEAR_MASK   0x00030000

◆ CM_HSI_CFG_REG_CM_HSI_STATUS_OFFSET

#define CM_HSI_CFG_REG_CM_HSI_STATUS_OFFSET   16

◆ CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_OFF

#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_OFF   0b01

◆ CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_ON

#define CM_HSI_CFG_REG_CM_HSI_STATUS_POWER_ON   0b10

◆ CM_VE_CFG_REG

#define CM_VE_CFG_REG   0x00001b10

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK   0x00000001

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE   0b0

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE   0b1

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET   0

◆ CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK

#define CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK   0x00030000

◆ CM_VE_CFG_REG_CM_VE_STATUS_OFFSET

#define CM_VE_CFG_REG_CM_VE_STATUS_OFFSET   16

◆ CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF

#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF   0b01

◆ CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON

#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON   0b10

◆ CM_VIDEO_IN_CFG_REG

#define CM_VIDEO_IN_CFG_REG   0x00001b00

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_CLEAR_MASK

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_CLEAR_MASK   0x00000001

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_DISABLE

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_DISABLE   0b0

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_ENABLE

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_ENABLE   0b1

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_OFFSET

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_MODULE_MODE_OFFSET   0

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_CLEAR_MASK

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_CLEAR_MASK   0x00030000

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_OFFSET

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_OFFSET   16

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_OFF

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_OFF   0b01

◆ CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_ON

#define CM_VIDEO_IN_CFG_REG_CM_VIDEO_IN_STATUS_POWER_ON   0b10

◆ CM_VIDEO_OUT0_CFG_REG

#define CM_VIDEO_OUT0_CFG_REG   0x00001b34

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_CLEAR_MASK

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_CLEAR_MASK   0x00000001

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_DISABLE

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_DISABLE   0b0

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_ENABLE

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_ENABLE   0b1

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_OFFSET

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_MODULE_MODE_OFFSET   0

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_CLEAR_MASK

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_CLEAR_MASK   0x00030000

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_OFFSET

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_OFFSET   16

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_OFF

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_OFF   0b01

◆ CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_ON

#define CM_VIDEO_OUT0_CFG_REG_CM_VIDEO_OUT0_STATUS_POWER_ON   0b10

◆ COMBOPHY0_CLK_REG

#define COMBOPHY0_CLK_REG   0x000015c0

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_OFFSET

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define COMBOPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLEAR_MASK

#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLEAR_MASK   0x80000000

◆ COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_OFF

#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_ON

#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_CLOCK_IS_ON   0b1

◆ COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_OFFSET

#define COMBOPHY0_CLK_REG_COMBOPHY0_CLK_GATING_OFFSET   31

◆ COMBOPHY0_CLK_REG_FACTOR_M_CLEAR_MASK

#define COMBOPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ COMBOPHY0_CLK_REG_FACTOR_M_OFFSET

#define COMBOPHY0_CLK_REG_FACTOR_M_OFFSET   0

◆ CPU_SYS_DP_CLK_REG

#define CPU_SYS_DP_CLK_REG   0x00000548

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLEAR_MASK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLEAR_MASK   0x80000000

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_OFF

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_ON

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_CLOCK_IS_ON   0b1

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_OFFSET

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_GATING_OFFSET   31

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_CLEAR_MASK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_CLEAR_MASK   0x07000000

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_HDR_CLK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_HDR_CLK   0b101

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_OFFSET

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_OFFSET   24

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0_800M

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0_800M   0b011

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0PLL2X

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_PERI0PLL2X   0b001

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_SYS_24M_CLK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_SYS_24M_CLK   0b000

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL3X

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL3X   0b100

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL4X

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_CLK_SEL_VIDEO0PLL4X   0b010

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_CLEAR_MASK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_CLEAR_MASK   0x0000001f

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_OFFSET

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_DIV1_OFFSET   0

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_CLEAR_MASK

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_CLEAR_MASK   0x08000000

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_INVALID

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_INVALID   0b0

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_OFFSET

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_OFFSET   27

◆ CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_VALID

#define CPU_SYS_DP_CLK_REG_CPU_SYS_DP_UPD_VALID   0b1

◆ CPUX_GIC_CLK_REG

#define CPUX_GIC_CLK_REG   0x00000560

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define CPUX_GIC_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b001

◆ CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLEAR_MASK

#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLEAR_MASK   0x80000000

◆ CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_OFF

#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_ON

#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_CLOCK_IS_ON   0b1

◆ CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_OFFSET

#define CPUX_GIC_CLK_REG_CPUX_GIC_CLK_GATING_OFFSET   31

◆ CPUX_GIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define CPUX_GIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CPUX_GIC_CLK_REG_FACTOR_M_OFFSET

#define CPUX_GIC_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_CLK_REG

#define CSI_CLK_REG   0x00001840

◆ CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ CSI_CLK_REG_CLK_SRC_SEL_VEPLL

#define CSI_CLK_REG_CLK_SRC_SEL_VEPLL   0b111

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b001

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_CLK_REG_CSI_CLK_GATING_OFFSET

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31

◆ CSI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_CLK_REG_FACTOR_M_OFFSET

#define CSI_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG

#define CSI_MASTER0_CLK_REG   0x00001800

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31

◆ CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER1_CLK_REG

#define CSI_MASTER1_CLK_REG   0x00001804

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31

◆ CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER2_CLK_REG

#define CSI_MASTER2_CLK_REG   0x00001808

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b110

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b010

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b100

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31

◆ CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8

◆ DAP_GAR_REG

#define DAP_GAR_REG   0x000007ac

◆ DAP_GAR_REG_DAP_AHB_CLK_EN_CLEAR_MASK

#define DAP_GAR_REG_DAP_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ DAP_GAR_REG_DAP_AHB_CLK_EN_MASK

#define DAP_GAR_REG_DAP_AHB_CLK_EN_MASK   0x0

◆ DAP_GAR_REG_DAP_AHB_CLK_EN_OFFSET

#define DAP_GAR_REG_DAP_AHB_CLK_EN_OFFSET   0

◆ DAP_GAR_REG_DAP_AHB_CLK_EN_SECURE_DEBUG

#define DAP_GAR_REG_DAP_AHB_CLK_EN_SECURE_DEBUG   0b1

◆ DAP_GAR_REG_DAP_RST_N_ASSERT

#define DAP_GAR_REG_DAP_RST_N_ASSERT   0b0

◆ DAP_GAR_REG_DAP_RST_N_CLEAR_MASK

#define DAP_GAR_REG_DAP_RST_N_CLEAR_MASK   0x00010000

◆ DAP_GAR_REG_DAP_RST_N_OFFSET

#define DAP_GAR_REG_DAP_RST_N_OFFSET   16

◆ DAP_GAR_REG_DAP_RST_N_SECURE_DEBUG

#define DAP_GAR_REG_DAP_RST_N_SECURE_DEBUG   0b1

◆ DAP_REQ_CTRL_REG

#define DAP_REQ_CTRL_REG   0x00001f10

◆ DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_CLEAR_MASK

#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_CLEAR_MASK   0x00000001

◆ DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_OFFSET

#define DAP_REQ_CTRL_REG_DAP_REQ_ENABLE_OFFSET   0

◆ DCU_GAR_REG

#define DCU_GAR_REG   0x000007a4

◆ DCU_GAR_REG_DCU_CLK_EN_CLEAR_MASK

#define DCU_GAR_REG_DCU_CLK_EN_CLEAR_MASK   0x00000001

◆ DCU_GAR_REG_DCU_CLK_EN_MASK

#define DCU_GAR_REG_DCU_CLK_EN_MASK   0x0

◆ DCU_GAR_REG_DCU_CLK_EN_OFFSET

#define DCU_GAR_REG_DCU_CLK_EN_OFFSET   0

◆ DCU_GAR_REG_DCU_CLK_EN_PASS

#define DCU_GAR_REG_DCU_CLK_EN_PASS   0b1

◆ DCU_GAR_REG_DCU_RST_N_ASSERT

#define DCU_GAR_REG_DCU_RST_N_ASSERT   0b0

◆ DCU_GAR_REG_DCU_RST_N_CLEAR_MASK

#define DCU_GAR_REG_DCU_RST_N_CLEAR_MASK   0x00010000

◆ DCU_GAR_REG_DCU_RST_N_DE_ASSERT

#define DCU_GAR_REG_DCU_RST_N_DE_ASSERT   0b1

◆ DCU_GAR_REG_DCU_RST_N_OFFSET

#define DCU_GAR_REG_DCU_RST_N_OFFSET   16

◆ DE0_CLK_REG

#define DE0_CLK_REG   0x00000a00

◆ DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DE0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000

◆ DE0_CLK_REG_CLK_SRC_SEL_VEPLL

#define DE0_CLK_REG_CLK_SRC_SEL_VEPLL   0b011

◆ DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK

#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK   0x80000000

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON   0b1

◆ DE0_CLK_REG_DE0_CLK_GATING_OFFSET

#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET   31

◆ DE0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DE0_CLK_REG_FACTOR_M_OFFSET

#define DE0_CLK_REG_FACTOR_M_OFFSET   0

◆ DE0_GAR_REG

#define DE0_GAR_REG   0x00000a04

◆ DE0_GAR_REG_DE0_AHB_CLK_EN_CLEAR_MASK

#define DE0_GAR_REG_DE0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ DE0_GAR_REG_DE0_AHB_CLK_EN_MASK

#define DE0_GAR_REG_DE0_AHB_CLK_EN_MASK   0x0

◆ DE0_GAR_REG_DE0_AHB_CLK_EN_OFFSET

#define DE0_GAR_REG_DE0_AHB_CLK_EN_OFFSET   0

◆ DE0_GAR_REG_DE0_AHB_CLK_EN_PASS

#define DE0_GAR_REG_DE0_AHB_CLK_EN_PASS   0b1

◆ DE0_GAR_REG_DE0_RST_N_ASSERT

#define DE0_GAR_REG_DE0_RST_N_ASSERT   0b0

◆ DE0_GAR_REG_DE0_RST_N_CLEAR_MASK

#define DE0_GAR_REG_DE0_RST_N_CLEAR_MASK   0x00010000

◆ DE0_GAR_REG_DE0_RST_N_DE_ASSERT

#define DE0_GAR_REG_DE0_RST_N_DE_ASSERT   0b1

◆ DE0_GAR_REG_DE0_RST_N_OFFSET

#define DE0_GAR_REG_DE0_RST_N_OFFSET   16

◆ DMA0_GAR_REG

#define DMA0_GAR_REG   0x00000704

◆ DMA0_GAR_REG_DMA0_AHB_CLK_EN_CLEAR_MASK

#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ DMA0_GAR_REG_DMA0_AHB_CLK_EN_MASK

#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_MASK   0x0

◆ DMA0_GAR_REG_DMA0_AHB_CLK_EN_OFFSET

#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_OFFSET   0

◆ DMA0_GAR_REG_DMA0_AHB_CLK_EN_PASS

#define DMA0_GAR_REG_DMA0_AHB_CLK_EN_PASS   0b1

◆ DMA0_GAR_REG_DMA0_RST_N_ASSERT

#define DMA0_GAR_REG_DMA0_RST_N_ASSERT   0b0

◆ DMA0_GAR_REG_DMA0_RST_N_CLEAR_MASK

#define DMA0_GAR_REG_DMA0_RST_N_CLEAR_MASK   0x00010000

◆ DMA0_GAR_REG_DMA0_RST_N_DE_ASSERT

#define DMA0_GAR_REG_DMA0_RST_N_DE_ASSERT   0b1

◆ DMA0_GAR_REG_DMA0_RST_N_OFFSET

#define DMA0_GAR_REG_DMA0_RST_N_OFFSET   16

◆ DMA_GATING_BASE

#define DMA_GATING_BASE   CCU_DMA_BGR_REG

◆ DMA_GATING_BIT

#define DMA_GATING_BIT   (0)

◆ DMA_GATING_PASS

#define DMA_GATING_PASS   (1)

◆ DMIC_CLK_REG

#define DMIC_CLK_REG   0x000012c0

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DMIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK   0x80000000

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON   0b1

◆ DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET

#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET   31

◆ DMIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DMIC_CLK_REG_FACTOR_M_OFFSET

#define DMIC_CLK_REG_FACTOR_M_OFFSET   0

◆ DMIC_GAR_REG

#define DMIC_GAR_REG   0x000012cc

◆ DMIC_GAR_REG_DMIC_APB_CLK_EN_CLEAR_MASK

#define DMIC_GAR_REG_DMIC_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ DMIC_GAR_REG_DMIC_APB_CLK_EN_MASK

#define DMIC_GAR_REG_DMIC_APB_CLK_EN_MASK   0b0

◆ DMIC_GAR_REG_DMIC_APB_CLK_EN_OFFSET

#define DMIC_GAR_REG_DMIC_APB_CLK_EN_OFFSET   0

◆ DMIC_GAR_REG_DMIC_APB_CLK_EN_PASS

#define DMIC_GAR_REG_DMIC_APB_CLK_EN_PASS   0b1

◆ DMIC_GAR_REG_DMIC_RST_N_ASSERT

#define DMIC_GAR_REG_DMIC_RST_N_ASSERT   0b0

◆ DMIC_GAR_REG_DMIC_RST_N_CLEAR_MASK

#define DMIC_GAR_REG_DMIC_RST_N_CLEAR_MASK   0x00010000

◆ DMIC_GAR_REG_DMIC_RST_N_DE_ASSERT

#define DMIC_GAR_REG_DMIC_RST_N_DE_ASSERT   0b1

◆ DMIC_GAR_REG_DMIC_RST_N_OFFSET

#define DMIC_GAR_REG_DMIC_RST_N_OFFSET   16

◆ DRAMC_GAR_REG

#define DRAMC_GAR_REG   0x00000c0c

◆ DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_CLEAR_MASK

#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_MASK

#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_MASK   0x0

◆ DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_OFFSET

#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_OFFSET   0

◆ DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_PASS

#define DRAMC_GAR_REG_DRAMC_AHB_CLK_EN_PASS   0b1

◆ DRAMC_GAR_REG_DRAMC_RST_N_ASSERT

#define DRAMC_GAR_REG_DRAMC_RST_N_ASSERT   0b0

◆ DRAMC_GAR_REG_DRAMC_RST_N_CLEAR_MASK

#define DRAMC_GAR_REG_DRAMC_RST_N_CLEAR_MASK   0x00010000

◆ DRAMC_GAR_REG_DRAMC_RST_N_DE_ASSERT

#define DRAMC_GAR_REG_DRAMC_RST_N_DE_ASSERT   0b1

◆ DRAMC_GAR_REG_DRAMC_RST_N_OFFSET

#define DRAMC_GAR_REG_DRAMC_RST_N_OFFSET   16

◆ eDP_GAR_REG

#define eDP_GAR_REG   0x0000164c

◆ eDP_GAR_REG_EDP_AHB_CLK_EN_CLEAR_MASK

#define eDP_GAR_REG_EDP_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ eDP_GAR_REG_EDP_AHB_CLK_EN_MASK

#define eDP_GAR_REG_EDP_AHB_CLK_EN_MASK   0b0

◆ eDP_GAR_REG_EDP_AHB_CLK_EN_OFFSET

#define eDP_GAR_REG_EDP_AHB_CLK_EN_OFFSET   0

◆ eDP_GAR_REG_EDP_AHB_CLK_EN_PASS

#define eDP_GAR_REG_EDP_AHB_CLK_EN_PASS   0b1

◆ eDP_GAR_REG_EDP_RST_N_ASSERT

#define eDP_GAR_REG_EDP_RST_N_ASSERT   0b0

◆ eDP_GAR_REG_EDP_RST_N_CLEAR_MASK

#define eDP_GAR_REG_EDP_RST_N_CLEAR_MASK   0x00010000

◆ eDP_GAR_REG_EDP_RST_N_DE_ASSERT

#define eDP_GAR_REG_EDP_RST_N_DE_ASSERT   0b1

◆ eDP_GAR_REG_EDP_RST_N_OFFSET

#define eDP_GAR_REG_EDP_RST_N_OFFSET   16

◆ EINK_GAR_REG

#define EINK_GAR_REG   0x00000a6c

◆ EINK_GAR_REG_EINK_AHB_CLK_EN_CLEAR_MASK

#define EINK_GAR_REG_EINK_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ EINK_GAR_REG_EINK_AHB_CLK_EN_MASK

#define EINK_GAR_REG_EINK_AHB_CLK_EN_MASK   0x0

◆ EINK_GAR_REG_EINK_AHB_CLK_EN_OFFSET

#define EINK_GAR_REG_EINK_AHB_CLK_EN_OFFSET   0

◆ EINK_GAR_REG_EINK_AHB_CLK_EN_PASS

#define EINK_GAR_REG_EINK_AHB_CLK_EN_PASS   0b1

◆ EINK_GAR_REG_EINK_RST_N_ASSERT

#define EINK_GAR_REG_EINK_RST_N_ASSERT   0b0

◆ EINK_GAR_REG_EINK_RST_N_CLEAR_MASK

#define EINK_GAR_REG_EINK_RST_N_CLEAR_MASK   0x00010000

◆ EINK_GAR_REG_EINK_RST_N_DE_ASSERT

#define EINK_GAR_REG_EINK_RST_N_DE_ASSERT   0b1

◆ EINK_GAR_REG_EINK_RST_N_OFFSET

#define EINK_GAR_REG_EINK_RST_N_OFFSET   16

◆ EINK_PANEL_CLK_REG

#define EINK_PANEL_CLK_REG   0x00000a64

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK   0x80000000

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF   0b0

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON   0b1

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET   31

◆ EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK

#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ EINK_PANEL_CLK_REG_FACTOR_M_OFFSET

#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET   0

◆ G2D_CLK_REG

#define G2D_CLK_REG   0x00000a40

◆ G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ G2D_CLK_REG_CLK_SRC_SEL_OFFSET

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b10

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b01

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b00

◆ G2D_CLK_REG_FACTOR_M_CLEAR_MASK

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ G2D_CLK_REG_FACTOR_M_OFFSET

#define G2D_CLK_REG_FACTOR_M_OFFSET   0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1

◆ G2D_CLK_REG_G2D_CLK_GATING_OFFSET

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31

◆ G2D_GAR_REG

#define G2D_GAR_REG   0x00000a44

◆ G2D_GAR_REG_G2D_AHB_CLK_EN_CLEAR_MASK

#define G2D_GAR_REG_G2D_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ G2D_GAR_REG_G2D_AHB_CLK_EN_MASK

#define G2D_GAR_REG_G2D_AHB_CLK_EN_MASK   0x0

◆ G2D_GAR_REG_G2D_AHB_CLK_EN_OFFSET

#define G2D_GAR_REG_G2D_AHB_CLK_EN_OFFSET   0

◆ G2D_GAR_REG_G2D_AHB_CLK_EN_PASS

#define G2D_GAR_REG_G2D_AHB_CLK_EN_PASS   0b1

◆ G2D_GAR_REG_G2D_RST_N_ASSERT

#define G2D_GAR_REG_G2D_RST_N_ASSERT   0b0

◆ G2D_GAR_REG_G2D_RST_N_CLEAR_MASK

#define G2D_GAR_REG_G2D_RST_N_CLEAR_MASK   0x00010000

◆ G2D_GAR_REG_G2D_RST_N_DE_ASSERT

#define G2D_GAR_REG_G2D_RST_N_DE_ASSERT   0b1

◆ G2D_GAR_REG_G2D_RST_N_OFFSET

#define G2D_GAR_REG_G2D_RST_N_OFFSET   16

◆ GATING_SHIFT

#define GATING_SHIFT   (0)

◆ GMAC0_GAR_REG

#define GMAC0_GAR_REG   0x0000140c

◆ GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_CLEAR_MASK

#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_MASK

#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_MASK   0b0

◆ GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_OFFSET

#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_OFFSET   0

◆ GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_PASS

#define GMAC0_GAR_REG_GMAC0_AHB_CLK_EN_PASS   0b1

◆ GMAC0_GAR_REG_GMAC0_AHB_RST_N_ASSERT

#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_ASSERT   0b0

◆ GMAC0_GAR_REG_GMAC0_AHB_RST_N_CLEAR_MASK

#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_CLEAR_MASK   0x00010000

◆ GMAC0_GAR_REG_GMAC0_AHB_RST_N_DE_ASSERT

#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_DE_ASSERT   0b1

◆ GMAC0_GAR_REG_GMAC0_AHB_RST_N_OFFSET

#define GMAC0_GAR_REG_GMAC0_AHB_RST_N_OFFSET   16

◆ GMAC0_GAR_REG_GMAC0_AXI_RST_N_ASSERT

#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_ASSERT   0b0

◆ GMAC0_GAR_REG_GMAC0_AXI_RST_N_CLEAR_MASK

#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_CLEAR_MASK   0x00020000

◆ GMAC0_GAR_REG_GMAC0_AXI_RST_N_DE_ASSERT

#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_DE_ASSERT   0b1

◆ GMAC0_GAR_REG_GMAC0_AXI_RST_N_OFFSET

#define GMAC0_GAR_REG_GMAC0_AXI_RST_N_OFFSET   17

◆ GMAC0_PHY_CLK_REG

#define GMAC0_PHY_CLK_REG   0x00001400

◆ GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET

#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET   0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK   0x80000000

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON   0b1

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET   31

◆ GPADC0_CLK_REG

#define GPADC0_CLK_REG   0x00000fc0

◆ GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M

#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M   0b001

◆ GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010

◆ GPADC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define GPADC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ GPADC0_CLK_REG_FACTOR_M_OFFSET

#define GPADC0_CLK_REG_FACTOR_M_OFFSET   0

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK   0x80000000

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON   0b1

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET   31

◆ GPADC0_GAR_REG

#define GPADC0_GAR_REG   0x00000fc4

◆ GPADC0_GAR_REG_GPADC0_APB_CLK_EN_CLEAR_MASK

#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ GPADC0_GAR_REG_GPADC0_APB_CLK_EN_MASK

#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_MASK   0x0

◆ GPADC0_GAR_REG_GPADC0_APB_CLK_EN_OFFSET

#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_OFFSET   0

◆ GPADC0_GAR_REG_GPADC0_APB_CLK_EN_PASS

#define GPADC0_GAR_REG_GPADC0_APB_CLK_EN_PASS   0b1

◆ GPADC0_GAR_REG_GPADC0_RST_N_ASSERT

#define GPADC0_GAR_REG_GPADC0_RST_N_ASSERT   0b0

◆ GPADC0_GAR_REG_GPADC0_RST_N_CLEAR_MASK

#define GPADC0_GAR_REG_GPADC0_RST_N_CLEAR_MASK   0x00010000

◆ GPADC0_GAR_REG_GPADC0_RST_N_DE_ASSERT

#define GPADC0_GAR_REG_GPADC0_RST_N_DE_ASSERT   0b1

◆ GPADC0_GAR_REG_GPADC0_RST_N_OFFSET

#define GPADC0_GAR_REG_GPADC0_RST_N_OFFSET   16

◆ GPU_CLK_REG

#define GPU_CLK_REG   0x00000b20

◆ GPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ GPU_CLK_REG_CLK_SRC_SEL_GPUPLL

#define GPU_CLK_REG_CLK_SRC_SEL_GPUPLL   0b000

◆ GPU_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPU_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GPU_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b101

◆ GPU_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100

◆ GPU_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011

◆ GPU_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ GPU_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define GPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ GPU_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ GPU_CLK_REG_FACTOR_M_MASK_15_CYCLES_AT_16_CYCLES

#define GPU_CLK_REG_FACTOR_M_MASK_15_CYCLES_AT_16_CYCLES   0b1111

◆ GPU_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES

#define GPU_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES   0b0001

◆ GPU_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES

#define GPU_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES   0b0010

◆ GPU_CLK_REG_FACTOR_M_MASK_3_CYCLES_AT_16_CYCLES

#define GPU_CLK_REG_FACTOR_M_MASK_3_CYCLES_AT_16_CYCLES   0b0011

◆ GPU_CLK_REG_FACTOR_M_NOT_MASK

#define GPU_CLK_REG_FACTOR_M_NOT_MASK   0x0000

◆ GPU_CLK_REG_FACTOR_M_OFFSET

#define GPU_CLK_REG_FACTOR_M_OFFSET   0

◆ GPU_CLK_REG_GPU_CLK_GATING_CLEAR_MASK

#define GPU_CLK_REG_GPU_CLK_GATING_CLEAR_MASK   0x80000000

◆ GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_OFF

#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_ON

#define GPU_CLK_REG_GPU_CLK_GATING_CLOCK_IS_ON   0b1

◆ GPU_CLK_REG_GPU_CLK_GATING_OFFSET

#define GPU_CLK_REG_GPU_CLK_GATING_OFFSET   31

◆ GPU_GAR_REG

#define GPU_GAR_REG   0x00000b24

◆ GPU_GAR_REG_GPU_AHB_CLK_EN_CLEAR_MASK

#define GPU_GAR_REG_GPU_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ GPU_GAR_REG_GPU_AHB_CLK_EN_MASK

#define GPU_GAR_REG_GPU_AHB_CLK_EN_MASK   0x0

◆ GPU_GAR_REG_GPU_AHB_CLK_EN_OFFSET

#define GPU_GAR_REG_GPU_AHB_CLK_EN_OFFSET   0

◆ GPU_GAR_REG_GPU_AHB_CLK_EN_PASS

#define GPU_GAR_REG_GPU_AHB_CLK_EN_PASS   0b1

◆ GPU_GAR_REG_GPU_RST_N_ASSERT

#define GPU_GAR_REG_GPU_RST_N_ASSERT   0b0

◆ GPU_GAR_REG_GPU_RST_N_CLEAR_MASK

#define GPU_GAR_REG_GPU_RST_N_CLEAR_MASK   0x00010000

◆ GPU_GAR_REG_GPU_RST_N_DE_ASSERT

#define GPU_GAR_REG_GPU_RST_N_DE_ASSERT   0b1

◆ GPU_GAR_REG_GPU_RST_N_OFFSET

#define GPU_GAR_REG_GPU_RST_N_OFFSET   16

◆ GPUPLL_GATE_EN_REG

#define GPUPLL_GATE_EN_REG   0x00001914

◆ GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_AUTO

#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_AUTO   0b0

◆ GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_CLEAR_MASK

#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_NO_AUTO

#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_OFFSET

#define GPUPLL_GATE_EN_REG_GPUPLL_AUTO_GATE_EN_OFFSET   0

◆ GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_CLEAR_MASK

#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_DISABLE

#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_DISABLE   0b0

◆ GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_ENABLE

#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_ENABLE   0b1

◆ GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_OFFSET

#define GPUPLL_GATE_EN_REG_GPUPLL_GATE_SW_CFG_OFFSET   16

◆ GPUPLL_GATE_STAT_REG

#define GPUPLL_GATE_STAT_REG   0x00001994

◆ GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_CLEAR_MASK

#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_CLEAR_MASK   0x00010000

◆ GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_DISABLE

#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_DISABLE   0b0

◆ GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_ENABLE

#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_ENABLE   0b1

◆ GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_OFFSET

#define GPUPLL_GATE_STAT_REG_GPUPLL_GATE_STAT_OFFSET   16

◆ HSI_AXI_CLK_REG

#define HSI_AXI_CLK_REG   0x000013e0

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_OFFSET

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b11

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b10

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b01

◆ HSI_AXI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define HSI_AXI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ HSI_AXI_CLK_REG_FACTOR_M_CLEAR_MASK

#define HSI_AXI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ HSI_AXI_CLK_REG_FACTOR_M_OFFSET

#define HSI_AXI_CLK_REG_FACTOR_M_OFFSET   0

◆ HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLEAR_MASK

#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLEAR_MASK   0x80000000

◆ HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_OFF

#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_ON

#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_CLOCK_IS_ON   0b1

◆ HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_OFFSET

#define HSI_AXI_CLK_REG_HSI_AXI_CLK_GATING_OFFSET   31

◆ HSI_COMB0_PHY_CFG_CLK_REG

#define HSI_COMB0_PHY_CFG_CLK_REG   0x000013c0

◆ HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET

#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b1

◆ HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define HSI_COMB0_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b0

◆ HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK

#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_OFFSET

#define HSI_COMB0_PHY_CFG_CLK_REG_FACTOR_M_OFFSET   0

◆ HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLEAR_MASK

#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLEAR_MASK   0x80000000

◆ HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_OFF

#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_ON

#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_CLOCK_IS_ON   0b1

◆ HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_OFFSET

#define HSI_COMB0_PHY_CFG_CLK_REG_HSI_COMB0_PHY_CFG_CLK_GATING_OFFSET   31

◆ HSI_COMB0_PHY_REF_CLK_REG

#define HSI_COMB0_PHY_REF_CLK_REG   0x000013c4

◆ HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET

#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define HSI_COMB0_PHY_REF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK

#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_OFFSET

#define HSI_COMB0_PHY_REF_CLK_REG_FACTOR_M_OFFSET   0

◆ HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLEAR_MASK

#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000

◆ HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_OFF

#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_ON

#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1

◆ HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_OFFSET

#define HSI_COMB0_PHY_REF_CLK_REG_HSI_COMB0_PHY_REF_CLK_GATING_OFFSET   31

◆ HSI_SYS_GAR_REG

#define HSI_SYS_GAR_REG   0x000013cc

◆ HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_CLEAR_MASK

#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_MASK

#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_MASK   0b0

◆ HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_OFFSET

#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_OFFSET   0

◆ HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_PASS

#define HSI_SYS_GAR_REG_HSI_AHB_CLK_EN_PASS   0b1

◆ HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_CLEAR_MASK

#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_CLEAR_MASK   0x00000002

◆ HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_MASK

#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_MASK   0b0

◆ HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_OFFSET

#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_OFFSET   1

◆ HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_PASS

#define HSI_SYS_GAR_REG_HSI_AXI_CLK_EN_PASS   0b1

◆ HSI_SYS_GAR_REG_HSI_SYS_RST_N_ASSERT

#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_ASSERT   0b0

◆ HSI_SYS_GAR_REG_HSI_SYS_RST_N_CLEAR_MASK

#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_CLEAR_MASK   0x00010000

◆ HSI_SYS_GAR_REG_HSI_SYS_RST_N_DE_ASSERT

#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_DE_ASSERT   0b1

◆ HSI_SYS_GAR_REG_HSI_SYS_RST_N_OFFSET

#define HSI_SYS_GAR_REG_HSI_SYS_RST_N_OFFSET   16

◆ I2S0_CLK_REG

#define I2S0_CLK_REG   0x00001200

◆ I2S0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ I2S0_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2S0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2S0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2S0_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ I2S0_CLK_REG_FACTOR_M_OFFSET

#define I2S0_CLK_REG_FACTOR_M_OFFSET   0

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK   0x80000000

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET

#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET   31

◆ I2S0_GAR_REG

#define I2S0_GAR_REG   0x0000120c

◆ I2S0_GAR_REG_I2S0_APB_CLK_EN_CLEAR_MASK

#define I2S0_GAR_REG_I2S0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ I2S0_GAR_REG_I2S0_APB_CLK_EN_MASK

#define I2S0_GAR_REG_I2S0_APB_CLK_EN_MASK   0x0

◆ I2S0_GAR_REG_I2S0_APB_CLK_EN_OFFSET

#define I2S0_GAR_REG_I2S0_APB_CLK_EN_OFFSET   0

◆ I2S0_GAR_REG_I2S0_APB_CLK_EN_PASS

#define I2S0_GAR_REG_I2S0_APB_CLK_EN_PASS   0b1

◆ I2S0_GAR_REG_I2S0_RST_N_ASSERT

#define I2S0_GAR_REG_I2S0_RST_N_ASSERT   0b0

◆ I2S0_GAR_REG_I2S0_RST_N_CLEAR_MASK

#define I2S0_GAR_REG_I2S0_RST_N_CLEAR_MASK   0x00010000

◆ I2S0_GAR_REG_I2S0_RST_N_DE_ASSERT

#define I2S0_GAR_REG_I2S0_RST_N_DE_ASSERT   0b1

◆ I2S0_GAR_REG_I2S0_RST_N_OFFSET

#define I2S0_GAR_REG_I2S0_RST_N_OFFSET   16

◆ I2S1_CLK_REG

#define I2S1_CLK_REG   0x00001210

◆ I2S1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define I2S1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ I2S1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2S1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ I2S1_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2S1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2S1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2S1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2S1_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2S1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ I2S1_CLK_REG_FACTOR_M_OFFSET

#define I2S1_CLK_REG_FACTOR_M_OFFSET   0

◆ I2S1_CLK_REG_I2S1_CLK_GATING_CLEAR_MASK

#define I2S1_CLK_REG_I2S1_CLK_GATING_CLEAR_MASK   0x80000000

◆ I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_OFF

#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_ON

#define I2S1_CLK_REG_I2S1_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2S1_CLK_REG_I2S1_CLK_GATING_OFFSET

#define I2S1_CLK_REG_I2S1_CLK_GATING_OFFSET   31

◆ I2S1_GAR_REG

#define I2S1_GAR_REG   0x0000121c

◆ I2S1_GAR_REG_I2S1_APB_CLK_EN_CLEAR_MASK

#define I2S1_GAR_REG_I2S1_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ I2S1_GAR_REG_I2S1_APB_CLK_EN_MASK

#define I2S1_GAR_REG_I2S1_APB_CLK_EN_MASK   0x0

◆ I2S1_GAR_REG_I2S1_APB_CLK_EN_OFFSET

#define I2S1_GAR_REG_I2S1_APB_CLK_EN_OFFSET   0

◆ I2S1_GAR_REG_I2S1_APB_CLK_EN_PASS

#define I2S1_GAR_REG_I2S1_APB_CLK_EN_PASS   0b1

◆ I2S1_GAR_REG_I2S1_RST_N_ASSERT

#define I2S1_GAR_REG_I2S1_RST_N_ASSERT   0b0

◆ I2S1_GAR_REG_I2S1_RST_N_CLEAR_MASK

#define I2S1_GAR_REG_I2S1_RST_N_CLEAR_MASK   0x00010000

◆ I2S1_GAR_REG_I2S1_RST_N_DE_ASSERT

#define I2S1_GAR_REG_I2S1_RST_N_DE_ASSERT   0b1

◆ I2S1_GAR_REG_I2S1_RST_N_OFFSET

#define I2S1_GAR_REG_I2S1_RST_N_OFFSET   16

◆ I2S2_CLK_REG

#define I2S2_CLK_REG   0x00001220

◆ I2S2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define I2S2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ I2S2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2S2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ I2S2_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2S2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2S2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2S2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2S2_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2S2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ I2S2_CLK_REG_FACTOR_M_OFFSET

#define I2S2_CLK_REG_FACTOR_M_OFFSET   0

◆ I2S2_CLK_REG_I2S2_CLK_GATING_CLEAR_MASK

#define I2S2_CLK_REG_I2S2_CLK_GATING_CLEAR_MASK   0x80000000

◆ I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_OFF

#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_ON

#define I2S2_CLK_REG_I2S2_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2S2_CLK_REG_I2S2_CLK_GATING_OFFSET

#define I2S2_CLK_REG_I2S2_CLK_GATING_OFFSET   31

◆ I2S2_GAR_REG

#define I2S2_GAR_REG   0x0000122c

◆ I2S2_GAR_REG_I2S2_APB_CLK_EN_CLEAR_MASK

#define I2S2_GAR_REG_I2S2_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ I2S2_GAR_REG_I2S2_APB_CLK_EN_MASK

#define I2S2_GAR_REG_I2S2_APB_CLK_EN_MASK   0x0

◆ I2S2_GAR_REG_I2S2_APB_CLK_EN_OFFSET

#define I2S2_GAR_REG_I2S2_APB_CLK_EN_OFFSET   0

◆ I2S2_GAR_REG_I2S2_APB_CLK_EN_PASS

#define I2S2_GAR_REG_I2S2_APB_CLK_EN_PASS   0b1

◆ I2S2_GAR_REG_I2S2_RST_N_ASSERT

#define I2S2_GAR_REG_I2S2_RST_N_ASSERT   0b0

◆ I2S2_GAR_REG_I2S2_RST_N_CLEAR_MASK

#define I2S2_GAR_REG_I2S2_RST_N_CLEAR_MASK   0x00010000

◆ I2S2_GAR_REG_I2S2_RST_N_DE_ASSERT

#define I2S2_GAR_REG_I2S2_RST_N_DE_ASSERT   0b1

◆ I2S2_GAR_REG_I2S2_RST_N_OFFSET

#define I2S2_GAR_REG_I2S2_RST_N_OFFSET   16

◆ I2S3_CLK_REG

#define I2S3_CLK_REG   0x00001230

◆ I2S3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define I2S3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ I2S3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2S3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ I2S3_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2S3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2S3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2S3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2S3_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2S3_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ I2S3_CLK_REG_FACTOR_M_OFFSET

#define I2S3_CLK_REG_FACTOR_M_OFFSET   0

◆ I2S3_CLK_REG_I2S3_CLK_GATING_CLEAR_MASK

#define I2S3_CLK_REG_I2S3_CLK_GATING_CLEAR_MASK   0x80000000

◆ I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_OFF

#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_ON

#define I2S3_CLK_REG_I2S3_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2S3_CLK_REG_I2S3_CLK_GATING_OFFSET

#define I2S3_CLK_REG_I2S3_CLK_GATING_OFFSET   31

◆ I2S3_GAR_REG

#define I2S3_GAR_REG   0x0000123c

◆ I2S3_GAR_REG_I2S3_APB_CLK_EN_CLEAR_MASK

#define I2S3_GAR_REG_I2S3_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ I2S3_GAR_REG_I2S3_APB_CLK_EN_MASK

#define I2S3_GAR_REG_I2S3_APB_CLK_EN_MASK   0x0

◆ I2S3_GAR_REG_I2S3_APB_CLK_EN_OFFSET

#define I2S3_GAR_REG_I2S3_APB_CLK_EN_OFFSET   0

◆ I2S3_GAR_REG_I2S3_APB_CLK_EN_PASS

#define I2S3_GAR_REG_I2S3_APB_CLK_EN_PASS   0b1

◆ I2S3_GAR_REG_I2S3_RST_N_ASSERT

#define I2S3_GAR_REG_I2S3_RST_N_ASSERT   0b0

◆ I2S3_GAR_REG_I2S3_RST_N_CLEAR_MASK

#define I2S3_GAR_REG_I2S3_RST_N_CLEAR_MASK   0x00010000

◆ I2S3_GAR_REG_I2S3_RST_N_DE_ASSERT

#define I2S3_GAR_REG_I2S3_RST_N_DE_ASSERT   0b1

◆ I2S3_GAR_REG_I2S3_RST_N_OFFSET

#define I2S3_GAR_REG_I2S3_RST_N_OFFSET   16

◆ IOMMU_GAR_REG

#define IOMMU_GAR_REG   0x0000058c

◆ IOMMU_GAR_REG_IOMMU_APB_CLK_EN_CLEAR_MASK

#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ IOMMU_GAR_REG_IOMMU_APB_CLK_EN_MASK

#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_MASK   0x0

◆ IOMMU_GAR_REG_IOMMU_APB_CLK_EN_OFFSET

#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_OFFSET   0

◆ IOMMU_GAR_REG_IOMMU_APB_CLK_EN_PASS

#define IOMMU_GAR_REG_IOMMU_APB_CLK_EN_PASS   0b1

◆ IR_RX0_CLK_REG

#define IR_RX0_CLK_REG   0x00001000

◆ IR_RX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IR_RX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ IR_RX0_CLK_REG_CLK_SRC_SEL_OFFSET

#define IR_RX0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b001

◆ IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define IR_RX0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b000

◆ IR_RX0_CLK_REG_FACTOR_M_CLEAR_MASK

#define IR_RX0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ IR_RX0_CLK_REG_FACTOR_M_OFFSET

#define IR_RX0_CLK_REG_FACTOR_M_OFFSET   0

◆ IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLEAR_MASK

#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLEAR_MASK   0x80000000

◆ IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_OFF

#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_ON

#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_CLOCK_IS_ON   0b1

◆ IR_RX0_CLK_REG_IR_RX0_CLK_GATING_OFFSET

#define IR_RX0_CLK_REG_IR_RX0_CLK_GATING_OFFSET   31

◆ IR_RX0_GAR_REG

#define IR_RX0_GAR_REG   0x00001004

◆ IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_CLEAR_MASK

#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_MASK

#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_MASK   0x0

◆ IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_OFFSET

#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_OFFSET   0

◆ IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_PASS

#define IR_RX0_GAR_REG_IR_RX0_APB_CLK_EN_PASS   0b1

◆ IR_RX0_GAR_REG_IR_RX0_RST_N_ASSERT

#define IR_RX0_GAR_REG_IR_RX0_RST_N_ASSERT   0b0

◆ IR_RX0_GAR_REG_IR_RX0_RST_N_CLEAR_MASK

#define IR_RX0_GAR_REG_IR_RX0_RST_N_CLEAR_MASK   0x00010000

◆ IR_RX0_GAR_REG_IR_RX0_RST_N_DE_ASSERT

#define IR_RX0_GAR_REG_IR_RX0_RST_N_DE_ASSERT   0b1

◆ IR_RX0_GAR_REG_IR_RX0_RST_N_OFFSET

#define IR_RX0_GAR_REG_IR_RX0_RST_N_OFFSET   16

◆ IR_TX_CLK_REG

#define IR_TX_CLK_REG   0x00001008

◆ IR_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IR_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ IR_TX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IR_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IR_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define IR_TX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b1

◆ IR_TX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define IR_TX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0

◆ IR_TX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IR_TX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ IR_TX_CLK_REG_FACTOR_M_OFFSET

#define IR_TX_CLK_REG_FACTOR_M_OFFSET   0

◆ IR_TX_CLK_REG_IR_TX_CLK_GATING_CLEAR_MASK

#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLEAR_MASK   0x80000000

◆ IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_OFF

#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_ON

#define IR_TX_CLK_REG_IR_TX_CLK_GATING_CLOCK_IS_ON   0b1

◆ IR_TX_CLK_REG_IR_TX_CLK_GATING_OFFSET

#define IR_TX_CLK_REG_IR_TX_CLK_GATING_OFFSET   31

◆ IR_TX_GAR_REG

#define IR_TX_GAR_REG   0x0000100c

◆ IR_TX_GAR_REG_IR_TX_APB_CLK_EN_CLEAR_MASK

#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ IR_TX_GAR_REG_IR_TX_APB_CLK_EN_MASK

#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_MASK   0x0

◆ IR_TX_GAR_REG_IR_TX_APB_CLK_EN_OFFSET

#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_OFFSET   0

◆ IR_TX_GAR_REG_IR_TX_APB_CLK_EN_PASS

#define IR_TX_GAR_REG_IR_TX_APB_CLK_EN_PASS   0b1

◆ IR_TX_GAR_REG_IR_TX_RST_N_ASSERT

#define IR_TX_GAR_REG_IR_TX_RST_N_ASSERT   0b0

◆ IR_TX_GAR_REG_IR_TX_RST_N_CLEAR_MASK

#define IR_TX_GAR_REG_IR_TX_RST_N_CLEAR_MASK   0x00010000

◆ IR_TX_GAR_REG_IR_TX_RST_N_DE_ASSERT

#define IR_TX_GAR_REG_IR_TX_RST_N_DE_ASSERT   0b1

◆ IR_TX_GAR_REG_IR_TX_RST_N_OFFSET

#define IR_TX_GAR_REG_IR_TX_RST_N_OFFSET   16

◆ ISP_CLK_REG

#define ISP_CLK_REG   0x00001860

◆ ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ ISP_CLK_REG_CLK_SRC_SEL_OFFSET

#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ ISP_CLK_REG_CLK_SRC_SEL_VEPLL

#define ISP_CLK_REG_CLK_SRC_SEL_VEPLL   0b111

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b001

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000

◆ ISP_CLK_REG_FACTOR_M_CLEAR_MASK

#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ ISP_CLK_REG_FACTOR_M_OFFSET

#define ISP_CLK_REG_FACTOR_M_OFFSET   0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK

#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   0x80000000

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0b0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0b1

◆ ISP_CLK_REG_ISP_CLK_GATING_OFFSET

#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31

◆ LEDC_CLK_REG

#define LEDC_CLK_REG   0x00001700

◆ LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ LEDC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b1

◆ LEDC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0

◆ LEDC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ LEDC_CLK_REG_FACTOR_M_OFFSET

#define LEDC_CLK_REG_FACTOR_M_OFFSET   0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   0x80000000

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0b1

◆ LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET

#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31

◆ LEDC_GAR_REG

#define LEDC_GAR_REG   0x00001704

◆ LEDC_GAR_REG_LEDC_APB_CLK_EN_CLEAR_MASK

#define LEDC_GAR_REG_LEDC_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ LEDC_GAR_REG_LEDC_APB_CLK_EN_MASK

#define LEDC_GAR_REG_LEDC_APB_CLK_EN_MASK   0b0

◆ LEDC_GAR_REG_LEDC_APB_CLK_EN_OFFSET

#define LEDC_GAR_REG_LEDC_APB_CLK_EN_OFFSET   0

◆ LEDC_GAR_REG_LEDC_APB_CLK_EN_PASS

#define LEDC_GAR_REG_LEDC_APB_CLK_EN_PASS   0b1

◆ LEDC_GAR_REG_LEDC_RST_N_ASSERT

#define LEDC_GAR_REG_LEDC_RST_N_ASSERT   0b0

◆ LEDC_GAR_REG_LEDC_RST_N_CLEAR_MASK

#define LEDC_GAR_REG_LEDC_RST_N_CLEAR_MASK   0x00010000

◆ LEDC_GAR_REG_LEDC_RST_N_DE_ASSERT

#define LEDC_GAR_REG_LEDC_RST_N_DE_ASSERT   0b1

◆ LEDC_GAR_REG_LEDC_RST_N_OFFSET

#define LEDC_GAR_REG_LEDC_RST_N_OFFSET   16

◆ LVDS0_GAR_REG

#define LVDS0_GAR_REG   0x00001544

◆ LVDS0_GAR_REG_LVDS0_RST_N_ASSERT

#define LVDS0_GAR_REG_LVDS0_RST_N_ASSERT   0b0

◆ LVDS0_GAR_REG_LVDS0_RST_N_CLEAR_MASK

#define LVDS0_GAR_REG_LVDS0_RST_N_CLEAR_MASK   0x00010000

◆ LVDS0_GAR_REG_LVDS0_RST_N_DE_ASSERT

#define LVDS0_GAR_REG_LVDS0_RST_N_DE_ASSERT   0b1

◆ LVDS0_GAR_REG_LVDS0_RST_N_OFFSET

#define LVDS0_GAR_REG_LVDS0_RST_N_OFFSET   16

◆ MBUS_CLK_GATE_EN_REG

#define MBUS_CLK_GATE_EN_REG   0x000005e4

◆ MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_CLEAR_MASK   0x00000004

◆ MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET   2

◆ MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_SECURE_DEBUG

#define MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_SECURE_DEBUG   0b1

◆ MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_CLEAR_MASK   0x00000100

◆ MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_OFFSET   8

◆ MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_PASS

#define MBUS_CLK_GATE_EN_REG_CSI_MBUS_CLK_EN_PASS   0b1

◆ MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_CLEAR_MASK   0x00000001

◆ MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_OFFSET   0

◆ MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_PASS

#define MBUS_CLK_GATE_EN_REG_DMA0_MBUS_CLK_EN_PASS   0b1

◆ MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_CLEAR_MASK   0x00000800

◆ MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_OFFSET   11

◆ MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_PASS

#define MBUS_CLK_GATE_EN_REG_GMAC0_AXI_CLK_EN_PASS   0b1

◆ MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_CLEAR_MASK   0x00000200

◆ MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_OFFSET   9

◆ MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_PASS

#define MBUS_CLK_GATE_EN_REG_ISP_MBUS_CLK_EN_PASS   0b1

◆ MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_CLEAR_MASK

#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_CLEAR_MASK   0x00000002

◆ MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_MASK

#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_MASK   0x0

◆ MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_OFFSET

#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_OFFSET   1

◆ MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_PASS

#define MBUS_CLK_GATE_EN_REG_VE0_MBUS_CLK_EN_PASS   0b1

◆ MBUS_CLK_REG

#define MBUS_CLK_REG   0x00000588

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK   0x80000000

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF   0b0

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON   0b1

◆ MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET   31

◆ MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK   0x07000000

◆ MBUS_CLK_REG_MBUS_CLK_SEL_HDR_CLK

#define MBUS_CLK_REG_MBUS_CLK_SEL_HDR_CLK   0b100

◆ MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET   24

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M   0b011

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M   0b010

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS   0b001

◆ MBUS_CLK_REG_MBUS_CLK_SEL_SYS_24M_CLK

#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_24M_CLK   0b000

◆ MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK   0x10000000

◆ MBUS_CLK_REG_MBUS_DFS_EN_DISABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE   0b0

◆ MBUS_CLK_REG_MBUS_DFS_EN_ENABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE   0b1

◆ MBUS_CLK_REG_MBUS_DFS_EN_OFFSET

#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET   28

◆ MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK   0x0000001f

◆ MBUS_CLK_REG_MBUS_DIV1_OFFSET

#define MBUS_CLK_REG_MBUS_DIV1_OFFSET   0

◆ MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK   0x08000000

◆ MBUS_CLK_REG_MBUS_UPD_INVALID

#define MBUS_CLK_REG_MBUS_UPD_INVALID   0b0

◆ MBUS_CLK_REG_MBUS_UPD_OFFSET

#define MBUS_CLK_REG_MBUS_UPD_OFFSET   27

◆ MBUS_CLK_REG_MBUS_UPD_VALID

#define MBUS_CLK_REG_MBUS_UPD_VALID   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG

#define MBUS_MAT_CLK_GATE_EN_REG   0x000005e0

◆ MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_CLEAR_MASK   0x00000100

◆ MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET   8

◆ MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000020

◆ MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_DE_SYS_MBUS_GATE_SW_CFG_OFFSET   5

◆ MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_CLEAR_MASK   0x10000000

◆ MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_DMA0_MBUS_GATE_SW_CFG_OFFSET   28

◆ MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_CLEAR_MASK   0x00000080

◆ MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_GPU_AXI_GATE_SW_CFG_OFFSET   7

◆ MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000002

◆ MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_VE0_MBUS_GATE_SW_CFG_OFFSET   1

◆ MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00000004

◆ MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATE_EN_REG_VIDEO_IN_MBUS_GATE_SW_CFG_OFFSET   2

◆ MIPI_DSI00_CLK_REG

#define MIPI_DSI00_CLK_REG   0x00001580

◆ MIPI_DSI00_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ MIPI_DSI00_CLK_REG_CLK_SRC_SEL_OFFSET

#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010

◆ MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ MIPI_DSI00_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define MIPI_DSI00_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ MIPI_DSI00_CLK_REG_FACTOR_M_CLEAR_MASK

#define MIPI_DSI00_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ MIPI_DSI00_CLK_REG_FACTOR_M_OFFSET

#define MIPI_DSI00_CLK_REG_FACTOR_M_OFFSET   0

◆ MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLEAR_MASK

#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLEAR_MASK   0x80000000

◆ MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_OFF

#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_ON

#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_CLOCK_IS_ON   0b1

◆ MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_OFFSET

#define MIPI_DSI00_CLK_REG_MIPI_DSI0_CLK_GATING_OFFSET   31

◆ MIPI_DSI00_GAR_REG

#define MIPI_DSI00_GAR_REG   0x00001584

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_CLEAR_MASK

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_MASK

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_MASK   0b0

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_OFFSET

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_OFFSET   0

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_PASS

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_AHB_CLK_EN_PASS   0b1

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_ASSERT

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_ASSERT   0b0

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_CLEAR_MASK

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_CLEAR_MASK   0x00010000

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_DE_ASSERT

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_DE_ASSERT   0b1

◆ MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_OFFSET

#define MIPI_DSI00_GAR_REG_MIPI_DSI0_RST_N_OFFSET   16

◆ MSGBOX_CPUS_GAR_REG

#define MSGBOX_CPUS_GAR_REG   0x0000074c

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_CLEAR_MASK

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_MASK

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_MASK   0x0

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_OFFSET

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_OFFSET   0

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_PASS

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_AHB_CLK_EN_PASS   0b1

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_ASSERT

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_ASSERT   0b0

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_CLEAR_MASK

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_CLEAR_MASK   0x00010000

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_DE_ASSERT

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_DE_ASSERT   0b1

◆ MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_OFFSET

#define MSGBOX_CPUS_GAR_REG_MSGBOX_CPUS_RST_N_OFFSET   16

◆ MSGBOX_CPUX_GAR_REG

#define MSGBOX_CPUX_GAR_REG   0x00000744

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_CLEAR_MASK

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_MASK

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_MASK   0x0

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_OFFSET

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_OFFSET   0

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_PASS

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_AHB_CLK_EN_PASS   0b1

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_ASSERT

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_ASSERT   0b0

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_CLEAR_MASK

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_CLEAR_MASK   0x00010000

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_DE_ASSERT

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_DE_ASSERT   0b1

◆ MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_OFFSET

#define MSGBOX_CPUX_GAR_REG_MSGBOX_CPUX_RST_N_OFFSET   16

◆ NSI_CLK_REG

#define NSI_CLK_REG   0x00000580

◆ NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK   0x80000000

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON   0b1

◆ NSI_CLK_REG_NSI_CLK_GATING_OFFSET

#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET   31

◆ NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK   0x07000000

◆ NSI_CLK_REG_NSI_CLK_SEL_HDR_CLK

#define NSI_CLK_REG_NSI_CLK_SEL_HDR_CLK   0b101

◆ NSI_CLK_REG_NSI_CLK_SEL_OFFSET

#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET   24

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M   0b100

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M   0b011

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS   0b010

◆ NSI_CLK_REG_NSI_CLK_SEL_SYS_24M_CLK

#define NSI_CLK_REG_NSI_CLK_SEL_SYS_24M_CLK   0b000

◆ NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL3X

#define NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL3X   0b001

◆ NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK

#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK   0x10000000

◆ NSI_CLK_REG_NSI_DFS_EN_DISABLE

#define NSI_CLK_REG_NSI_DFS_EN_DISABLE   0b0

◆ NSI_CLK_REG_NSI_DFS_EN_ENABLE

#define NSI_CLK_REG_NSI_DFS_EN_ENABLE   0b1

◆ NSI_CLK_REG_NSI_DFS_EN_OFFSET

#define NSI_CLK_REG_NSI_DFS_EN_OFFSET   28

◆ NSI_CLK_REG_NSI_DIV1_CLEAR_MASK

#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK   0x0000001f

◆ NSI_CLK_REG_NSI_DIV1_OFFSET

#define NSI_CLK_REG_NSI_DIV1_OFFSET   0

◆ NSI_CLK_REG_NSI_UPD_CLEAR_MASK

#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK   0x08000000

◆ NSI_CLK_REG_NSI_UPD_INVALID

#define NSI_CLK_REG_NSI_UPD_INVALID   0b0

◆ NSI_CLK_REG_NSI_UPD_OFFSET

#define NSI_CLK_REG_NSI_UPD_OFFSET   27

◆ NSI_CLK_REG_NSI_UPD_VALID

#define NSI_CLK_REG_NSI_UPD_VALID   0b1

◆ NSI_GAR_REG

#define NSI_GAR_REG   0x00000584

◆ NSI_GAR_REG_NSI_CFG_CLK_EN_CLEAR_MASK

#define NSI_GAR_REG_NSI_CFG_CLK_EN_CLEAR_MASK   0x00000001

◆ NSI_GAR_REG_NSI_CFG_CLK_EN_MASK

#define NSI_GAR_REG_NSI_CFG_CLK_EN_MASK   0x0

◆ NSI_GAR_REG_NSI_CFG_CLK_EN_OFFSET

#define NSI_GAR_REG_NSI_CFG_CLK_EN_OFFSET   0

◆ NSI_GAR_REG_NSI_CFG_CLK_EN_PASS

#define NSI_GAR_REG_NSI_CFG_CLK_EN_PASS   0b1

◆ NSI_GAR_REG_NSI_CFG_RST_N_ASSERT

#define NSI_GAR_REG_NSI_CFG_RST_N_ASSERT   0b0

◆ NSI_GAR_REG_NSI_CFG_RST_N_CLEAR_MASK

#define NSI_GAR_REG_NSI_CFG_RST_N_CLEAR_MASK   0x00020000

◆ NSI_GAR_REG_NSI_CFG_RST_N_DE_ASSERT

#define NSI_GAR_REG_NSI_CFG_RST_N_DE_ASSERT   0b1

◆ NSI_GAR_REG_NSI_CFG_RST_N_OFFSET

#define NSI_GAR_REG_NSI_CFG_RST_N_OFFSET   17

◆ NSI_GAR_REG_NSI_RST_N_ASSERT

#define NSI_GAR_REG_NSI_RST_N_ASSERT   0b0

◆ NSI_GAR_REG_NSI_RST_N_CLEAR_MASK

#define NSI_GAR_REG_NSI_RST_N_CLEAR_MASK   0x00010000

◆ NSI_GAR_REG_NSI_RST_N_DE_ASSERT

#define NSI_GAR_REG_NSI_RST_N_DE_ASSERT   0b1

◆ NSI_GAR_REG_NSI_RST_N_OFFSET

#define NSI_GAR_REG_NSI_RST_N_OFFSET   16

◆ OWA0_GAR_REG

#define OWA0_GAR_REG   0x0000128c

◆ OWA0_GAR_REG_OWA0_APB_CLK_EN_CLEAR_MASK

#define OWA0_GAR_REG_OWA0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ OWA0_GAR_REG_OWA0_APB_CLK_EN_MASK

#define OWA0_GAR_REG_OWA0_APB_CLK_EN_MASK   0b0

◆ OWA0_GAR_REG_OWA0_APB_CLK_EN_OFFSET

#define OWA0_GAR_REG_OWA0_APB_CLK_EN_OFFSET   0

◆ OWA0_GAR_REG_OWA0_APB_CLK_EN_PASS

#define OWA0_GAR_REG_OWA0_APB_CLK_EN_PASS   0b1

◆ OWA0_GAR_REG_OWA0_RST_N_ASSERT

#define OWA0_GAR_REG_OWA0_RST_N_ASSERT   0b0

◆ OWA0_GAR_REG_OWA0_RST_N_CLEAR_MASK

#define OWA0_GAR_REG_OWA0_RST_N_CLEAR_MASK   0x00010000

◆ OWA0_GAR_REG_OWA0_RST_N_DE_ASSERT

#define OWA0_GAR_REG_OWA0_RST_N_DE_ASSERT   0b1

◆ OWA0_GAR_REG_OWA0_RST_N_OFFSET

#define OWA0_GAR_REG_OWA0_RST_N_OFFSET   16

◆ OWA0_RX_CLK_REG

#define OWA0_RX_CLK_REG   0x00001284

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b010

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b011

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b100

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_OFFSET

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define OWA0_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b000

◆ OWA0_RX_CLK_REG_FACTOR_M_CLEAR_MASK

#define OWA0_RX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ OWA0_RX_CLK_REG_FACTOR_M_OFFSET

#define OWA0_RX_CLK_REG_FACTOR_M_OFFSET   0

◆ OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLEAR_MASK

#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLEAR_MASK   0x80000000

◆ OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_OFF

#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_ON

#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_CLOCK_IS_ON   0b1

◆ OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_OFFSET

#define OWA0_RX_CLK_REG_OWA0_RX_CLK_GATING_OFFSET   31

◆ OWA0_TX_CLK_REG

#define OWA0_TX_CLK_REG   0x00001280

◆ OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL

#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL   0b000

◆ OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X

#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL2X   0b001

◆ OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X

#define OWA0_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL5X   0b010

◆ OWA0_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define OWA0_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ OWA0_TX_CLK_REG_CLK_SRC_SEL_OFFSET

#define OWA0_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ OWA0_TX_CLK_REG_FACTOR_M_CLEAR_MASK

#define OWA0_TX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ OWA0_TX_CLK_REG_FACTOR_M_OFFSET

#define OWA0_TX_CLK_REG_FACTOR_M_OFFSET   0

◆ OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLEAR_MASK

#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLEAR_MASK   0x80000000

◆ OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_OFF

#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_ON

#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_CLOCK_IS_ON   0b1

◆ OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_OFFSET

#define OWA0_TX_CLK_REG_OWA0_TX_CLK_GATING_OFFSET   31

◆ PCIe0_AUX_CLK_REG

#define PCIe0_AUX_CLK_REG   0x00001380

◆ PCIe0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ PCIe0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b0

◆ PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define PCIe0_AUX_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b1

◆ PCIe0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIe0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ PCIe0_AUX_CLK_REG_FACTOR_M_OFFSET

#define PCIe0_AUX_CLK_REG_FACTOR_M_OFFSET   0

◆ PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK

#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK   0x80000000

◆ PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF

#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON

#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON   0b1

◆ PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET

#define PCIe0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET   31

◆ PCIe0_AXI_S_CLK_REG

#define PCIe0_AXI_S_CLK_REG   0x00001384

◆ PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b1

◆ PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define PCIe0_AXI_S_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b0

◆ PCIe0_AXI_S_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIe0_AXI_S_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ PCIe0_AXI_S_CLK_REG_FACTOR_M_OFFSET

#define PCIe0_AXI_S_CLK_REG_FACTOR_M_OFFSET   0

◆ PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLEAR_MASK

#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLEAR_MASK   0x80000000

◆ PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_OFF

#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_ON

#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_CLOCK_IS_ON   0b1

◆ PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_OFFSET

#define PCIe0_AXI_S_CLK_REG_PCIE0_AXI_S_CLK_GATING_OFFSET   31

◆ PCIe0_GAR_REG

#define PCIe0_GAR_REG   0x0000138c

◆ PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_ASSERT

#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_ASSERT   0b0

◆ PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_CLEAR_MASK

#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_CLEAR_MASK   0x00010000

◆ PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_DE_ASSERT

#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_DE_ASSERT   0b1

◆ PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_OFFSET

#define PCIe0_GAR_REG_PCIE0_PWR_UP_RST_N_OFFSET   16

◆ PCIe0_GAR_REG_PCIE0_RST_N_ASSERT

#define PCIe0_GAR_REG_PCIE0_RST_N_ASSERT   0b0

◆ PCIe0_GAR_REG_PCIE0_RST_N_CLEAR_MASK

#define PCIe0_GAR_REG_PCIE0_RST_N_CLEAR_MASK   0x00020000

◆ PCIe0_GAR_REG_PCIE0_RST_N_DE_ASSERT

#define PCIe0_GAR_REG_PCIE0_RST_N_DE_ASSERT   0b1

◆ PCIe0_GAR_REG_PCIE0_RST_N_OFFSET

#define PCIe0_GAR_REG_PCIE0_RST_N_OFFSET   17

◆ PERI0PLL_GATE_EN_REG

#define PERI0PLL_GATE_EN_REG   0x00001908

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_CLEAR_MASK   0x80000000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_STBY_GATE_EN_OFFSET   31

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27

◆ PERI0PLL_GATE_STAT_REG

#define PERI0PLL_GATE_STAT_REG   0x00001988

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK   0x00080000

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET   19

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK   0x00400000

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET   22

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK   0x00010000

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET   16

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET   21

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK   0x00100000

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET   20

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET   18

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK   0x00020000

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET   17

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET   24

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK   0x00800000

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET   23

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK   0x02000000

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET   25

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK   0x04000000

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET   26

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK   0x08000000

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET   27

◆ PERI1PLL_GATE_EN_REG

#define PERI1PLL_GATE_EN_REG   0x0000190c

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET   3

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET   19

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET   6

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET   22

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET   0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET   16

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET   4

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET   21

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET   20

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_CLEAR_MASK   0x80000000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_STBY_GATE_EN_OFFSET   31

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET   1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET   18

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET   17

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET   7

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET   24

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET   23

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000400

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET   10

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET   9

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK   0x04000000

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET   26

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET   25

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000800

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET   11

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK   0x08000000

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET   27

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00001000

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_AUTO_GATE_EN_OFFSET   12

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_CLEAR_MASK   0x10000000

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1PLL2X_GATE_SW_CFG_OFFSET   28

◆ PERI1PLL_GATE_STAT_REG

#define PERI1PLL_GATE_STAT_REG   0x0000198c

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK   0x00080000

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET   19

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK   0x00400000

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET   22

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK   0x00010000

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET   16

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET   21

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK   0x00100000

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET   20

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET   18

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK   0x00020000

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET   17

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET   24

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK   0x00800000

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET   23

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK   0x04000000

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET   26

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK   0x02000000

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET   25

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK   0x08000000

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET   27

◆ PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_CLEAR_MASK   0x10000000

◆ PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1PLL2X_GATE_STAT_OFFSET   28

◆ PLL_AUDIO0_BIAS_REG

#define PLL_AUDIO0_BIAS_REG   0x00000270

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO0_CTRL_REG

#define PLL_AUDIO0_CTRL_REG   0x00000260

◆ PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK   0x003f0000

◆ PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET   16

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO0_PAT0_CTRL_REG

#define PLL_AUDIO0_PAT0_CTRL_REG   0x00000268

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO0_PAT1_CTRL_REG

#define PLL_AUDIO0_PAT1_CTRL_REG   0x0000026c

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_AUDIO1_BIAS_REG

#define PLL_AUDIO1_BIAS_REG   0x00000290

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO1_CTRL_REG

#define PLL_AUDIO1_CTRL_REG   0x00000280

◆ PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000

◆ PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET   16

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO1_PAT0_CTRL_REG

#define PLL_AUDIO1_PAT0_CTRL_REG   0x00000288

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO1_PAT1_CTRL_REG

#define PLL_AUDIO1_PAT1_CTRL_REG   0x0000028c

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_CFG0_REG

#define PLL_CFG0_REG   0x00001f20

◆ PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK

#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   0xffffffff

◆ PLL_CFG0_REG_PLL_CONFIG0_OFFSET

#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0

◆ PLL_CFG1_REG

#define PLL_CFG1_REG   0x00001f24

◆ PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK

#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   0xffffffff

◆ PLL_CFG1_REG_PLL_CONFIG1_OFFSET

#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0

◆ PLL_CFG2_REG

#define PLL_CFG2_REG   0x00001f28

◆ PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK

#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   0xffffffff

◆ PLL_CFG2_REG_PLL_CONFIG2_OFFSET

#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0

◆ PLL_FO0_EN_REG

#define PLL_FO0_EN_REG   0x00001a10

◆ PLL_FO0_EN_REG_PERI1PLL_CPU_EN_CLEAR_MASK

#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_CLEAR_MASK   0x00000001

◆ PLL_FO0_EN_REG_PERI1PLL_CPU_EN_DISABLE

#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_DISABLE   0b0

◆ PLL_FO0_EN_REG_PERI1PLL_CPU_EN_ENABLE

#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_ENABLE   0b1

◆ PLL_FO0_EN_REG_PERI1PLL_CPU_EN_OFFSET

#define PLL_FO0_EN_REG_PERI1PLL_CPU_EN_OFFSET   0

◆ PLL_GPU_BIAS_REG

#define PLL_GPU_BIAS_REG   0x000000f0

◆ PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_GPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_GPU_CTRL_REG

#define PLL_GPU_CTRL_REG   0x000000e0

◆ PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_GPU_CTRL_REG_LOCK_OFFSET

#define PLL_GPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_GPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_GPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_GPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_GPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_GPU_CTRL_REG_PLL_N_OFFSET

#define PLL_GPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_GPU_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_GPU_CTRL_REG_PLL_P0_OFFSET

#define PLL_GPU_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_GPU_PAT0_CTRL_REG

#define PLL_GPU_PAT0_CTRL_REG   0x000000e8

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_GPU_PAT1_CTRL_REG

#define PLL_GPU_PAT1_CTRL_REG   0x000000ec

◆ PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_LOCK_DBG_CTRL_REG

#define PLL_LOCK_DBG_CTRL_REG   0x00001f2c

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   0x80000000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0b0

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0b1

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL   0b0111

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL   0b1000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   0x03f00000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL0

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL0   0b0000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL1

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL1   0b0001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL2

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL2   0b0010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL   0b0110

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL   0b0011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL   0b0100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL   0b0101

◆ PLL_OPG_BYPASS_REG

#define PLL_OPG_BYPASS_REG   0x00001a20

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK   0x00000001

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE   0b0

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE   0b1

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET   0

◆ PLL_PERI0_BIAS_REG

#define PLL_PERI0_BIAS_REG   0x000000b0

◆ PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_PERI0_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI0_CTRL_REG

#define PLL_PERI0_CTRL_REG   0x000000a0

◆ PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_PERI0_CTRL_REG_LOCK_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI0_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI0_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_PERI0_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_PERI0_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_PERI0_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_PERI0_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI0_PAT0_CTRL_REG

#define PLL_PERI0_PAT0_CTRL_REG   0x000000a8

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG

#define PLL_PERI0_PAT1_CTRL_REG   0x000000ac

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PERI1_BIAS_REG

#define PLL_PERI1_BIAS_REG   0x000000d0

◆ PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_PERI1_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI1_CTRL_REG

#define PLL_PERI1_CTRL_REG   0x000000c0

◆ PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_PERI1_CTRL_REG_LOCK_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI1_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI1_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_PERI1_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_PERI1_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_PERI1_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_PERI1_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI1_PAT0_CTRL_REG

#define PLL_PERI1_PAT0_CTRL_REG   0x000000c8

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG

#define PLL_PERI1_PAT1_CTRL_REG   0x000000cc

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VE_BIAS_REG

#define PLL_VE_BIAS_REG   0x00000230

◆ PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VE_BIAS_REG_PLL_CP_OFFSET

#define PLL_VE_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VE_CTRL_REG

#define PLL_VE_CTRL_REG   0x00000220

◆ PLL_VE_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VE_CTRL_REG_LOCK_OFFSET

#define PLL_VE_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VE_CTRL_REG_LOCK_UNLOCKED

#define PLL_VE_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VE_CTRL_REG_PLL_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VE_CTRL_REG_PLL_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VE_CTRL_REG_PLL_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VE_CTRL_REG_PLL_N_OFFSET

#define PLL_VE_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_VE_CTRL_REG_PLL_P0_OFFSET

#define PLL_VE_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VE_PAT0_CTRL_REG

#define PLL_VE_PAT0_CTRL_REG   0x00000228

◆ PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VE_PAT1_CTRL_REG

#define PLL_VE_PAT1_CTRL_REG   0x0000022c

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO0_BIAS_REG

#define PLL_VIDEO0_BIAS_REG   0x00000130

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO0_CTRL_REG

#define PLL_VIDEO0_CTRL_REG   0x00000120

◆ PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000

◆ PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET   16

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO0_PAT0_CTRL_REG

#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000128

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG

#define PLL_VIDEO0_PAT1_CTRL_REG   0x0000012c

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO1_BIAS_REG

#define PLL_VIDEO1_BIAS_REG   0x00000150

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO1_CTRL_REG

#define PLL_VIDEO1_CTRL_REG   0x00000140

◆ PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000

◆ PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET   16

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO1_PAT0_CTRL_REG

#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG

#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO2_BIAS_REG

#define PLL_VIDEO2_BIAS_REG   0x00000170

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO2_CTRL_REG

#define PLL_VIDEO2_CTRL_REG   0x00000160

◆ PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO2_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_P0_CLEAR_MASK   0x00700000

◆ PLL_VIDEO2_CTRL_REG_PLL_P0_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_VIDEO2_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_P1_CLEAR_MASK   0x00070000

◆ PLL_VIDEO2_CTRL_REG_PLL_P1_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_P1_OFFSET   16

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO2_PAT0_CTRL_REG

#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000168

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG

#define PLL_VIDEO2_PAT1_CTRL_REG   0x0000016c

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PWM0_GAR_REG

#define PWM0_GAR_REG   0x00000784

◆ PWM0_GAR_REG_PWM0_APB_CLK_EN_CLEAR_MASK

#define PWM0_GAR_REG_PWM0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ PWM0_GAR_REG_PWM0_APB_CLK_EN_MASK

#define PWM0_GAR_REG_PWM0_APB_CLK_EN_MASK   0x0

◆ PWM0_GAR_REG_PWM0_APB_CLK_EN_OFFSET

#define PWM0_GAR_REG_PWM0_APB_CLK_EN_OFFSET   0

◆ PWM0_GAR_REG_PWM0_APB_CLK_EN_PASS

#define PWM0_GAR_REG_PWM0_APB_CLK_EN_PASS   0b1

◆ PWM0_GAR_REG_PWM0_RST_N_ASSERT

#define PWM0_GAR_REG_PWM0_RST_N_ASSERT   0b0

◆ PWM0_GAR_REG_PWM0_RST_N_CLEAR_MASK

#define PWM0_GAR_REG_PWM0_RST_N_CLEAR_MASK   0x00010000

◆ PWM0_GAR_REG_PWM0_RST_N_DE_ASSERT

#define PWM0_GAR_REG_PWM0_RST_N_DE_ASSERT   0b1

◆ PWM0_GAR_REG_PWM0_RST_N_OFFSET

#define PWM0_GAR_REG_PWM0_RST_N_OFFSET   16

◆ RES24M_GATE_EN_REG

#define RES24M_GATE_EN_REG   0x00001a00

◆ RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_CLEAR_MASK

#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_CLEAR_MASK   0x00000001

◆ RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_DISABLE

#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_DISABLE   0b0

◆ RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_ENABLE

#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_ENABLE   0b1

◆ RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_OFFSET

#define RES24M_GATE_EN_REG_RES_DCAP_24M_CLK_EN_OFFSET   0

◆ RESET_SHIFT

#define RESET_SHIFT   (16)

◆ SMHC0_BGR_REG_SMHC0_GATING_OFFSET

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET    (SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)

◆ SMHC0_BGR_REG_SMHC0_RST_OFFSET

#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   (SMHC0_GAR_REG_SMHC0_RST_N_OFFSET)

◆ SMHC0_CLK_REG

#define SMHC0_CLK_REG   0x00000d00

◆ SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ SMHC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC0_CLK_REG_FACTOR_M_OFFSET

#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC0_CLK_REG_FACTOR_N_OFFSET

#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31

◆ SMHC0_CLK_SRC_PERI0_400M_FREQ

#define SMHC0_CLK_SRC_PERI0_400M_FREQ   (400000000)

◆ SMHC0_GAR_REG

#define SMHC0_GAR_REG   0x00000d0c

◆ SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_CLEAR_MASK

#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_MASK

#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_MASK   0x0

◆ SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET

#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_OFFSET   0

◆ SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_PASS

#define SMHC0_GAR_REG_SMHC0_AHB_CLK_EN_PASS   0b1

◆ SMHC0_GAR_REG_SMHC0_RST_N_ASSERT

#define SMHC0_GAR_REG_SMHC0_RST_N_ASSERT   0b0

◆ SMHC0_GAR_REG_SMHC0_RST_N_CLEAR_MASK

#define SMHC0_GAR_REG_SMHC0_RST_N_CLEAR_MASK   0x00010000

◆ SMHC0_GAR_REG_SMHC0_RST_N_DE_ASSERT

#define SMHC0_GAR_REG_SMHC0_RST_N_DE_ASSERT   0b1

◆ SMHC0_GAR_REG_SMHC0_RST_N_OFFSET

#define SMHC0_GAR_REG_SMHC0_RST_N_OFFSET   16

◆ SMHC1_CLK_REG

#define SMHC1_CLK_REG   0x00000d10

◆ SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ SMHC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC1_CLK_REG_FACTOR_M_OFFSET

#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC1_CLK_REG_FACTOR_N_OFFSET

#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31

◆ SMHC1_GAR_REG

#define SMHC1_GAR_REG   0x00000d1c

◆ SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_CLEAR_MASK

#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_MASK

#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_MASK   0x0

◆ SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_OFFSET

#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_OFFSET   0

◆ SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_PASS

#define SMHC1_GAR_REG_SMHC1_AHB_CLK_EN_PASS   0b1

◆ SMHC1_GAR_REG_SMHC1_RST_N_ASSERT

#define SMHC1_GAR_REG_SMHC1_RST_N_ASSERT   0b0

◆ SMHC1_GAR_REG_SMHC1_RST_N_CLEAR_MASK

#define SMHC1_GAR_REG_SMHC1_RST_N_CLEAR_MASK   0x00010000

◆ SMHC1_GAR_REG_SMHC1_RST_N_DE_ASSERT

#define SMHC1_GAR_REG_SMHC1_RST_N_DE_ASSERT   0b1

◆ SMHC1_GAR_REG_SMHC1_RST_N_OFFSET

#define SMHC1_GAR_REG_SMHC1_RST_N_OFFSET   16

◆ SMHC2_CLK_REG

#define SMHC2_CLK_REG   0x00000d20

◆ SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011

◆ SMHC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC2_CLK_REG_FACTOR_M_OFFSET

#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC2_CLK_REG_FACTOR_N_OFFSET

#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31

◆ SMHC2_CLK_SRC_PERI0_800M_FREQ

#define SMHC2_CLK_SRC_PERI0_800M_FREQ   (800000000)

◆ SMHC2_GAR_REG

#define SMHC2_GAR_REG   0x00000d2c

◆ SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_CLEAR_MASK

#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_MASK

#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_MASK   0x0

◆ SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_OFFSET

#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_OFFSET   0

◆ SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_PASS

#define SMHC2_GAR_REG_SMHC2_AHB_CLK_EN_PASS   0b1

◆ SMHC2_GAR_REG_SMHC2_RST_N_ASSERT

#define SMHC2_GAR_REG_SMHC2_RST_N_ASSERT   0b0

◆ SMHC2_GAR_REG_SMHC2_RST_N_CLEAR_MASK

#define SMHC2_GAR_REG_SMHC2_RST_N_CLEAR_MASK   0x00010000

◆ SMHC2_GAR_REG_SMHC2_RST_N_DE_ASSERT

#define SMHC2_GAR_REG_SMHC2_RST_N_DE_ASSERT   0b1

◆ SMHC2_GAR_REG_SMHC2_RST_N_OFFSET

#define SMHC2_GAR_REG_SMHC2_RST_N_OFFSET   16

◆ SPI0_CLK_REG

#define SPI0_CLK_REG   0x00000f00

◆ SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100

◆ SPI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SPI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI0_CLK_REG_FACTOR_M_OFFSET

#define SPI0_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SPI0_CLK_REG_FACTOR_N_OFFSET

#define SPI0_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31

◆ SPI0_GAR_REG

#define SPI0_GAR_REG   0x00000f04

◆ SPI0_GAR_REG_SPI0_AHB_CLK_EN_CLEAR_MASK

#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SPI0_GAR_REG_SPI0_AHB_CLK_EN_MASK

#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_MASK   0x0

◆ SPI0_GAR_REG_SPI0_AHB_CLK_EN_OFFSET

#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_OFFSET   0

◆ SPI0_GAR_REG_SPI0_AHB_CLK_EN_PASS

#define SPI0_GAR_REG_SPI0_AHB_CLK_EN_PASS   0b1

◆ SPI0_GAR_REG_SPI0_RST_N_ASSERT

#define SPI0_GAR_REG_SPI0_RST_N_ASSERT   0b0

◆ SPI0_GAR_REG_SPI0_RST_N_CLEAR_MASK

#define SPI0_GAR_REG_SPI0_RST_N_CLEAR_MASK   0x00010000

◆ SPI0_GAR_REG_SPI0_RST_N_DE_ASSERT

#define SPI0_GAR_REG_SPI0_RST_N_DE_ASSERT   0b1

◆ SPI0_GAR_REG_SPI0_RST_N_OFFSET

#define SPI0_GAR_REG_SPI0_RST_N_OFFSET   16

◆ SPI1_CLK_REG

#define SPI1_CLK_REG   0x00000f08

◆ SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100

◆ SPI1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SPI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI1_CLK_REG_FACTOR_M_OFFSET

#define SPI1_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SPI1_CLK_REG_FACTOR_N_OFFSET

#define SPI1_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31

◆ SPI1_GAR_REG

#define SPI1_GAR_REG   0x00000f0c

◆ SPI1_GAR_REG_SPI1_AHB_CLK_EN_CLEAR_MASK

#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SPI1_GAR_REG_SPI1_AHB_CLK_EN_MASK

#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_MASK   0x0

◆ SPI1_GAR_REG_SPI1_AHB_CLK_EN_OFFSET

#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_OFFSET   0

◆ SPI1_GAR_REG_SPI1_AHB_CLK_EN_PASS

#define SPI1_GAR_REG_SPI1_AHB_CLK_EN_PASS   0b1

◆ SPI1_GAR_REG_SPI1_RST_N_ASSERT

#define SPI1_GAR_REG_SPI1_RST_N_ASSERT   0b0

◆ SPI1_GAR_REG_SPI1_RST_N_CLEAR_MASK

#define SPI1_GAR_REG_SPI1_RST_N_CLEAR_MASK   0x00010000

◆ SPI1_GAR_REG_SPI1_RST_N_DE_ASSERT

#define SPI1_GAR_REG_SPI1_RST_N_DE_ASSERT   0b1

◆ SPI1_GAR_REG_SPI1_RST_N_OFFSET

#define SPI1_GAR_REG_SPI1_RST_N_OFFSET   16

◆ SPI2_CLK_REG

#define SPI2_CLK_REG   0x00000f10

◆ SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b101

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100

◆ SPI2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ SPI2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI2_CLK_REG_FACTOR_M_OFFSET

#define SPI2_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SPI2_CLK_REG_FACTOR_N_OFFSET

#define SPI2_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31

◆ SPI2_GAR_REG

#define SPI2_GAR_REG   0x00000f14

◆ SPI2_GAR_REG_SPI2_AHB_CLK_EN_CLEAR_MASK

#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SPI2_GAR_REG_SPI2_AHB_CLK_EN_MASK

#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_MASK   0x0

◆ SPI2_GAR_REG_SPI2_AHB_CLK_EN_OFFSET

#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_OFFSET   0

◆ SPI2_GAR_REG_SPI2_AHB_CLK_EN_PASS

#define SPI2_GAR_REG_SPI2_AHB_CLK_EN_PASS   0b1

◆ SPI2_GAR_REG_SPI2_RST_N_ASSERT

#define SPI2_GAR_REG_SPI2_RST_N_ASSERT   0b0

◆ SPI2_GAR_REG_SPI2_RST_N_CLEAR_MASK

#define SPI2_GAR_REG_SPI2_RST_N_CLEAR_MASK   0x00010000

◆ SPI2_GAR_REG_SPI2_RST_N_DE_ASSERT

#define SPI2_GAR_REG_SPI2_RST_N_DE_ASSERT   0b1

◆ SPI2_GAR_REG_SPI2_RST_N_OFFSET

#define SPI2_GAR_REG_SPI2_RST_N_OFFSET   16

◆ SPINLOCK_GAR_REG

#define SPINLOCK_GAR_REG   0x00000724

◆ SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_CLEAR_MASK

#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_MASK

#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_MASK   0x0

◆ SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_OFFSET

#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_OFFSET   0

◆ SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_PASS

#define SPINLOCK_GAR_REG_SPINLOCK_AHB_CLK_EN_PASS   0b1

◆ SPINLOCK_GAR_REG_SPINLOCK_RST_N_ASSERT

#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_ASSERT   0b0

◆ SPINLOCK_GAR_REG_SPINLOCK_RST_N_CLEAR_MASK

#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_CLEAR_MASK   0x00010000

◆ SPINLOCK_GAR_REG_SPINLOCK_RST_N_DE_ASSERT

#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_DE_ASSERT   0b1

◆ SPINLOCK_GAR_REG_SPINLOCK_RST_N_OFFSET

#define SPINLOCK_GAR_REG_SPINLOCK_RST_N_OFFSET   16

◆ SUNXI_CE_FACTOR_0

#define SUNXI_CE_FACTOR_0   0b0

◆ SUNXI_CE_GATING_OFFSET

#define SUNXI_CE_GATING_OFFSET   CE_SYS_GAR_REG_CE_SYS_IP_AHB_CLK_EN_MASK

◆ SUNXI_CE_GATING_ON

#define SUNXI_CE_GATING_ON   1

◆ SUNXI_CE_MBUS_CLK_GATE_OFFSET

#define SUNXI_CE_MBUS_CLK_GATE_OFFSET   MBUS_CLK_GATE_EN_REG_CE_SYS_AXI_CLK_EN_OFFSET

◆ SUNXI_CE_MBUS_CLK_REG

#define SUNXI_CE_MBUS_CLK_REG   (SUNXI_CCU_BASE + MBUS_CLK_GATE_EN_REG)

◆ SUNXI_CE_MBUS_MAT_CLK_GATE_OFFSET

#define SUNXI_CE_MBUS_MAT_CLK_GATE_OFFSET   MBUS_MAT_CLK_GATE_EN_REG_CE_SYS_AXI_GATE_SW_CFG_OFFSET

◆ SUNXI_CE_MBUS_MAT_CLK_REG

#define SUNXI_CE_MBUS_MAT_CLK_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATE_EN_REG)

◆ SUNXI_CE_SRC_600M

#define SUNXI_CE_SRC_600M   CE_SYS_CLK_REG_CLK_SRC_SEL_PERI0_600M

◆ SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET

#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET   CE_SYS_CLK_REG_FACTOR_M_OFFSET

◆ SUNXI_CE_SYS_CLK_REG

#define SUNXI_CE_SYS_CLK_REG   (SUNXI_CCU_BASE + CE_SYS_CLK_REG)

◆ SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET

#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET   CE_SYS_CLK_REG_CLK_SRC_SEL_OFFSET

◆ SUNXI_CE_SYS_GATING_OFFSET

#define SUNXI_CE_SYS_GATING_OFFSET   CE_SYS_CLK_REG_CE_SYS_CLK_GATING_OFFSET

◆ SUNXI_CE_SYS_GATING_RESET_OFFSET

#define SUNXI_CE_SYS_GATING_RESET_OFFSET   CE_SYS_GAR_REG_CE_SYS_RST_N_OFFSET

◆ SUNXI_CE_SYS_GATING_RESET_REG

#define SUNXI_CE_SYS_GATING_RESET_REG   (SUNXI_CCU_BASE + CE_SYS_GAR_REG)

◆ TCON_LCD0_CLK_REG

#define TCON_LCD0_CLK_REG   0x00001500

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_OFFSET

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define TCON_LCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ TCON_LCD0_CLK_REG_FACTOR_M_CLEAR_MASK

#define TCON_LCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ TCON_LCD0_CLK_REG_FACTOR_M_OFFSET

#define TCON_LCD0_CLK_REG_FACTOR_M_OFFSET   0

◆ TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLEAR_MASK

#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLEAR_MASK   0x80000000

◆ TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_OFF

#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_ON

#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_CLOCK_IS_ON   0b1

◆ TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_OFFSET

#define TCON_LCD0_CLK_REG_TCON_LCD0_CLK_GATING_OFFSET   31

◆ TCON_LCD0_GAR_REG

#define TCON_LCD0_GAR_REG   0x00001504

◆ TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_CLEAR_MASK

#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_MASK

#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_MASK   0b0

◆ TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_OFFSET

#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_OFFSET   0

◆ TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_PASS

#define TCON_LCD0_GAR_REG_TCON_LCD0_AHB_CLK_EN_PASS   0b1

◆ TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_ASSERT

#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_ASSERT   0b0

◆ TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_CLEAR_MASK

#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_CLEAR_MASK   0x00010000

◆ TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_DE_ASSERT

#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_DE_ASSERT   0b1

◆ TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_OFFSET

#define TCON_LCD0_GAR_REG_TCON_LCD0_RST_N_OFFSET   16

◆ TCON_TV0_eDP_CLK_REG

#define TCON_TV0_eDP_CLK_REG   0x00001600

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_OFFSET

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b101

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define TCON_TV0_eDP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ TCON_TV0_eDP_CLK_REG_FACTOR_M_CLEAR_MASK

#define TCON_TV0_eDP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ TCON_TV0_eDP_CLK_REG_FACTOR_M_OFFSET

#define TCON_TV0_eDP_CLK_REG_FACTOR_M_OFFSET   0

◆ TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLEAR_MASK

#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLEAR_MASK   0x80000000

◆ TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_OFF

#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_OFF   0b0

◆ TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_ON

#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_CLOCK_IS_ON   0b1

◆ TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_OFFSET

#define TCON_TV0_eDP_CLK_REG_TCON_TV0_EDP_CLK_GATING_OFFSET   31

◆ TCON_TV0_GAR_REG

#define TCON_TV0_GAR_REG   0x00001604

◆ TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_CLEAR_MASK

#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_MASK

#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_MASK   0b0

◆ TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_OFFSET

#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_OFFSET   0

◆ TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_PASS

#define TCON_TV0_GAR_REG_TCON_TV0_AHB_CLK_EN_PASS   0b1

◆ TCON_TV0_GAR_REG_TCON_TV0_RST_N_ASSERT

#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_ASSERT   0b0

◆ TCON_TV0_GAR_REG_TCON_TV0_RST_N_CLEAR_MASK

#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_CLEAR_MASK   0x00010000

◆ TCON_TV0_GAR_REG_TCON_TV0_RST_N_DE_ASSERT

#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_DE_ASSERT   0b1

◆ TCON_TV0_GAR_REG_TCON_TV0_RST_N_OFFSET

#define TCON_TV0_GAR_REG_TCON_TV0_RST_N_OFFSET   16

◆ TIMER0_0_CLK_REG

#define TIMER0_0_CLK_REG   0x00000800

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define TIMER0_0_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010

◆ TIMER0_0_CLK_REG_FACTOR_M__1

#define TIMER0_0_CLK_REG_FACTOR_M__1   0b000

◆ TIMER0_0_CLK_REG_FACTOR_M__128

#define TIMER0_0_CLK_REG_FACTOR_M__128   0b111

◆ TIMER0_0_CLK_REG_FACTOR_M__16

#define TIMER0_0_CLK_REG_FACTOR_M__16   0b100

◆ TIMER0_0_CLK_REG_FACTOR_M__2

#define TIMER0_0_CLK_REG_FACTOR_M__2   0b001

◆ TIMER0_0_CLK_REG_FACTOR_M__32

#define TIMER0_0_CLK_REG_FACTOR_M__32   0b101

◆ TIMER0_0_CLK_REG_FACTOR_M__4

#define TIMER0_0_CLK_REG_FACTOR_M__4   0b010

◆ TIMER0_0_CLK_REG_FACTOR_M__64

#define TIMER0_0_CLK_REG_FACTOR_M__64   0b110

◆ TIMER0_0_CLK_REG_FACTOR_M__8

#define TIMER0_0_CLK_REG_FACTOR_M__8   0b011

◆ TIMER0_0_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_0_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER0_0_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_0_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_CLEAR_MASK

#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_DISABLE

#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_DISABLE   0b0

◆ TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_ENABLE

#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_ENABLE   0b1

◆ TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_OFFSET

#define TIMER0_0_CLK_REG_TIMER0_0_CLK_GATING_OFFSET   31

◆ TIMER0_1_CLK_REG

#define TIMER0_1_CLK_REG   0x00000804

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define TIMER0_1_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010

◆ TIMER0_1_CLK_REG_FACTOR_M__1

#define TIMER0_1_CLK_REG_FACTOR_M__1   0b000

◆ TIMER0_1_CLK_REG_FACTOR_M__128

#define TIMER0_1_CLK_REG_FACTOR_M__128   0b111

◆ TIMER0_1_CLK_REG_FACTOR_M__16

#define TIMER0_1_CLK_REG_FACTOR_M__16   0b100

◆ TIMER0_1_CLK_REG_FACTOR_M__2

#define TIMER0_1_CLK_REG_FACTOR_M__2   0b001

◆ TIMER0_1_CLK_REG_FACTOR_M__32

#define TIMER0_1_CLK_REG_FACTOR_M__32   0b101

◆ TIMER0_1_CLK_REG_FACTOR_M__4

#define TIMER0_1_CLK_REG_FACTOR_M__4   0b010

◆ TIMER0_1_CLK_REG_FACTOR_M__64

#define TIMER0_1_CLK_REG_FACTOR_M__64   0b110

◆ TIMER0_1_CLK_REG_FACTOR_M__8

#define TIMER0_1_CLK_REG_FACTOR_M__8   0b011

◆ TIMER0_1_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_1_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER0_1_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_1_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_CLEAR_MASK

#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_DISABLE

#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_DISABLE   0b0

◆ TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_ENABLE

#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_ENABLE   0b1

◆ TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_OFFSET

#define TIMER0_1_CLK_REG_TIMER0_1_CLK_GATING_OFFSET   31

◆ TIMER0_2_CLK_REG

#define TIMER0_2_CLK_REG   0x00000808

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define TIMER0_2_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010

◆ TIMER0_2_CLK_REG_FACTOR_M__1

#define TIMER0_2_CLK_REG_FACTOR_M__1   0b000

◆ TIMER0_2_CLK_REG_FACTOR_M__128

#define TIMER0_2_CLK_REG_FACTOR_M__128   0b111

◆ TIMER0_2_CLK_REG_FACTOR_M__16

#define TIMER0_2_CLK_REG_FACTOR_M__16   0b100

◆ TIMER0_2_CLK_REG_FACTOR_M__2

#define TIMER0_2_CLK_REG_FACTOR_M__2   0b001

◆ TIMER0_2_CLK_REG_FACTOR_M__32

#define TIMER0_2_CLK_REG_FACTOR_M__32   0b101

◆ TIMER0_2_CLK_REG_FACTOR_M__4

#define TIMER0_2_CLK_REG_FACTOR_M__4   0b010

◆ TIMER0_2_CLK_REG_FACTOR_M__64

#define TIMER0_2_CLK_REG_FACTOR_M__64   0b110

◆ TIMER0_2_CLK_REG_FACTOR_M__8

#define TIMER0_2_CLK_REG_FACTOR_M__8   0b011

◆ TIMER0_2_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_2_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER0_2_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_2_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_CLEAR_MASK

#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_DISABLE

#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_DISABLE   0b0

◆ TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_ENABLE

#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_ENABLE   0b1

◆ TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_OFFSET

#define TIMER0_2_CLK_REG_TIMER0_2_CLK_GATING_OFFSET   31

◆ TIMER0_3_CLK_REG

#define TIMER0_3_CLK_REG   0x0000080c

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_RC_16M_CLK

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_RC_16M_CLK   0b001

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define TIMER0_3_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b010

◆ TIMER0_3_CLK_REG_FACTOR_M__1

#define TIMER0_3_CLK_REG_FACTOR_M__1   0b000

◆ TIMER0_3_CLK_REG_FACTOR_M__128

#define TIMER0_3_CLK_REG_FACTOR_M__128   0b111

◆ TIMER0_3_CLK_REG_FACTOR_M__16

#define TIMER0_3_CLK_REG_FACTOR_M__16   0b100

◆ TIMER0_3_CLK_REG_FACTOR_M__2

#define TIMER0_3_CLK_REG_FACTOR_M__2   0b001

◆ TIMER0_3_CLK_REG_FACTOR_M__32

#define TIMER0_3_CLK_REG_FACTOR_M__32   0b101

◆ TIMER0_3_CLK_REG_FACTOR_M__4

#define TIMER0_3_CLK_REG_FACTOR_M__4   0b010

◆ TIMER0_3_CLK_REG_FACTOR_M__64

#define TIMER0_3_CLK_REG_FACTOR_M__64   0b110

◆ TIMER0_3_CLK_REG_FACTOR_M__8

#define TIMER0_3_CLK_REG_FACTOR_M__8   0b011

◆ TIMER0_3_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_3_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER0_3_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_3_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_CLEAR_MASK

#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_DISABLE

#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_DISABLE   0b0

◆ TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_ENABLE

#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_ENABLE   0b1

◆ TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_OFFSET

#define TIMER0_3_CLK_REG_TIMER0_3_CLK_GATING_OFFSET   31

◆ TIMER0_GAR_REG

#define TIMER0_GAR_REG   0x00000850

◆ TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_CLEAR_MASK

#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_MASK

#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_MASK   0x0

◆ TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_OFFSET

#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_OFFSET   0

◆ TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_PASS

#define TIMER0_GAR_REG_TIMER0_AHB_CLK_EN_PASS   0b1

◆ TIMER0_GAR_REG_TIMER0_RST_N_ASSERT

#define TIMER0_GAR_REG_TIMER0_RST_N_ASSERT   0b0

◆ TIMER0_GAR_REG_TIMER0_RST_N_CLEAR_MASK

#define TIMER0_GAR_REG_TIMER0_RST_N_CLEAR_MASK   0x00010000

◆ TIMER0_GAR_REG_TIMER0_RST_N_DE_ASSERT

#define TIMER0_GAR_REG_TIMER0_RST_N_DE_ASSERT   0b1

◆ TIMER0_GAR_REG_TIMER0_RST_N_OFFSET

#define TIMER0_GAR_REG_TIMER0_RST_N_OFFSET   16

◆ TSENSOR_GAR_REG

#define TSENSOR_GAR_REG   0x00000fe4

◆ TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_CLEAR_MASK

#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_MASK

#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_MASK   0x0

◆ TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_OFFSET

#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_OFFSET   0

◆ TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_PASS

#define TSENSOR_GAR_REG_TSENSOR_APB_CLK_EN_PASS   0b1

◆ TSENSOR_GAR_REG_TSENSOR_RST_N_ASSERT

#define TSENSOR_GAR_REG_TSENSOR_RST_N_ASSERT   0b0

◆ TSENSOR_GAR_REG_TSENSOR_RST_N_CLEAR_MASK

#define TSENSOR_GAR_REG_TSENSOR_RST_N_CLEAR_MASK   0x00010000

◆ TSENSOR_GAR_REG_TSENSOR_RST_N_DE_ASSERT

#define TSENSOR_GAR_REG_TSENSOR_RST_N_DE_ASSERT   0b1

◆ TSENSOR_GAR_REG_TSENSOR_RST_N_OFFSET

#define TSENSOR_GAR_REG_TSENSOR_RST_N_OFFSET   16

◆ TWI0_GAR_REG

#define TWI0_GAR_REG   0x00000e80

◆ TWI0_GAR_REG_TWI0_APB_CLK_EN_CLEAR_MASK

#define TWI0_GAR_REG_TWI0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI0_GAR_REG_TWI0_APB_CLK_EN_MASK

#define TWI0_GAR_REG_TWI0_APB_CLK_EN_MASK   0x0

◆ TWI0_GAR_REG_TWI0_APB_CLK_EN_OFFSET

#define TWI0_GAR_REG_TWI0_APB_CLK_EN_OFFSET   0

◆ TWI0_GAR_REG_TWI0_APB_CLK_EN_PASS

#define TWI0_GAR_REG_TWI0_APB_CLK_EN_PASS   0b1

◆ TWI0_GAR_REG_TWI0_RST_N_ASSERT

#define TWI0_GAR_REG_TWI0_RST_N_ASSERT   0b0

◆ TWI0_GAR_REG_TWI0_RST_N_CLEAR_MASK

#define TWI0_GAR_REG_TWI0_RST_N_CLEAR_MASK   0x00010000

◆ TWI0_GAR_REG_TWI0_RST_N_DE_ASSERT

#define TWI0_GAR_REG_TWI0_RST_N_DE_ASSERT   0b1

◆ TWI0_GAR_REG_TWI0_RST_N_OFFSET

#define TWI0_GAR_REG_TWI0_RST_N_OFFSET   16

◆ TWI1_GAR_REG

#define TWI1_GAR_REG   0x00000e84

◆ TWI1_GAR_REG_TWI1_APB_CLK_EN_CLEAR_MASK

#define TWI1_GAR_REG_TWI1_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI1_GAR_REG_TWI1_APB_CLK_EN_MASK

#define TWI1_GAR_REG_TWI1_APB_CLK_EN_MASK   0x0

◆ TWI1_GAR_REG_TWI1_APB_CLK_EN_OFFSET

#define TWI1_GAR_REG_TWI1_APB_CLK_EN_OFFSET   0

◆ TWI1_GAR_REG_TWI1_APB_CLK_EN_PASS

#define TWI1_GAR_REG_TWI1_APB_CLK_EN_PASS   0b1

◆ TWI1_GAR_REG_TWI1_RST_N_ASSERT

#define TWI1_GAR_REG_TWI1_RST_N_ASSERT   0b0

◆ TWI1_GAR_REG_TWI1_RST_N_CLEAR_MASK

#define TWI1_GAR_REG_TWI1_RST_N_CLEAR_MASK   0x00010000

◆ TWI1_GAR_REG_TWI1_RST_N_DE_ASSERT

#define TWI1_GAR_REG_TWI1_RST_N_DE_ASSERT   0b1

◆ TWI1_GAR_REG_TWI1_RST_N_OFFSET

#define TWI1_GAR_REG_TWI1_RST_N_OFFSET   16

◆ TWI2_GAR_REG

#define TWI2_GAR_REG   0x00000e88

◆ TWI2_GAR_REG_TWI2_APB_CLK_EN_CLEAR_MASK

#define TWI2_GAR_REG_TWI2_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI2_GAR_REG_TWI2_APB_CLK_EN_MASK

#define TWI2_GAR_REG_TWI2_APB_CLK_EN_MASK   0x0

◆ TWI2_GAR_REG_TWI2_APB_CLK_EN_OFFSET

#define TWI2_GAR_REG_TWI2_APB_CLK_EN_OFFSET   0

◆ TWI2_GAR_REG_TWI2_APB_CLK_EN_PASS

#define TWI2_GAR_REG_TWI2_APB_CLK_EN_PASS   0b1

◆ TWI2_GAR_REG_TWI2_RST_N_ASSERT

#define TWI2_GAR_REG_TWI2_RST_N_ASSERT   0b0

◆ TWI2_GAR_REG_TWI2_RST_N_CLEAR_MASK

#define TWI2_GAR_REG_TWI2_RST_N_CLEAR_MASK   0x00010000

◆ TWI2_GAR_REG_TWI2_RST_N_DE_ASSERT

#define TWI2_GAR_REG_TWI2_RST_N_DE_ASSERT   0b1

◆ TWI2_GAR_REG_TWI2_RST_N_OFFSET

#define TWI2_GAR_REG_TWI2_RST_N_OFFSET   16

◆ TWI3_GAR_REG

#define TWI3_GAR_REG   0x00000e8c

◆ TWI3_GAR_REG_TWI3_APB_CLK_EN_CLEAR_MASK

#define TWI3_GAR_REG_TWI3_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI3_GAR_REG_TWI3_APB_CLK_EN_MASK

#define TWI3_GAR_REG_TWI3_APB_CLK_EN_MASK   0x0

◆ TWI3_GAR_REG_TWI3_APB_CLK_EN_OFFSET

#define TWI3_GAR_REG_TWI3_APB_CLK_EN_OFFSET   0

◆ TWI3_GAR_REG_TWI3_APB_CLK_EN_PASS

#define TWI3_GAR_REG_TWI3_APB_CLK_EN_PASS   0b1

◆ TWI3_GAR_REG_TWI3_RST_N_ASSERT

#define TWI3_GAR_REG_TWI3_RST_N_ASSERT   0b0

◆ TWI3_GAR_REG_TWI3_RST_N_CLEAR_MASK

#define TWI3_GAR_REG_TWI3_RST_N_CLEAR_MASK   0x00010000

◆ TWI3_GAR_REG_TWI3_RST_N_DE_ASSERT

#define TWI3_GAR_REG_TWI3_RST_N_DE_ASSERT   0b1

◆ TWI3_GAR_REG_TWI3_RST_N_OFFSET

#define TWI3_GAR_REG_TWI3_RST_N_OFFSET   16

◆ TWI4_GAR_REG

#define TWI4_GAR_REG   0x00000e90

◆ TWI4_GAR_REG_TWI4_APB_CLK_EN_CLEAR_MASK

#define TWI4_GAR_REG_TWI4_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI4_GAR_REG_TWI4_APB_CLK_EN_MASK

#define TWI4_GAR_REG_TWI4_APB_CLK_EN_MASK   0x0

◆ TWI4_GAR_REG_TWI4_APB_CLK_EN_OFFSET

#define TWI4_GAR_REG_TWI4_APB_CLK_EN_OFFSET   0

◆ TWI4_GAR_REG_TWI4_APB_CLK_EN_PASS

#define TWI4_GAR_REG_TWI4_APB_CLK_EN_PASS   0b1

◆ TWI4_GAR_REG_TWI4_RST_N_ASSERT

#define TWI4_GAR_REG_TWI4_RST_N_ASSERT   0b0

◆ TWI4_GAR_REG_TWI4_RST_N_CLEAR_MASK

#define TWI4_GAR_REG_TWI4_RST_N_CLEAR_MASK   0x00010000

◆ TWI4_GAR_REG_TWI4_RST_N_DE_ASSERT

#define TWI4_GAR_REG_TWI4_RST_N_DE_ASSERT   0b1

◆ TWI4_GAR_REG_TWI4_RST_N_OFFSET

#define TWI4_GAR_REG_TWI4_RST_N_OFFSET   16

◆ TWI5_GAR_REG

#define TWI5_GAR_REG   0x00000e94

◆ TWI5_GAR_REG_TWI5_APB_CLK_EN_CLEAR_MASK

#define TWI5_GAR_REG_TWI5_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ TWI5_GAR_REG_TWI5_APB_CLK_EN_MASK

#define TWI5_GAR_REG_TWI5_APB_CLK_EN_MASK   0x0

◆ TWI5_GAR_REG_TWI5_APB_CLK_EN_OFFSET

#define TWI5_GAR_REG_TWI5_APB_CLK_EN_OFFSET   0

◆ TWI5_GAR_REG_TWI5_APB_CLK_EN_PASS

#define TWI5_GAR_REG_TWI5_APB_CLK_EN_PASS   0b1

◆ TWI5_GAR_REG_TWI5_RST_N_ASSERT

#define TWI5_GAR_REG_TWI5_RST_N_ASSERT   0b0

◆ TWI5_GAR_REG_TWI5_RST_N_CLEAR_MASK

#define TWI5_GAR_REG_TWI5_RST_N_CLEAR_MASK   0x00010000

◆ TWI5_GAR_REG_TWI5_RST_N_DE_ASSERT

#define TWI5_GAR_REG_TWI5_RST_N_DE_ASSERT   0b1

◆ TWI5_GAR_REG_TWI5_RST_N_OFFSET

#define TWI5_GAR_REG_TWI5_RST_N_OFFSET   16

◆ UART0_GAR_REG

#define UART0_GAR_REG   0x00000e00

◆ UART0_GAR_REG_UART0_APB_CLK_EN_CLEAR_MASK

#define UART0_GAR_REG_UART0_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART0_GAR_REG_UART0_APB_CLK_EN_MASK

#define UART0_GAR_REG_UART0_APB_CLK_EN_MASK   0x0

◆ UART0_GAR_REG_UART0_APB_CLK_EN_OFFSET

#define UART0_GAR_REG_UART0_APB_CLK_EN_OFFSET   0

◆ UART0_GAR_REG_UART0_APB_CLK_EN_PASS

#define UART0_GAR_REG_UART0_APB_CLK_EN_PASS   0b1

◆ UART0_GAR_REG_UART0_RST_N_ASSERT

#define UART0_GAR_REG_UART0_RST_N_ASSERT   0b0

◆ UART0_GAR_REG_UART0_RST_N_CLEAR_MASK

#define UART0_GAR_REG_UART0_RST_N_CLEAR_MASK   0x00010000

◆ UART0_GAR_REG_UART0_RST_N_DE_ASSERT

#define UART0_GAR_REG_UART0_RST_N_DE_ASSERT   0b1

◆ UART0_GAR_REG_UART0_RST_N_OFFSET

#define UART0_GAR_REG_UART0_RST_N_OFFSET   16

◆ UART1_GAR_REG

#define UART1_GAR_REG   0x00000e04

◆ UART1_GAR_REG_UART1_APB_CLK_EN_CLEAR_MASK

#define UART1_GAR_REG_UART1_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART1_GAR_REG_UART1_APB_CLK_EN_MASK

#define UART1_GAR_REG_UART1_APB_CLK_EN_MASK   0x0

◆ UART1_GAR_REG_UART1_APB_CLK_EN_OFFSET

#define UART1_GAR_REG_UART1_APB_CLK_EN_OFFSET   0

◆ UART1_GAR_REG_UART1_APB_CLK_EN_PASS

#define UART1_GAR_REG_UART1_APB_CLK_EN_PASS   0b1

◆ UART1_GAR_REG_UART1_RST_N_ASSERT

#define UART1_GAR_REG_UART1_RST_N_ASSERT   0b0

◆ UART1_GAR_REG_UART1_RST_N_CLEAR_MASK

#define UART1_GAR_REG_UART1_RST_N_CLEAR_MASK   0x00010000

◆ UART1_GAR_REG_UART1_RST_N_DE_ASSERT

#define UART1_GAR_REG_UART1_RST_N_DE_ASSERT   0b1

◆ UART1_GAR_REG_UART1_RST_N_OFFSET

#define UART1_GAR_REG_UART1_RST_N_OFFSET   16

◆ UART2_GAR_REG

#define UART2_GAR_REG   0x00000e08

◆ UART2_GAR_REG_UART2_APB_CLK_EN_CLEAR_MASK

#define UART2_GAR_REG_UART2_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART2_GAR_REG_UART2_APB_CLK_EN_MASK

#define UART2_GAR_REG_UART2_APB_CLK_EN_MASK   0x0

◆ UART2_GAR_REG_UART2_APB_CLK_EN_OFFSET

#define UART2_GAR_REG_UART2_APB_CLK_EN_OFFSET   0

◆ UART2_GAR_REG_UART2_APB_CLK_EN_PASS

#define UART2_GAR_REG_UART2_APB_CLK_EN_PASS   0b1

◆ UART2_GAR_REG_UART2_RST_N_ASSERT

#define UART2_GAR_REG_UART2_RST_N_ASSERT   0b0

◆ UART2_GAR_REG_UART2_RST_N_CLEAR_MASK

#define UART2_GAR_REG_UART2_RST_N_CLEAR_MASK   0x00010000

◆ UART2_GAR_REG_UART2_RST_N_DE_ASSERT

#define UART2_GAR_REG_UART2_RST_N_DE_ASSERT   0b1

◆ UART2_GAR_REG_UART2_RST_N_OFFSET

#define UART2_GAR_REG_UART2_RST_N_OFFSET   16

◆ UART3_GAR_REG

#define UART3_GAR_REG   0x00000e0c

◆ UART3_GAR_REG_UART3_APB_CLK_EN_CLEAR_MASK

#define UART3_GAR_REG_UART3_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART3_GAR_REG_UART3_APB_CLK_EN_MASK

#define UART3_GAR_REG_UART3_APB_CLK_EN_MASK   0x0

◆ UART3_GAR_REG_UART3_APB_CLK_EN_OFFSET

#define UART3_GAR_REG_UART3_APB_CLK_EN_OFFSET   0

◆ UART3_GAR_REG_UART3_APB_CLK_EN_PASS

#define UART3_GAR_REG_UART3_APB_CLK_EN_PASS   0b1

◆ UART3_GAR_REG_UART3_RST_N_ASSERT

#define UART3_GAR_REG_UART3_RST_N_ASSERT   0b0

◆ UART3_GAR_REG_UART3_RST_N_CLEAR_MASK

#define UART3_GAR_REG_UART3_RST_N_CLEAR_MASK   0x00010000

◆ UART3_GAR_REG_UART3_RST_N_DE_ASSERT

#define UART3_GAR_REG_UART3_RST_N_DE_ASSERT   0b1

◆ UART3_GAR_REG_UART3_RST_N_OFFSET

#define UART3_GAR_REG_UART3_RST_N_OFFSET   16

◆ UART4_GAR_REG

#define UART4_GAR_REG   0x00000e10

◆ UART4_GAR_REG_UART4_APB_CLK_EN_CLEAR_MASK

#define UART4_GAR_REG_UART4_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART4_GAR_REG_UART4_APB_CLK_EN_MASK

#define UART4_GAR_REG_UART4_APB_CLK_EN_MASK   0x0

◆ UART4_GAR_REG_UART4_APB_CLK_EN_OFFSET

#define UART4_GAR_REG_UART4_APB_CLK_EN_OFFSET   0

◆ UART4_GAR_REG_UART4_APB_CLK_EN_PASS

#define UART4_GAR_REG_UART4_APB_CLK_EN_PASS   0b1

◆ UART4_GAR_REG_UART4_RST_N_ASSERT

#define UART4_GAR_REG_UART4_RST_N_ASSERT   0b0

◆ UART4_GAR_REG_UART4_RST_N_CLEAR_MASK

#define UART4_GAR_REG_UART4_RST_N_CLEAR_MASK   0x00010000

◆ UART4_GAR_REG_UART4_RST_N_DE_ASSERT

#define UART4_GAR_REG_UART4_RST_N_DE_ASSERT   0b1

◆ UART4_GAR_REG_UART4_RST_N_OFFSET

#define UART4_GAR_REG_UART4_RST_N_OFFSET   16

◆ UART5_GAR_REG

#define UART5_GAR_REG   0x00000e14

◆ UART5_GAR_REG_UART5_APB_CLK_EN_CLEAR_MASK

#define UART5_GAR_REG_UART5_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART5_GAR_REG_UART5_APB_CLK_EN_MASK

#define UART5_GAR_REG_UART5_APB_CLK_EN_MASK   0x0

◆ UART5_GAR_REG_UART5_APB_CLK_EN_OFFSET

#define UART5_GAR_REG_UART5_APB_CLK_EN_OFFSET   0

◆ UART5_GAR_REG_UART5_APB_CLK_EN_PASS

#define UART5_GAR_REG_UART5_APB_CLK_EN_PASS   0b1

◆ UART5_GAR_REG_UART5_RST_N_ASSERT

#define UART5_GAR_REG_UART5_RST_N_ASSERT   0b0

◆ UART5_GAR_REG_UART5_RST_N_CLEAR_MASK

#define UART5_GAR_REG_UART5_RST_N_CLEAR_MASK   0x00010000

◆ UART5_GAR_REG_UART5_RST_N_DE_ASSERT

#define UART5_GAR_REG_UART5_RST_N_DE_ASSERT   0b1

◆ UART5_GAR_REG_UART5_RST_N_OFFSET

#define UART5_GAR_REG_UART5_RST_N_OFFSET   16

◆ UART6_GAR_REG

#define UART6_GAR_REG   0x00000e18

◆ UART6_GAR_REG_UART6_APB_CLK_EN_CLEAR_MASK

#define UART6_GAR_REG_UART6_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART6_GAR_REG_UART6_APB_CLK_EN_MASK

#define UART6_GAR_REG_UART6_APB_CLK_EN_MASK   0x0

◆ UART6_GAR_REG_UART6_APB_CLK_EN_OFFSET

#define UART6_GAR_REG_UART6_APB_CLK_EN_OFFSET   0

◆ UART6_GAR_REG_UART6_APB_CLK_EN_PASS

#define UART6_GAR_REG_UART6_APB_CLK_EN_PASS   0b1

◆ UART6_GAR_REG_UART6_RST_N_ASSERT

#define UART6_GAR_REG_UART6_RST_N_ASSERT   0b0

◆ UART6_GAR_REG_UART6_RST_N_CLEAR_MASK

#define UART6_GAR_REG_UART6_RST_N_CLEAR_MASK   0x00010000

◆ UART6_GAR_REG_UART6_RST_N_DE_ASSERT

#define UART6_GAR_REG_UART6_RST_N_DE_ASSERT   0b1

◆ UART6_GAR_REG_UART6_RST_N_OFFSET

#define UART6_GAR_REG_UART6_RST_N_OFFSET   16

◆ UART7_GAR_REG

#define UART7_GAR_REG   0x00000e1c

◆ UART7_GAR_REG_UART7_APB_CLK_EN_CLEAR_MASK

#define UART7_GAR_REG_UART7_APB_CLK_EN_CLEAR_MASK   0x00000001

◆ UART7_GAR_REG_UART7_APB_CLK_EN_MASK

#define UART7_GAR_REG_UART7_APB_CLK_EN_MASK   0x0

◆ UART7_GAR_REG_UART7_APB_CLK_EN_OFFSET

#define UART7_GAR_REG_UART7_APB_CLK_EN_OFFSET   0

◆ UART7_GAR_REG_UART7_APB_CLK_EN_PASS

#define UART7_GAR_REG_UART7_APB_CLK_EN_PASS   0b1

◆ UART7_GAR_REG_UART7_RST_N_ASSERT

#define UART7_GAR_REG_UART7_RST_N_ASSERT   0b0

◆ UART7_GAR_REG_UART7_RST_N_CLEAR_MASK

#define UART7_GAR_REG_UART7_RST_N_CLEAR_MASK   0x00010000

◆ UART7_GAR_REG_UART7_RST_N_DE_ASSERT

#define UART7_GAR_REG_UART7_RST_N_DE_ASSERT   0b1

◆ UART7_GAR_REG_UART7_RST_N_OFFSET

#define UART7_GAR_REG_UART7_RST_N_OFFSET   16

◆ USB0_CLK_REG

#define USB0_CLK_REG   0x00001300

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK   0b01

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000

◆ USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24

◆ USB0_CLK_REG_USB0_CLK12M_SEL_RC_16M_CLK

#define USB0_CLK_REG_USB0_CLK12M_SEL_RC_16M_CLK   0b11

◆ USB0_CLK_REG_USB0_CLK12M_SEL_SYS_32K_CLK

#define USB0_CLK_REG_USB0_CLK12M_SEL_SYS_32K_CLK   0b10

◆ USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1

◆ USB0_CLK_REG_USB0_CLKEN_OFFSET

#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31

◆ USB0_GAR_REG

#define USB0_GAR_REG   0x00001304

◆ USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_CLEAR_MASK

#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_CLEAR_MASK   0x00000100

◆ USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_MASK

#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_MASK   0b0

◆ USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_OFFSET

#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_OFFSET   8

◆ USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_PASS

#define USB0_GAR_REG_USB0_DEV_AHB_CLK_EN_PASS   0b1

◆ USB0_GAR_REG_USB0_DEV_RST_N_ASSERT

#define USB0_GAR_REG_USB0_DEV_RST_N_ASSERT   0b0

◆ USB0_GAR_REG_USB0_DEV_RST_N_CLEAR_MASK

#define USB0_GAR_REG_USB0_DEV_RST_N_CLEAR_MASK   0x01000000

◆ USB0_GAR_REG_USB0_DEV_RST_N_DE_ASSERT

#define USB0_GAR_REG_USB0_DEV_RST_N_DE_ASSERT   0b1

◆ USB0_GAR_REG_USB0_DEV_RST_N_OFFSET

#define USB0_GAR_REG_USB0_DEV_RST_N_OFFSET   24

◆ USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_CLEAR_MASK

#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_CLEAR_MASK   0x00000010

◆ USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_MASK

#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_MASK   0b0

◆ USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_OFFSET

#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_OFFSET   4

◆ USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_PASS

#define USB0_GAR_REG_USB0_EHCI_AHB_CLK_EN_PASS   0b1

◆ USB0_GAR_REG_USB0_EHCI_RST_N_ASSERT

#define USB0_GAR_REG_USB0_EHCI_RST_N_ASSERT   0b0

◆ USB0_GAR_REG_USB0_EHCI_RST_N_CLEAR_MASK

#define USB0_GAR_REG_USB0_EHCI_RST_N_CLEAR_MASK   0x00100000

◆ USB0_GAR_REG_USB0_EHCI_RST_N_DE_ASSERT

#define USB0_GAR_REG_USB0_EHCI_RST_N_DE_ASSERT   0b1

◆ USB0_GAR_REG_USB0_EHCI_RST_N_OFFSET

#define USB0_GAR_REG_USB0_EHCI_RST_N_OFFSET   20

◆ USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_CLEAR_MASK

#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_MASK

#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_MASK   0b0

◆ USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_OFFSET

#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_OFFSET   0

◆ USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_PASS

#define USB0_GAR_REG_USB0_OHCI_AHB_CLK_EN_PASS   0b1

◆ USB0_GAR_REG_USB0_OHCI_RST_N_ASSERT

#define USB0_GAR_REG_USB0_OHCI_RST_N_ASSERT   0b0

◆ USB0_GAR_REG_USB0_OHCI_RST_N_CLEAR_MASK

#define USB0_GAR_REG_USB0_OHCI_RST_N_CLEAR_MASK   0x00010000

◆ USB0_GAR_REG_USB0_OHCI_RST_N_DE_ASSERT

#define USB0_GAR_REG_USB0_OHCI_RST_N_DE_ASSERT   0b1

◆ USB0_GAR_REG_USB0_OHCI_RST_N_OFFSET

#define USB0_GAR_REG_USB0_OHCI_RST_N_OFFSET   16

◆ USB1_CLK_REG

#define USB1_CLK_REG   0x00001308

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_24M_CLK   0b01

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   0x03000000

◆ USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET

#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24

◆ USB1_CLK_REG_USB1_CLK12M_SEL_RC_16M_CLK

#define USB1_CLK_REG_USB1_CLK12M_SEL_RC_16M_CLK   0b11

◆ USB1_CLK_REG_USB1_CLK12M_SEL_SYS_32K_CLK

#define USB1_CLK_REG_USB1_CLK12M_SEL_SYS_32K_CLK   0b10

◆ USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   0x80000000

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0b0

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0b1

◆ USB1_CLK_REG_USB1_CLKEN_OFFSET

#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31

◆ USB1_GAR_REG

#define USB1_GAR_REG   0x0000130c

◆ USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_CLEAR_MASK

#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_CLEAR_MASK   0x00000010

◆ USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_MASK

#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_MASK   0b0

◆ USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_OFFSET

#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_OFFSET   4

◆ USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_PASS

#define USB1_GAR_REG_USB1_EHCI_AHB_CLK_EN_PASS   0b1

◆ USB1_GAR_REG_USB1_EHCI_RST_N_ASSERT

#define USB1_GAR_REG_USB1_EHCI_RST_N_ASSERT   0b0

◆ USB1_GAR_REG_USB1_EHCI_RST_N_CLEAR_MASK

#define USB1_GAR_REG_USB1_EHCI_RST_N_CLEAR_MASK   0x00100000

◆ USB1_GAR_REG_USB1_EHCI_RST_N_DE_ASSERT

#define USB1_GAR_REG_USB1_EHCI_RST_N_DE_ASSERT   0b1

◆ USB1_GAR_REG_USB1_EHCI_RST_N_OFFSET

#define USB1_GAR_REG_USB1_EHCI_RST_N_OFFSET   20

◆ USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_CLEAR_MASK

#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_MASK

#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_MASK   0b0

◆ USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_OFFSET

#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_OFFSET   0

◆ USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_PASS

#define USB1_GAR_REG_USB1_OHCI_AHB_CLK_EN_PASS   0b1

◆ USB1_GAR_REG_USB1_OHCI_RST_N_ASSERT

#define USB1_GAR_REG_USB1_OHCI_RST_N_ASSERT   0b0

◆ USB1_GAR_REG_USB1_OHCI_RST_N_CLEAR_MASK

#define USB1_GAR_REG_USB1_OHCI_RST_N_CLEAR_MASK   0x00010000

◆ USB1_GAR_REG_USB1_OHCI_RST_N_DE_ASSERT

#define USB1_GAR_REG_USB1_OHCI_RST_N_DE_ASSERT   0b1

◆ USB1_GAR_REG_USB1_OHCI_RST_N_OFFSET

#define USB1_GAR_REG_USB1_OHCI_RST_N_OFFSET   16

◆ USB2_GAR_REG

#define USB2_GAR_REG   0x0000135c

◆ USB2_GAR_REG_USB2_RST_N_ASSERT

#define USB2_GAR_REG_USB2_RST_N_ASSERT   0b0

◆ USB2_GAR_REG_USB2_RST_N_CLEAR_MASK

#define USB2_GAR_REG_USB2_RST_N_CLEAR_MASK   0x00010000

◆ USB2_GAR_REG_USB2_RST_N_DE_ASSERT

#define USB2_GAR_REG_USB2_RST_N_DE_ASSERT   0b1

◆ USB2_GAR_REG_USB2_RST_N_OFFSET

#define USB2_GAR_REG_USB2_RST_N_OFFSET   16

◆ USB2_MF_CLK_REG

#define USB2_MF_CLK_REG   0x00001354

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b01

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b00

◆ USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ USB2_MF_CLK_REG_FACTOR_M_OFFSET

#define USB2_MF_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET   31

◆ USB2_SUSPEND_CLK_REG

#define USB2_SUSPEND_CLK_REG   0x00001350

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b1

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_32K_CLK   0b0

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET

#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31

◆ USB2_U2_ONLY_PIPE_CLK_REG

#define USB2_U2_ONLY_PIPE_CLK_REG   0x00001364

◆ USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define USB2_U2_ONLY_PIPE_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_OFFSET

#define USB2_U2_ONLY_PIPE_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLEAR_MASK

#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_OFF

#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_ON

#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_OFFSET

#define USB2_U2_ONLY_PIPE_CLK_REG_USB2_U2_ONLY_PIPE_CLK_GATING_OFFSET   31

◆ USB2_U2_PHY_REF_CLK_REG

#define USB2_U2_PHY_REF_CLK_REG   0x00001348

◆ USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLEAR_MASK

#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_OFF

#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_ON

#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_OFFSET

#define USB2_U2_PHY_REF_CLK_REG_USB2_U2_PHY_REF_CLK_GATING_OFFSET   31

◆ USB2_U3_ONLY_UTMI_CLK_REG

#define USB2_U3_ONLY_UTMI_CLK_REG   0x00001360

◆ USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK

#define USB2_U3_ONLY_UTMI_CLK_REG_CLK_SRC_SEL_SYS_24M_CLK   0b000

◆ USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_OFFSET

#define USB2_U3_ONLY_UTMI_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLEAR_MASK

#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_OFF

#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_ON

#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_OFFSET

#define USB2_U3_ONLY_UTMI_CLK_REG_USB2_U3_ONLY_UTMI_CLK_GATING_OFFSET   31

◆ USB2P0_SYS_GAR_REG

#define USB2P0_SYS_GAR_REG   0x00001344

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_CLEAR_MASK

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_MASK

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_MASK   0b0

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_OFFSET

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_OFFSET   0

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_PASS

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_AHB_CLK_EN_PASS   0b1

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_ASSERT

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_ASSERT   0b0

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_CLEAR_MASK

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_CLEAR_MASK   0x00010000

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_DE_ASSERT

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_DE_ASSERT   0b1

◆ USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_OFFSET

#define USB2P0_SYS_GAR_REG_USB2P0_SYS_RST_N_OFFSET   16

◆ USB2P0_SYS_PHY_REF_CLK_REG

#define USB2P0_SYS_PHY_REF_CLK_REG   0x00001340

◆ USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLEAR_MASK

#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_OFF

#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_ON

#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_OFFSET

#define USB2P0_SYS_PHY_REF_CLK_REG_USB2P0_SYS_PHY_REF_CLK_GATING_OFFSET   31

◆ USBEHCI0_GATIING_BIT

#define USBEHCI0_GATIING_BIT   24

◆ USBEHCI0_RST_BIT

#define USBEHCI0_RST_BIT   24

◆ USBEHCI1_GATIING_BIT

#define USBEHCI1_GATIING_BIT   25

◆ USBEHCI1_RST_BIT

#define USBEHCI1_RST_BIT   25

◆ USBPHY0_RST_BIT

#define USBPHY0_RST_BIT   0

◆ USBPHY0_SCLK_GATING_BIT

#define USBPHY0_SCLK_GATING_BIT   8

◆ USBPHY1_RST_BIT

#define USBPHY1_RST_BIT   1

◆ USBPHY1_SCLK_GATING_BIT

#define USBPHY1_SCLK_GATING_BIT   9

◆ USBPHY_CONFIG_REG

#define USBPHY_CONFIG_REG   0xcc

◆ VE0_CLK_REG

#define VE0_CLK_REG   0x00000a80

◆ VE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VE0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VE0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ VE0_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ VE0_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define VE0_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ VE0_CLK_REG_CLK_SRC_SEL_VEPLL

#define VE0_CLK_REG_CLK_SRC_SEL_VEPLL   0b000

◆ VE0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VE0_CLK_REG_FACTOR_M_OFFSET

#define VE0_CLK_REG_FACTOR_M_OFFSET   0

◆ VE0_CLK_REG_VE0_CLK_GATING_CLEAR_MASK

#define VE0_CLK_REG_VE0_CLK_GATING_CLEAR_MASK   0x80000000

◆ VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_OFF

#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_ON

#define VE0_CLK_REG_VE0_CLK_GATING_CLOCK_IS_ON   0b1

◆ VE0_CLK_REG_VE0_CLK_GATING_OFFSET

#define VE0_CLK_REG_VE0_CLK_GATING_OFFSET   31

◆ VE0_GAR_REG

#define VE0_GAR_REG   0x00000a8c

◆ VE0_GAR_REG_VE0_AHB_CLK_EN_CLEAR_MASK

#define VE0_GAR_REG_VE0_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ VE0_GAR_REG_VE0_AHB_CLK_EN_MASK

#define VE0_GAR_REG_VE0_AHB_CLK_EN_MASK   0x0

◆ VE0_GAR_REG_VE0_AHB_CLK_EN_OFFSET

#define VE0_GAR_REG_VE0_AHB_CLK_EN_OFFSET   0

◆ VE0_GAR_REG_VE0_AHB_CLK_EN_PASS

#define VE0_GAR_REG_VE0_AHB_CLK_EN_PASS   0b1

◆ VE0_GAR_REG_VE0_RST_N_ASSERT

#define VE0_GAR_REG_VE0_RST_N_ASSERT   0b0

◆ VE0_GAR_REG_VE0_RST_N_CLEAR_MASK

#define VE0_GAR_REG_VE0_RST_N_CLEAR_MASK   0x00010000

◆ VE0_GAR_REG_VE0_RST_N_DE_ASSERT

#define VE0_GAR_REG_VE0_RST_N_DE_ASSERT   0b1

◆ VE0_GAR_REG_VE0_RST_N_OFFSET

#define VE0_GAR_REG_VE0_RST_N_OFFSET   16

◆ VEPLL_GATE_EN_REG

#define VEPLL_GATE_EN_REG   0x00001918

◆ VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_AUTO

#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_AUTO   0b0

◆ VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_NO_AUTO

#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_OFFSET

#define VEPLL_GATE_EN_REG_VEPLL_AUTO_GATE_EN_OFFSET   0

◆ VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_DISABLE

#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_DISABLE   0b0

◆ VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_ENABLE

#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_ENABLE   0b1

◆ VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_OFFSET

#define VEPLL_GATE_EN_REG_VEPLL_GATE_SW_CFG_OFFSET   16

◆ VEPLL_GATE_STAT_REG

#define VEPLL_GATE_STAT_REG   0x00001998

◆ VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_CLEAR_MASK

#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_CLEAR_MASK   0x00010000

◆ VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_DISABLE

#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_DISABLE   0b0

◆ VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_ENABLE

#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_ENABLE   0b1

◆ VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_OFFSET

#define VEPLL_GATE_STAT_REG_VEPLL_GATE_STAT_OFFSET   16

◆ VIDEO_IN_GAR_REG

#define VIDEO_IN_GAR_REG   0x00001884

◆ VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_CLEAR_MASK

#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_MASK

#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_MASK   0b0

◆ VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_OFFSET

#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_OFFSET   0

◆ VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_PASS

#define VIDEO_IN_GAR_REG_VIDEO_IN_AHB_CLK_EN_PASS   0b1

◆ VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_ASSERT

#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_ASSERT   0b0

◆ VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_CLEAR_MASK

#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_CLEAR_MASK   0x00010000

◆ VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_DE_ASSERT

#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_DE_ASSERT   0b1

◆ VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_OFFSET

#define VIDEO_IN_GAR_REG_VIDEO_IN_RST_N_OFFSET   16

◆ VIDEO_OUT0_GAR_REG

#define VIDEO_OUT0_GAR_REG   0x000016e4

◆ VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_ASSERT

#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_ASSERT   0b0

◆ VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_CLEAR_MASK

#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_CLEAR_MASK   0x00010000

◆ VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_DE_ASSERT

#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_DE_ASSERT   0b1

◆ VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_OFFSET

#define VIDEO_OUT0_GAR_REG_VIDEO_OUT0_RST_N_OFFSET   16

◆ VIDEOPLL_GATE_EN_REG

#define VIDEOPLL_GATE_EN_REG   0x00001910

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET   4

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET   20

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET   0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET   16

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000020

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET   5

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00200000

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET   21

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET   1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET   17

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK   0x00000040

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET   6

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET   22

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET   2

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET   18

◆ VIDEOPLL_GATE_STAT_REG

#define VIDEOPLL_GATE_STAT_REG   0x00001990

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK   0x00100000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET   20

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK   0x00010000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET   16

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK   0x00200000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET   21

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK   0x00020000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET   17

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK   0x00400000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET   22

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK   0x00040000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET   18

◆ VO0_REG_GAR_REG

#define VO0_REG_GAR_REG   0x000016c4

◆ VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_CLEAR_MASK

#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_MASK

#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_MASK   0b0

◆ VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_OFFSET

#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_OFFSET   0

◆ VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_PASS

#define VO0_REG_GAR_REG_VO0_REG_AHB_CLK_EN_PASS   0b1

◆ VO0_REG_GAR_REG_VO0_REG_RST_N_ASSERT

#define VO0_REG_GAR_REG_VO0_REG_RST_N_ASSERT   0b0

◆ VO0_REG_GAR_REG_VO0_REG_RST_N_CLEAR_MASK

#define VO0_REG_GAR_REG_VO0_REG_RST_N_CLEAR_MASK   0x00010000

◆ VO0_REG_GAR_REG_VO0_REG_RST_N_DE_ASSERT

#define VO0_REG_GAR_REG_VO0_REG_RST_N_DE_ASSERT   0b1

◆ VO0_REG_GAR_REG_VO0_REG_RST_N_OFFSET

#define VO0_REG_GAR_REG_VO0_REG_RST_N_OFFSET   16

◆ VO1_REG_GAR_REG

#define VO1_REG_GAR_REG   0x000016cc

◆ VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_CLEAR_MASK

#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_CLEAR_MASK   0x00000001

◆ VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_MASK

#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_MASK   0b0

◆ VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_OFFSET

#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_OFFSET   0

◆ VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_PASS

#define VO1_REG_GAR_REG_VO1_REG_AHB_CLK_EN_PASS   0b1

◆ VO1_REG_GAR_REG_VO1_REG_RST_N_ASSERT

#define VO1_REG_GAR_REG_VO1_REG_RST_N_ASSERT   0b0

◆ VO1_REG_GAR_REG_VO1_REG_RST_N_CLEAR_MASK

#define VO1_REG_GAR_REG_VO1_REG_RST_N_CLEAR_MASK   0x00010000

◆ VO1_REG_GAR_REG_VO1_REG_RST_N_DE_ASSERT

#define VO1_REG_GAR_REG_VO1_REG_RST_N_DE_ASSERT   0b1

◆ VO1_REG_GAR_REG_VO1_REG_RST_N_OFFSET

#define VO1_REG_GAR_REG_VO1_REG_RST_N_OFFSET   16
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