da/d09/chips_2sun60iw2_2reg-ccu_8h_source.html

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * (C) Copyright 2013-2025

 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>

 *

 * original from bsp uboot defines

 */


#ifndef __SUN60IW2_REG_CCU_H__

#define __SUN60IW2_REG_CCU_H__


#include <reg-ncat.h>


#define PLL_REF_CTRL_REG 0x00000000//PLL_REF Control Register

#define PLL_REF_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_REF_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_REF_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_REF_CTRL_REG_LOCK_OFFSET 28

#define PLL_REF_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_REF_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET 24

#define PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK (0x01000000)

#define PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE 0b0

#define PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE 0b1

#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16

#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000)

#define PLL_REF_CTRL_REG_PLL_N_OFFSET 8

#define PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_REF_LOCK_CTRL_REG 0x00000004//PLL_REF Lock Control Register

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET 4

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING 0b1

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET 0

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_REF_BIAS_REG 0x00000010//PLL_REF Bias Register

#define PLL_REF_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_DDR_CTRL_REG 0x00000020//PLL_DDR Control Register

#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28

#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)

#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8

#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_DDR_LOCK_CTRL_REG 0x00000024//PLL_DDR Lock Control Register

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET 4

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING 0b1

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET 0

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_DDR_PAT0_CTRL_REG 0x00000028//PLL_DDR Pattern0 Control Register

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_DDR_PAT1_CTRL_REG 0x0000002c//PLL_DDR Pattern1 Control Register

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_DDR_BIAS_REG 0x00000030//PLL_DDR Bias Register

#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_PERI0_CTRL_REG 0x000000a0//PLL_PERI0 Control Register

#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28

#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000)

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE 0b0

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE 0b1

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8

#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c)

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_PERI0_LOCK_CTRL_REG 0x000000a4//PLL_PERI0 Lock Control Register

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET 4

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING 0b1

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET 0

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8//PLL_PERI0 Pattern0 Control Register

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac//PLL_PERI0 Pattern1 Control Register

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_PERI0_BIAS_REG 0x00000b0//PLL_)PERI0 Bias Register

#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_PERI1_CTRL_REG 0x000000c0//PLL_PERI1 Control Register

#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28

#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000)

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE 0b0

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE 0b1

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8

#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c)

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_PERI1_LOCK_CTRL_REG 0x000000c4//PLL_PERI1 Lock Control Register

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET 4

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING 0b1

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET 0

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8//PLL_PERI1 Pattern0 Control Register

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc//PLL_PERI1 Pattern1 Control Register

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_PERI1_BIAS_REG 0x000000d0//PLL_PERI1 Bias Register

#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_GPU0_CTRL_REG 0x000000e0//PLL_GPU0 Control Register

#define PLL_GPU0_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_GPU0_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_GPU0_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_GPU0_CTRL_REG_LOCK_OFFSET 28

#define PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_GPU0_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)

#define PLL_GPU0_CTRL_REG_PLL_N_OFFSET 8

#define PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_GPU0_LOCK_CTRL_REG 0x000000e4//PLL_GPU0 Lock Control Register

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET 4

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING 0b1

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET 0

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_GPU0_PAT0_CTRL_REG 0x000000e8//PLL_GPU0 Pattern0 Control Register

#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_GPU0_PAT1_CTRL_REG 0x000000ec//PLL_GPU0 Pattern1 Control Register

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_GPU0_BIAS_REG 0x000000f0//PLL_GPU0 Bias Register

#define PLL_GPU0_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_VIDEO0_CTRL_REG 0x00000120//PLL_VIDEO0 Control Register

#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28

#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8

#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_VIDEO0_LOCK_CTRL_REG 0x00000124//PLL_VIDEO0 Lock Control Register

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET 4

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING 0b1

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET 0

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128//PLL_VIDEO0 Pattern0 Control Register

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c//PLL_VIDEO0 Pattern1 Control Register

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO0_BIAS_REG 0x00000130//PLL_VIDEO0 Bias Register

#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_VIDEO1_CTRL_REG 0x00000140//PLL_VIDEO1 Control Register

#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28

#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8

#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_VIDEO1_LOCK_CTRL_REG 0x00000144//PLL_VIDEO1 Lock Control Register

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET 4

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING 0b1

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET 0

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148//PLL_VIDEO1 Pattern0 Control Register

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c//PLL_VIDEO1 Pattern1 Control Register

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO1_BIAS_REG 0x00000150//PLL_VIDEO1 Bias Register

#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_VIDEO2_CTRL_REG 0x00000160//PLL_VIDEO2 Control Register

#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28

#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8

#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_VIDEO2_LOCK_CTRL_REG 0x00000164//PLL_VIDEO2 Lock Control Register

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET 4

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING 0b1

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET 0

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_VIDEO2_PAT0_CTRL_REG 0x00000168//PLL_VIDEO2 Pattern0 Control Register

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO2_PAT1_CTRL_REG 0x0000016c//PLL_VIDEO2 Pattern1 Control Register

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_VIDEO2_BIAS_REG 0x00000170//PLL_VIDEO2 Bias Register

#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_VE0_CTRL_REG 0x00000220//PLL_VE0 Control Register

#define PLL_VE0_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_VE0_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_VE0_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_VE0_CTRL_REG_LOCK_OFFSET 28

#define PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_VE0_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)

#define PLL_VE0_CTRL_REG_PLL_N_OFFSET 8

#define PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_VE0_LOCK_CTRL_REG 0x00000224//PLL_VE0 Lock Control Register

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET 4

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING 0b1

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET 0

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_VE0_PAT0_CTRL_REG 0x00000228//PLL_VE0 Pattern0 Control Register

#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_VE0_PAT1_CTRL_REG 0x0000022c//PLL_VE0 Pattern1 Control Register

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_VE0_BIAS_REG 0x00000230//PLL_VE0 Bias Register

#define PLL_VE0_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_VE1_CTRL_REG 0x00000240//PLL_VE1 Control Register

#define PLL_VE1_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_VE1_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_VE1_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_VE1_CTRL_REG_LOCK_OFFSET 28

#define PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_VE1_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)

#define PLL_VE1_CTRL_REG_PLL_N_OFFSET 8

#define PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_VE1_LOCK_CTRL_REG 0x00000244//PLL_VE1 Lock Control Register

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET 4

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING 0b1

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET 0

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_VE1_PAT0_CTRL_REG 0x00000248//PLL_VE1 Pattern0 Control Register

#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_VE1_PAT1_CTRL_REG 0x0000024c//PLL_VE1 Pattern1 Control Register

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_VE1_BIAS_REG 0x00000250//PLL_VE1 Bias Register

#define PLL_VE1_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_AUDIO0_CTRL_REG 0x00000260//PLL_AUDIO0 Control Register

#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28

#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000)

#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8

#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_AUDIO0_LOCK_CTRL_REG 0x00000264//PLL_AUDIO0 Lock Control Register

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET 4

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING 0b1

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET 0

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268//PLL_AUDIO0 Pattern0 Control Register

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c//PLL_AUDIO0 Pattern1 Control Register

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_AUDIO0_BIAS_REG 0x00000270//PLL_AUDIO0 Bias Register

#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_AUDIO1_CTRL_REG 0x00000280//PLL_AUDIO1 Control Register

#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28

#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET 20

#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK (0x00700000)

#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET 16

#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK (0x00070000)

#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8

#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_AUDIO1_LOCK_CTRL_REG 0x00000284//PLL_AUDIO1 Lock Control Register

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_OFFSET 4

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_PENDING 0b1

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_OFFSET 0

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_AUDIO1_PAT0_CTRL_REG 0x00000288//PLL_AUDIO1 Pattern0 Control Register

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_AUDIO1_PAT1_CTRL_REG 0x0000028c//PLL_AUDIO1 Pattern1 Control Register

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_AUDIO1_BIAS_REG 0x00000290//PLL_AUDIO1 Bias Register

#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_NPU_CTRL_REG 0x000002a0//PLL_NPU Control Register

#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_NPU_CTRL_REG_LOCK_OFFSET 28

#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)

#define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8

#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_NPU_LOCK_CTRL_REG 0x000002a4//PLL_NPU Lock Control Register

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET 4

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING 0b1

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET 0

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_NPU_PAT0_CTRL_REG 0x000002a8//PLL_NPU Pattern0 Control Register

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_NPU_PAT1_CTRL_REG 0x000002ac//PLL_NPU Pattern1 Control Register

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_NPU_BIAS_REG 0x000002b0//PLL_NPU Bias Register

#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define PLL_DE_CTRL_REG 0x000002e0//PLL_DE Control Register

#define PLL_DE_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)

#define PLL_DE_CTRL_REG_PLL_EN_DISABLE 0b0

#define PLL_DE_CTRL_REG_PLL_EN_ENABLE 0b1

#define PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)

#define PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)

#define PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define PLL_DE_CTRL_REG_LOCK_OFFSET 28

#define PLL_DE_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)

#define PLL_DE_CTRL_REG_LOCK_UNLOCKED 0b0

#define PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE 0b0

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE 0b1

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE 0b0

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE 0b1

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET 24

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC 0b0

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL 0b1

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)

#define PLL_DE_CTRL_REG_PLL_N_OFFSET 8

#define PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET 1

#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)


#define PLL_DE_LOCK_CTRL_REG 0x000002e4//PLL_DE Lock Control Register

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET 4

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK (0x00000010)

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT 0b0

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING 0b1

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET 0

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE 0b0

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE 0b1


#define PLL_DE_PAT0_CTRL_REG 0x000002e8//PLL_DE Pattern0 Control Register

#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP 0b0

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN 0b1

#define PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET 17

#define PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)

#define PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)


#define PLL_DE_PAT1_CTRL_REG 0x000002ec//PLL_DE Pattern1 Control Register

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE 0b0

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE 0b1

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_8UA 0b000

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_16UA 0b001

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_24UA 0b010

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_32UA 0b011

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_40UA 0b100

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_48UA 0b101

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_56UA 0b110

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_64UA 0b111

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY 0b0

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY 0b1

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE 0b0

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE 0b1

#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)

#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)

#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)


#define PLL_DE_BIAS_REG 0x000002f0//PLL_DE Bias Register

#define PLL_DE_BIAS_REG_PLL_CP_OFFSET 16

#define PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)


#define AHB_CLK_REG 0x00000500//AHB Clock Register

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)

#define AHB_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00

#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define AHB_CLK_REG_FACTOR_M_OFFSET 0

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define APB0_CLK_REG 0x00000510//APB0 Clock Register

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)

#define APB0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00

#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define APB0_CLK_REG_FACTOR_M_OFFSET 0

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define APB1_CLK_REG 0x00000518//APB1 Clock Register

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)

#define APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b00

#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define APB1_CLK_REG_FACTOR_M_OFFSET 0

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define APB_UART_CLK_REG 0x00000538//APB_UART Clock Register

#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100

#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0

#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define TRACE_CLK_REG 0x00000540//TRACE Clock Register

#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK (0x80000000)

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0b0

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0b1

#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TRACE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100

#define TRACE_CLK_REG_FACTOR_M_OFFSET 0

#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define GIC_CLK_REG 0x00000560//GIC Clock Register

#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31

#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK (0x80000000)

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0b0

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0b1

#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define GIC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100

#define GIC_CLK_REG_FACTOR_M_OFFSET 0

#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CPU_PERI_CLK_REG 0x00000568//CPU_PERI Clock Register

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_OFFSET 31

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLEAR_MASK (0x80000000)

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_OFF 0b0

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_ON 0b1

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b100

#define CPU_PERI_CLK_REG_FACTOR_M_OFFSET 0

#define CPU_PERI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define ITS0_BGR_REG 0x00000574//ITS0 Bus Gating Reset Register

#define ITS0_BGR_REG_ITS_PCIE0_RST_OFFSET 16

#define ITS0_BGR_REG_ITS_PCIE0_RST_CLEAR_MASK (0x00010000)

#define ITS0_BGR_REG_ITS_PCIE0_RST_ASSERT 0b0

#define ITS0_BGR_REG_ITS_PCIE0_RST_DE_ASSERT 0b1

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_OFFSET 1

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_CLEAR_MASK (0x00000002)

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_MASK 0b0

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_PASS 0b1


#define NSI_CLK_REG 0x00000580//NSI Clock Register

#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31

#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK (0x80000000)

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1

#define NSI_CLK_REG_NSI_RST_OFFSET 30

#define NSI_CLK_REG_NSI_RST_CLEAR_MASK (0x40000000)

#define NSI_CLK_REG_NSI_RST_ASSERT 0b0

#define NSI_CLK_REG_NSI_RST_DE_ASSERT 0b1

#define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28

#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK (0x10000000)

#define NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0

#define NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1

#define NSI_CLK_REG_NSI_UPD_OFFSET 27

#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK (0x08000000)

#define NSI_CLK_REG_NSI_UPD_INVALID 0b0

#define NSI_CLK_REG_NSI_UPD_VALID 0b1

#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24

#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK (0x07000000)

#define NSI_CLK_REG_NSI_CLK_SEL_SYS_CLK24M 0b000

#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL 0b001

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M 0b010

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M 0b011

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b100

#define NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X 0b101

#define NSI_CLK_REG_NSI_DIV1_OFFSET 0

#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK (0x0000001f)


#define NSI_BGR_REG 0x00000584//NSI Bus Gating Reset Register

#define NSI_BGR_REG_NSI_CFG_RST_OFFSET 16

#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK (0x00010000)

#define NSI_BGR_REG_NSI_CFG_RST_ASSERT 0b0

#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT 0b1

#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0

#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK (0x00000001)

#define NSI_BGR_REG_NSI_CFG_GATING_MASK 0b0

#define NSI_BGR_REG_NSI_CFG_GATING_PASS 0b1


#define MBUS_CLK_REG 0x00000588//MBUS Clock Register

#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK (0x80000000)

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1

#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28

#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK (0x10000000)

#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0

#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1

#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27

#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK (0x08000000)

#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0

#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1

#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24

#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK (0x07000000)

#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_CLK24M 0b000

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M 0b001

#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL 0b010

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b011

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b100

#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL 0b101

#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0

#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK (0x0000001f)


#define IOMMU0_BGR_REG 0x0000058c//IOMMU0 Bus Gating Reset Register

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_OFFSET 16

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_CLEAR_MASK (0x00010000)

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_ASSERT 0b0

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_DE_ASSERT 0b1

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_OFFSET 2

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_CLEAR_MASK (0x00000004)

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_MASK 0b0

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_PASS 0b1

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_OFFSET 1

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_CLEAR_MASK (0x00000002)

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_MASK 0b0

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_PASS 0b1

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_OFFSET 0

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_CLEAR_MASK (0x00000001)

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_MASK 0b0

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_PASS 0b1


#define MSI_LITE0_BGR_REG 0x00000594//MSI_LITE0 Bus Gating Reset Register

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_OFFSET 17

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_CLEAR_MASK (0x00020000)

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_ASSERT 0b0

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_DE_ASSERT 0b1

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_OFFSET 16

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_CLEAR_MASK (0x00010000)

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_ASSERT 0b0

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_DE_ASSERT 0b1

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET 0

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK (0x00000001)

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK 0b0

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS 0b1


#define MSI_LITE1_BGR_REG 0x0000059c//MSI_LITE1 Bus Gating Reset Register

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_OFFSET 17

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_CLEAR_MASK (0x00020000)

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_ASSERT 0b0

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_DE_ASSERT 0b1

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_OFFSET 16

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_CLEAR_MASK (0x00010000)

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_ASSERT 0b0

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_DE_ASSERT 0b1

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET 0

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK (0x00000001)

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK 0b0

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS 0b1


#define MSI_LITE2_BGR_REG 0x000005a4//MSI_LITE2 Bus Gating Reset Register

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_OFFSET 17

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_CLEAR_MASK (0x00020000)

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_ASSERT 0b0

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_DE_ASSERT 0b1

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_OFFSET 16

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_CLEAR_MASK (0x00010000)

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_ASSERT 0b0

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_DE_ASSERT 0b1

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_OFFSET 0

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_CLEAR_MASK (0x00000001)

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_MASK 0b0

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_PASS 0b1


#define IOMMU1_BGR_REG 0x000005b4//IOMMU1 Bus Gating Reset Register

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_OFFSET 16

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_CLEAR_MASK (0x00010000)

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_ASSERT 0b0

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_DE_ASSERT 0b1

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_OFFSET 2

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_CLEAR_MASK (0x00000004)

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_MASK 0b0

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_PASS 0b1

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_OFFSET 1

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_CLEAR_MASK (0x00000002)

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_MASK 0b0

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_PASS 0b1

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_OFFSET 0

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_CLEAR_MASK (0x00000001)

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_MASK 0b0

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_PASS 0b1


#define AHB_MAT_CLK_GATING_REG 0x000005c0//AHB Master Clock Gating Register

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_OFFSET 31

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_CLEAR_MASK (0x80000000)

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_OFFSET 29

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_CLEAR_MASK (0x20000000)

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK (0x10000000)

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_OFFSET 24

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_CLEAR_MASK (0x01000000)

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_OFFSET 16

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_OFFSET 9

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000200)

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_OFFSET 8

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000100)

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_OFFSET 7

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000080)

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_OFFSET 6

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000040)

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_OFFSET 5

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000020)

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_OFFSET 4

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000010)

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_OFFSET 3

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000008)

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000004)

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET 1

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000002)

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE 0b1

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET 0

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000001)

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE 0b0

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE 0b1


#define MBUS_MAT_CLK_GATING_REG 0x000005e0//MBUS Master Clock Gating Register

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET 31

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK (0x80000000)

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_OFFSET 30

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_CLEAR_MASK (0x40000000)

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET 29

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x20000000)

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET 28

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK (0x10000000)

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 24

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK (0x01000000)

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 18

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00040000)

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET 16

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET 14

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00004000)

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET 12

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00001000)

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET 11

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000800)

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_OFFSET 1

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000002)

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_ENABLE 0b1

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_OFFSET 0

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000001)

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_DISABLE 0b0

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_ENABLE 0b1


#define MBUS_GATE_EN_REG 0x000005e4//MBUS Gate Enable Register

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_OFFSET 18

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_CLEAR_MASK (0x00040000)

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET 12

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK (0x00001000)

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET 11

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK (0x00000800)

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET 9

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK (0x00000200)

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET 8

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK (0x00000100)

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_OFFSET 5

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_CLEAR_MASK (0x00000020)

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET 3

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK (0x00000008)

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET 2

#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK (0x00000004)

#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG 0b1

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_OFFSET 1

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_CLEAR_MASK (0x00000002)

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_PASS 0b1

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET 0

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK (0x00000001)

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK 0b0

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS 0b1


#define DMA0_BGR_REG 0x00000704//DMA0 Bus Gating Reset Register

#define DMA0_BGR_REG_DMA0_RST_OFFSET 16

#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK (0x00010000)

#define DMA0_BGR_REG_DMA0_RST_ASSERT 0b0

#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT 0b1

#define DMA0_BGR_REG_DMA0_GATING_OFFSET 0

#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK (0x00000001)

#define DMA0_BGR_REG_DMA0_GATING_MASK 0b0

#define DMA0_BGR_REG_DMA0_GATING_PASS 0b1


#define DMA1_BGR_REG 0x0000070c//DMA1 Bus Gating Reset Register

#define DMA1_BGR_REG_DMA1_RST_OFFSET 16

#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK (0x00010000)

#define DMA1_BGR_REG_DMA1_RST_ASSERT 0b0

#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT 0b1

#define DMA1_BGR_REG_DMA1_GATING_OFFSET 0

#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK (0x00000001)

#define DMA1_BGR_REG_DMA1_GATING_MASK 0b0

#define DMA1_BGR_REG_DMA1_GATING_PASS 0b1


#define SPINLOCK_BGR_REG 0x00000724//SPINLOCK Bus Gating Reset Register

#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16

#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK (0x00010000)

#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0b0

#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0b1

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK (0x00000001)

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0b0

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0b1


#define MSGBOX0_BGR_REG 0x00000744//MSGBOX0 Bus Gating Reset Register

#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16

#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK (0x00010000)

#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT 0b0

#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT 0b1

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK (0x00000001)

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK 0b0

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS 0b1


#define PWM0_BGR_REG 0x00000784//PWM0 Bus Gating Reset Register

#define PWM0_BGR_REG_PWM0_RST_OFFSET 16

#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK (0x00010000)

#define PWM0_BGR_REG_PWM0_RST_ASSERT 0b0

#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT 0b1

#define PWM0_BGR_REG_PWM0_GATING_OFFSET 0

#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK (0x00000001)

#define PWM0_BGR_REG_PWM0_GATING_MASK 0b0

#define PWM0_BGR_REG_PWM0_GATING_PASS 0b1


#define PWM1_BGR_REG 0x0000078c//PWM1 Bus Gating Reset Register

#define PWM1_BGR_REG_PWM1_RST_OFFSET 16

#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK (0x00010000)

#define PWM1_BGR_REG_PWM1_RST_ASSERT 0b0

#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT 0b1

#define PWM1_BGR_REG_PWM1_GATING_OFFSET 0

#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK (0x00000001)

#define PWM1_BGR_REG_PWM1_GATING_MASK 0b0

#define PWM1_BGR_REG_PWM1_GATING_PASS 0b1


#define DBGSYS_BGR_REG 0x000007a4//DBGSYS Bus Gating Reset Register

#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16

#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK (0x00010000)

#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0b0

#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0b1

#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0

#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK (0x00000001)

#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0b0

#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0b1


#define SYSDAP_BGR_REG 0x000007ac//SYSDAP Bus Gating Reset Register

#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16

#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK (0x00010000)

#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0b0

#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG 0b1

#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0

#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK (0x00000001)

#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0b0

#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG 0b1


#define TIMER0_CLK0_CLK_REG 0x00000800//TIMER0_CLK0 Clock Register

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET 31

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK0_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK0_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK0_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK0_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK0_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK0_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK0_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK0_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK1_CLK_REG 0x00000804//TIMER0_CLK1 Clock Register

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET 31

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK1_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK1_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK1_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK1_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK1_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK1_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK1_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK1_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK2_CLK_REG 0x00000808//TIMER0_CLK2 Clock Register

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET 31

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK2_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK2_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK2_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK2_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK2_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK2_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK2_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK2_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK3_CLK_REG 0x0000080c//TIMER0_CLK3 Clock Register

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET 31

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK3_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK3_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK3_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK3_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK3_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK3_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK3_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK3_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK4_CLK_REG 0x00000810//TIMER0_CLK4 Clock Register

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET 31

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK4_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK4_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK4_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK4_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK4_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK4_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK4_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK4_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK5_CLK_REG 0x00000814//TIMER0_CLK5 Clock Register

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET 31

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK5_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK5_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK5_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK5_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK5_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK5_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK5_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK5_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK6_CLK_REG 0x00000818//TIMER0_CLK6 Clock Register

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET 31

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK6_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK6_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK6_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK6_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK6_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK6_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK6_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK6_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK7_CLK_REG 0x0000081c//TIMER0_CLK7 Clock Register

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET 31

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK7_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK7_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK7_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK7_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK7_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK7_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK7_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK7_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK8_CLK_REG 0x00000820//TIMER0_CLK8 Clock Register

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET 31

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK8_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK8_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK8_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK8_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK8_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK8_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK8_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK8_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_CLK9_CLK_REG 0x00000824//TIMER0_CLK9 Clock Register

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET 31

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK (0x80000000)

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE 0b0

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE 0b1

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC 0b100

#define TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET 0

#define TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)

#define TIMER0_CLK9_CLK_REG_FACTOR_P__1 0b000

#define TIMER0_CLK9_CLK_REG_FACTOR_P__2 0b001

#define TIMER0_CLK9_CLK_REG_FACTOR_P__4 0b010

#define TIMER0_CLK9_CLK_REG_FACTOR_P__8 0b011

#define TIMER0_CLK9_CLK_REG_FACTOR_P__16 0b100

#define TIMER0_CLK9_CLK_REG_FACTOR_P__32 0b101

#define TIMER0_CLK9_CLK_REG_FACTOR_P__64 0b110

#define TIMER0_CLK9_CLK_REG_FACTOR_P__128 0b111


#define TIMER0_BGR_REG 0x00000850//TIMER0 Bus Gating Reset Register

#define TIMER0_BGR_REG_TIMER0_RST_OFFSET 16

#define TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK (0x00010000)

#define TIMER0_BGR_REG_TIMER0_RST_ASSERT 0b0

#define TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT 0b1

#define TIMER0_BGR_REG_TIMER0_GATING_OFFSET 0

#define TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK (0x00000001)

#define TIMER0_BGR_REG_TIMER0_GATING_MASK 0b0

#define TIMER0_BGR_REG_TIMER0_GATING_PASS 0b1


#define AVS_CLK_REG 0x00000880//AVS Clock Register

#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET 31

#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK (0x80000000)

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF 0b0

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON 0b1

#define AVS_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define AVS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define AVS_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define AVS_CLK_REG_CLK_SRC_SEL_HOSC 0b001


#define DE0_CLK_REG 0x00000a00//DE0 Clock Register

#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31

#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK (0x80000000)

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1

#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b000

#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X 0b001

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b100

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b110

#define DE0_CLK_REG_FACTOR_M_OFFSET 0

#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define DE0_BGR_REG 0x00000a04//DE0 Bus Gating Reset Register

#define DE0_BGR_REG_DE0_RST_OFFSET 16

#define DE0_BGR_REG_DE0_RST_CLEAR_MASK (0x00010000)

#define DE0_BGR_REG_DE0_RST_ASSERT 0b0

#define DE0_BGR_REG_DE0_RST_DE_ASSERT 0b1

#define DE0_BGR_REG_DE0_GATING_OFFSET 0

#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK (0x00000001)

#define DE0_BGR_REG_DE0_GATING_MASK 0b0

#define DE0_BGR_REG_DE0_GATING_PASS 0b1


#define DI_CLK_REG 0x00000a20//DI Clock Register

#define DI_CLK_REG_DI_CLK_GATING_OFFSET 31

#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK (0x80000000)

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF 0b0

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON 0b1

#define DI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define DI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b100

#define DI_CLK_REG_FACTOR_M_OFFSET 0

#define DI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define DI_BGR_REG 0x00000a24//DI Bus Gating Reset Register

#define DI_BGR_REG_DI_RST_OFFSET 16

#define DI_BGR_REG_DI_RST_CLEAR_MASK (0x00010000)

#define DI_BGR_REG_DI_RST_ASSERT 0b0

#define DI_BGR_REG_DI_RST_DE_ASSERT 0b1

#define DI_BGR_REG_DI_GATING_OFFSET 0

#define DI_BGR_REG_DI_GATING_CLEAR_MASK (0x00000001)

#define DI_BGR_REG_DI_GATING_MASK 0b0

#define DI_BGR_REG_DI_GATING_PASS 0b1


#define G2D_CLK_REG 0x00000a40//G2D Clock Register

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK (0x80000000)

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b010

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b011

#define G2D_CLK_REG_FACTOR_M_OFFSET 0

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define G2D_BGR_REG 0x00000a44//G2D Bus Gating Reset Register

#define G2D_BGR_REG_G2D_RST_OFFSET 16

#define G2D_BGR_REG_G2D_RST_CLEAR_MASK (0x00010000)

#define G2D_BGR_REG_G2D_RST_ASSERT 0b0

#define G2D_BGR_REG_G2D_RST_DE_ASSERT 0b1

#define G2D_BGR_REG_G2D_GATING_OFFSET 0

#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK (0x00000001)

#define G2D_BGR_REG_G2D_GATING_MASK 0b0

#define G2D_BGR_REG_G2D_GATING_PASS 0b1


#define EINK_CLK_REG 0x00000a60//EINK Clock Register

#define EINK_CLK_REG_EINK_CLK_GATING_OFFSET 31

#define EINK_CLK_REG_EINK_CLK_GATING_CLEAR_MASK (0x80000000)

#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_OFF 0b0

#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_ON 0b1

#define EINK_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define EINK_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define EINK_CLK_REG_FACTOR_M_OFFSET 0

#define EINK_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define EINK_PANEL_CLK_REG 0x00000a64//EINK PANEL Clock Register

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET 31

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK (0x80000000)

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF 0b0

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON 0b1

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b001

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b010

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b011

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b100

#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET 0

#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define EINK_BGR_REG 0x00000a6c//EINK Bus Gating Reset Register

#define EINK_BGR_REG_EINK_RST_OFFSET 16

#define EINK_BGR_REG_EINK_RST_CLEAR_MASK (0x00010000)

#define EINK_BGR_REG_EINK_RST_ASSERT 0b0

#define EINK_BGR_REG_EINK_RST_DE_ASSERT 0b1

#define EINK_BGR_REG_EINK_GATING_OFFSET 0

#define EINK_BGR_REG_EINK_GATING_CLEAR_MASK (0x00000001)

#define EINK_BGR_REG_EINK_GATING_MASK 0b0

#define EINK_BGR_REG_EINK_GATING_PASS 0b1


#define DE_SYS_BGR_REG 0x00000a74//DE_SYS Bus Gating Reset Register

#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16

#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK (0x00010000)

#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT 0b0

#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT 0b1


#define VE_ENC0_CLK_REG 0x00000a80//VE_ENC0 Clock Register

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET 31

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK (0x80000000)

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF 0b0

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON 0b1

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL 0b000

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL 0b001

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b010

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b101

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL 0b110

#define VE_ENC0_CLK_REG_FACTOR_M_OFFSET 0

#define VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VE_DEC_CLK_REG 0x00000a88//VE_DEC Clock Register

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET 31

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK (0x80000000)

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF 0b0

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON 0b1

#define VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL 0b000

#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL 0b001

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b010

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

#define VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b101

#define VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL 0b110

#define VE_DEC_CLK_REG_FACTOR_M_OFFSET 0

#define VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VE_BGR_REG 0x00000a8c//VE Bus Gating Reset Register

#define VE_BGR_REG_VE_DEC_RST_OFFSET 18

#define VE_BGR_REG_VE_DEC_RST_CLEAR_MASK (0x00040000)

#define VE_BGR_REG_VE_DEC_RST_ASSERT 0b0

#define VE_BGR_REG_VE_DEC_RST_DE_ASSERT 0b1

#define VE_BGR_REG_VE_ENC0_RST_OFFSET 16

#define VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK (0x00010000)

#define VE_BGR_REG_VE_ENC0_RST_ASSERT 0b0

#define VE_BGR_REG_VE_ENC0_RST_DE_ASSERT 0b1

#define VE_BGR_REG_VE_DEC_GATING_OFFSET 2

#define VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK (0x00000004)

#define VE_BGR_REG_VE_DEC_GATING_MASK 0b0

#define VE_BGR_REG_VE_DEC_GATING_PASS 0b1

#define VE_BGR_REG_VE_ENC0_GATING_OFFSET 0

#define VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK (0x00000001)

#define VE_BGR_REG_VE_ENC0_GATING_MASK 0b0

#define VE_BGR_REG_VE_ENC0_GATING_PASS 0b1


#define CE_CLK_REG 0x00000ac0//CE Clock Register

#define CE_CLK_REG_CE_CLK_GATING_OFFSET 31

#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK (0x80000000)

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0b0

#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG 0b1

#define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define CE_CLK_REG_FACTOR_M_OFFSET 0

#define CE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CE_BGR_REG 0x00000ac4//CE Bus Gating Reset Register

#define CE_BGR_REG_CE_SYS_RST_OFFSET 17

#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK (0x00020000)

#define CE_BGR_REG_CE_SYS_RST_ASSERT 0b0

#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG 0b1

#define CE_BGR_REG_CE_RST_OFFSET 16

#define CE_BGR_REG_CE_RST_CLEAR_MASK (0x00010000)

#define CE_BGR_REG_CE_RST_ASSERT 0b0

#define CE_BGR_REG_CE_RST_SECURE_DEBUG 0b1

#define CE_BGR_REG_CE_SYS_GATING_OFFSET 1

#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK (0x00000002)

#define CE_BGR_REG_CE_SYS_GATING_MASK 0b0

#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG 0b1

#define CE_BGR_REG_CE_GATING_OFFSET 0

#define CE_BGR_REG_CE_GATING_CLEAR_MASK (0x00000001)

#define CE_BGR_REG_CE_GATING_MASK 0b0

#define CE_BGR_REG_CE_GATING_SECURE_DEBUG 0b1


#define NPU_CLK_REG 0x00000b00//NPU) Clock Register

#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31

#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK (0x80000000)

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0b0

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0b1

#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL 0b000

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011

#define NPU_CLK_REG_CLK_SRC_SEL_VE0PLL 0b100

#define NPU_CLK_REG_CLK_SRC_SEL_VE1PLL 0b101

#define NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X 0b110

#define NPU_CLK_REG_FACTOR_M_OFFSET 0

#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define NPU_BGR_REG 0x00000b04//NPU) Bus Gating Reset Register

#define NPU_BGR_REG_NPU_SRAM_RST_OFFSET 19

#define NPU_BGR_REG_NPU_SRAM_RST_CLEAR_MASK (0x00080000)

#define NPU_BGR_REG_NPU_SRAM_RST_ASSERT 0b0

#define NPU_BGR_REG_NPU_SRAM_RST_DE_ASSERT 0b1

#define NPU_BGR_REG_NPU_AHB_RST_OFFSET 18

#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK (0x00040000)

#define NPU_BGR_REG_NPU_AHB_RST_ASSERT 0b0

#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT 0b1

#define NPU_BGR_REG_NPU_AXI_RST_OFFSET 17

#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK (0x00020000)

#define NPU_BGR_REG_NPU_AXI_RST_ASSERT 0b0

#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT 0b1

#define NPU_BGR_REG_NPU_CORE_RST_OFFSET 16

#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK (0x00010000)

#define NPU_BGR_REG_NPU_CORE_RST_ASSERT 0b0

#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT 0b1

#define NPU_BGR_REG_NPU_GATING_OFFSET 0

#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK (0x00000001)

#define NPU_BGR_REG_NPU_GATING_MASK 0b0

#define NPU_BGR_REG_NPU_GATING_PASS 0b1


#define DRAM0_CLK_REG 0x00000c00//DRAM0 Clock Register

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET 31

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK (0x80000000)

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF 0b0

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON 0b1

#define DRAM0_CLK_REG_DRAM0_UPD_OFFSET 27

#define DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK (0x08000000)

#define DRAM0_CLK_REG_DRAM0_UPD_INVALID 0b0

#define DRAM0_CLK_REG_DRAM0_UPD_VALID 0b1

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET 24

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK (0x07000000)

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL 0b000

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M 0b001

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M 0b010

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X 0b011

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL 0b100

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET 16

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK (0x00010000)

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY 0b0

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_8 0b1

#define DRAM0_CLK_REG_DRAM0_DIV1_OFFSET 0

#define DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK (0x0000001f)


#define DRAM0_BGR_REG 0x00000c0c//DRAM0 Bus Gating Reset Register

#define DRAM0_BGR_REG_DRAM0_RST_OFFSET 16

#define DRAM0_BGR_REG_DRAM0_RST_CLEAR_MASK (0x00010000)

#define DRAM0_BGR_REG_DRAM0_RST_ASSERT 0b0

#define DRAM0_BGR_REG_DRAM0_RST_DE_ASSERT 0b1

#define DRAM0_BGR_REG_DRAM0_GATING_OFFSET 0

#define DRAM0_BGR_REG_DRAM0_GATING_CLEAR_MASK (0x00000001)

#define DRAM0_BGR_REG_DRAM0_GATING_MASK 0b0

#define DRAM0_BGR_REG_DRAM0_GATING_PASS 0b1


#define NAND0_CLK0_CLK_REG 0x00000c80//NAND0 CLK0 Clock Register

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET 31

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF 0b0

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON 0b1

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET 0

#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define NAND0_CLK1_CLK_REG 0x00000c84//NAND0 CLK1 Clock Register

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0b0

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0b1

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0

#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define NAND0_BGR_REG 0x00000c8c//NAND0 Bus Gating Reset Register

#define NAND0_BGR_REG_NAND0_RST_OFFSET 16

#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK (0x00010000)

#define NAND0_BGR_REG_NAND0_RST_ASSERT 0b0

#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT 0b1

#define NAND0_BGR_REG_NAND0_GATING_OFFSET 0

#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK (0x00000001)

#define NAND0_BGR_REG_NAND0_GATING_MASK 0b0

#define NAND0_BGR_REG_NAND0_GATING_PASS 0b1


#define SMHC0_CLK_REG 0x00000d00//SMHC0 Clock Register

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK (0x80000000)

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SMHC0_BGR_REG 0x00000d0c//SMHC0 Bus Gating Reset Register

#define SMHC0_BGR_REG_SMHC0_RST_OFFSET 16

#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK (0x00010000)

#define SMHC0_BGR_REG_SMHC0_RST_ASSERT 0b0

#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT 0b1

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0

#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK (0x00000001)

#define SMHC0_BGR_REG_SMHC0_GATING_MASK 0b0

#define SMHC0_BGR_REG_SMHC0_GATING_PASS 0b1


#define SMHC1_CLK_REG 0x00000d10//SMHC1 Clock Register

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK (0x80000000)

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SMHC1_BGR_REG 0x00000d1c//SMHC1 Bus Gating Reset Register

#define SMHC1_BGR_REG_SMHC1_RST_OFFSET 16

#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK (0x00010000)

#define SMHC1_BGR_REG_SMHC1_RST_ASSERT 0b0

#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT 0b1

#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0

#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK (0x00000001)

#define SMHC1_BGR_REG_SMHC1_GATING_MASK 0b0

#define SMHC1_BGR_REG_SMHC1_GATING_PASS 0b1


#define SMHC2_CLK_REG 0x00000d20//SMHC2 Clock Register

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK (0x80000000)

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100

#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SMHC2_BGR_REG 0x00000d2c//SMHC2 Bus Gating Reset Register

#define SMHC2_BGR_REG_SMHC2_RST_OFFSET 16

#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK (0x00010000)

#define SMHC2_BGR_REG_SMHC2_RST_ASSERT 0b0

#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT 0b1

#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0

#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK (0x00000001)

#define SMHC2_BGR_REG_SMHC2_GATING_MASK 0b0

#define SMHC2_BGR_REG_SMHC2_GATING_PASS 0b1


#define SMHC3_CLK_REG 0x00000d30//SMHC3 Clock Register

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET 31

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK (0x80000000)

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF 0b0

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON 0b1

#define SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SMHC3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100

#define SMHC3_CLK_REG_FACTOR_N_OFFSET 8

#define SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SMHC3_CLK_REG_FACTOR_M_OFFSET 0

#define SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SMHC3_BGR_REG 0x00000d3c//SMHC3 Bus Gating Reset Register

#define SMHC3_BGR_REG_SMHC3_RST_OFFSET 16

#define SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK (0x00010000)

#define SMHC3_BGR_REG_SMHC3_RST_ASSERT 0b0

#define SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT 0b1

#define SMHC3_BGR_REG_SMHC3_GATING_OFFSET 0

#define SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK (0x00000001)

#define SMHC3_BGR_REG_SMHC3_GATING_MASK 0b0

#define SMHC3_BGR_REG_SMHC3_GATING_PASS 0b1


#define UFS_AXI_CLK_REG 0x00000d80//UFS_AXI Clock Register

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET 31

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK (0x80000000)

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF 0b0

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON 0b1

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

#define UFS_AXI_CLK_REG_FACTOR_M_OFFSET 0

#define UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define UFS_CFG_CLK_REG 0x00000d84//UFS_CFG Clock Register

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_OFFSET 31

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLEAR_MASK (0x80000000)

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_OFF 0b0

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_ON 0b1

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_HOSC 0b001

#define UFS_CFG_CLK_REG_FACTOR_M_OFFSET 0

#define UFS_CFG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define UFS_BGR_REG 0x00000d8c//UFS Bus Gating Reset Register

#define UFS_BGR_REG_UFS_CORE_RST_OFFSET 19

#define UFS_BGR_REG_UFS_CORE_RST_CLEAR_MASK (0x00080000)

#define UFS_BGR_REG_UFS_CORE_RST_ASSERT 0b0

#define UFS_BGR_REG_UFS_CORE_RST_DE_ASSERT 0b1

#define UFS_BGR_REG_UFS_PHY_RST_OFFSET 18

#define UFS_BGR_REG_UFS_PHY_RST_CLEAR_MASK (0x00040000)

#define UFS_BGR_REG_UFS_PHY_RST_ASSERT 0b0

#define UFS_BGR_REG_UFS_PHY_RST_DE_ASSERT 0b1

#define UFS_BGR_REG_UFS_AXI_RST_OFFSET 17

#define UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK (0x00020000)

#define UFS_BGR_REG_UFS_AXI_RST_ASSERT 0b0

#define UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT 0b1

#define UFS_BGR_REG_UFS_RST_OFFSET 16

#define UFS_BGR_REG_UFS_RST_CLEAR_MASK (0x00010000)

#define UFS_BGR_REG_UFS_RST_ASSERT 0b0

#define UFS_BGR_REG_UFS_RST_DE_ASSERT 0b1

#define UFS_BGR_REG_UFS_GATING_OFFSET 0

#define UFS_BGR_REG_UFS_GATING_CLEAR_MASK (0x00000001)

#define UFS_BGR_REG_UFS_GATING_MASK 0b0

#define UFS_BGR_REG_UFS_GATING_PASS 0b1


#define UFS_REF_CLK_EN_REG 0x00000d90//UFS Reference Clock Enable Register

#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_OFFSET 0

#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_CLEAR_MASK (0x00000001)


#define UART0_BGR_REG 0x00000e00//UART0 Bus Gating Reset Register

#define UART0_BGR_REG_UART0_RST_OFFSET 16

#define UART0_BGR_REG_UART0_RST_CLEAR_MASK (0x00010000)

#define UART0_BGR_REG_UART0_RST_ASSERT 0b0

#define UART0_BGR_REG_UART0_RST_DE_ASSERT 0b1

#define UART0_BGR_REG_UART0_GATING_OFFSET 0

#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK (0x00000001)

#define UART0_BGR_REG_UART0_GATING_MASK 0b0

#define UART0_BGR_REG_UART0_GATING_PASS 0b1


#define UART1_BGR_REG 0x00000e04//UART1 Bus Gating Reset Register

#define UART1_BGR_REG_UART1_RST_OFFSET 16

#define UART1_BGR_REG_UART1_RST_CLEAR_MASK (0x00010000)

#define UART1_BGR_REG_UART1_RST_ASSERT 0b0

#define UART1_BGR_REG_UART1_RST_DE_ASSERT 0b1

#define UART1_BGR_REG_UART1_GATING_OFFSET 0

#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK (0x00000001)

#define UART1_BGR_REG_UART1_GATING_MASK 0b0

#define UART1_BGR_REG_UART1_GATING_PASS 0b1


#define UART2_BGR_REG 0x00000e08//UART2 Bus Gating Reset Register

#define UART2_BGR_REG_UART2_RST_OFFSET 16

#define UART2_BGR_REG_UART2_RST_CLEAR_MASK (0x00010000)

#define UART2_BGR_REG_UART2_RST_ASSERT 0b0

#define UART2_BGR_REG_UART2_RST_DE_ASSERT 0b1

#define UART2_BGR_REG_UART2_GATING_OFFSET 0

#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK (0x00000001)

#define UART2_BGR_REG_UART2_GATING_MASK 0b0

#define UART2_BGR_REG_UART2_GATING_PASS 0b1


#define UART3_BGR_REG 0x00000e0c//UART3 Bus Gating Reset Register

#define UART3_BGR_REG_UART3_RST_OFFSET 16

#define UART3_BGR_REG_UART3_RST_CLEAR_MASK (0x00010000)

#define UART3_BGR_REG_UART3_RST_ASSERT 0b0

#define UART3_BGR_REG_UART3_RST_DE_ASSERT 0b1

#define UART3_BGR_REG_UART3_GATING_OFFSET 0

#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK (0x00000001)

#define UART3_BGR_REG_UART3_GATING_MASK 0b0

#define UART3_BGR_REG_UART3_GATING_PASS 0b1


#define UART4_BGR_REG 0x00000e10//UART4 Bus Gating Reset Register

#define UART4_BGR_REG_UART4_RST_OFFSET 16

#define UART4_BGR_REG_UART4_RST_CLEAR_MASK (0x00010000)

#define UART4_BGR_REG_UART4_RST_ASSERT 0b0

#define UART4_BGR_REG_UART4_RST_DE_ASSERT 0b1

#define UART4_BGR_REG_UART4_GATING_OFFSET 0

#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK (0x00000001)

#define UART4_BGR_REG_UART4_GATING_MASK 0b0

#define UART4_BGR_REG_UART4_GATING_PASS 0b1


#define UART5_BGR_REG 0x00000e14//UART5 Bus Gating Reset Register

#define UART5_BGR_REG_UART5_RST_OFFSET 16

#define UART5_BGR_REG_UART5_RST_CLEAR_MASK (0x00010000)

#define UART5_BGR_REG_UART5_RST_ASSERT 0b0

#define UART5_BGR_REG_UART5_RST_DE_ASSERT 0b1

#define UART5_BGR_REG_UART5_GATING_OFFSET 0

#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK (0x00000001)

#define UART5_BGR_REG_UART5_GATING_MASK 0b0

#define UART5_BGR_REG_UART5_GATING_PASS 0b1


#define UART6_BGR_REG 0x00000e18//UART6 Bus Gating Reset Register

#define UART6_BGR_REG_UART6_RST_OFFSET 16

#define UART6_BGR_REG_UART6_RST_CLEAR_MASK (0x00010000)

#define UART6_BGR_REG_UART6_RST_ASSERT 0b0

#define UART6_BGR_REG_UART6_RST_DE_ASSERT 0b1

#define UART6_BGR_REG_UART6_GATING_OFFSET 0

#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK (0x00000001)

#define UART6_BGR_REG_UART6_GATING_MASK 0b0

#define UART6_BGR_REG_UART6_GATING_PASS 0b1


#define TWI0_BGR_REG 0x00000e80//TWI0 Bus Gating Reset Register

#define TWI0_BGR_REG_TWI0_RST_OFFSET 16

#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK (0x00010000)

#define TWI0_BGR_REG_TWI0_RST_ASSERT 0b0

#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT 0b1

#define TWI0_BGR_REG_TWI0_GATING_OFFSET 0

#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK (0x00000001)

#define TWI0_BGR_REG_TWI0_GATING_MASK 0b0

#define TWI0_BGR_REG_TWI0_GATING_PASS 0b1


#define TWI1_BGR_REG 0x00000e84//TWI1 Bus Gating Reset Register

#define TWI1_BGR_REG_TWI1_RST_OFFSET 16

#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK (0x00010000)

#define TWI1_BGR_REG_TWI1_RST_ASSERT 0b0

#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT 0b1

#define TWI1_BGR_REG_TWI1_GATING_OFFSET 0

#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK (0x00000001)

#define TWI1_BGR_REG_TWI1_GATING_MASK 0b0

#define TWI1_BGR_REG_TWI1_GATING_PASS 0b1


#define TWI2_BGR_REG 0x00000e88//TWI2 Bus Gating Reset Register

#define TWI2_BGR_REG_TWI2_RST_OFFSET 16

#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK (0x00010000)

#define TWI2_BGR_REG_TWI2_RST_ASSERT 0b0

#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT 0b1

#define TWI2_BGR_REG_TWI2_GATING_OFFSET 0

#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK (0x00000001)

#define TWI2_BGR_REG_TWI2_GATING_MASK 0b0

#define TWI2_BGR_REG_TWI2_GATING_PASS 0b1


#define TWI3_BGR_REG 0x00000e8c//TWI3 Bus Gating Reset Register

#define TWI3_BGR_REG_TWI3_RST_OFFSET 16

#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK (0x00010000)

#define TWI3_BGR_REG_TWI3_RST_ASSERT 0b0

#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT 0b1

#define TWI3_BGR_REG_TWI3_GATING_OFFSET 0

#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK (0x00000001)

#define TWI3_BGR_REG_TWI3_GATING_MASK 0b0

#define TWI3_BGR_REG_TWI3_GATING_PASS 0b1


#define TWI4_BGR_REG 0x00000e90//TWI4 Bus Gating Reset Register

#define TWI4_BGR_REG_TWI4_RST_OFFSET 16

#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK (0x00010000)

#define TWI4_BGR_REG_TWI4_RST_ASSERT 0b0

#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT 0b1

#define TWI4_BGR_REG_TWI4_GATING_OFFSET 0

#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK (0x00000001)

#define TWI4_BGR_REG_TWI4_GATING_MASK 0b0

#define TWI4_BGR_REG_TWI4_GATING_PASS 0b1


#define TWI5_BGR_REG 0x00000e94//TWI5 Bus Gating Reset Register

#define TWI5_BGR_REG_TWI5_RST_OFFSET 16

#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK (0x00010000)

#define TWI5_BGR_REG_TWI5_RST_ASSERT 0b0

#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT 0b1

#define TWI5_BGR_REG_TWI5_GATING_OFFSET 0

#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK (0x00000001)

#define TWI5_BGR_REG_TWI5_GATING_MASK 0b0

#define TWI5_BGR_REG_TWI5_GATING_PASS 0b1


#define TWI6_BGR_REG 0x00000e98//TWI6 Bus Gating Reset Register

#define TWI6_BGR_REG_TWI6_RST_OFFSET 16

#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK (0x00010000)

#define TWI6_BGR_REG_TWI6_RST_ASSERT 0b0

#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT 0b1

#define TWI6_BGR_REG_TWI6_GATING_OFFSET 0

#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK (0x00000001)

#define TWI6_BGR_REG_TWI6_GATING_MASK 0b0

#define TWI6_BGR_REG_TWI6_GATING_PASS 0b1


#define TWI7_BGR_REG 0x00000e9c//TWI7 Bus Gating Reset Register

#define TWI7_BGR_REG_TWI7_RST_OFFSET 16

#define TWI7_BGR_REG_TWI7_RST_CLEAR_MASK (0x00010000)

#define TWI7_BGR_REG_TWI7_RST_ASSERT 0b0

#define TWI7_BGR_REG_TWI7_RST_DE_ASSERT 0b1

#define TWI7_BGR_REG_TWI7_GATING_OFFSET 0

#define TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK (0x00000001)

#define TWI7_BGR_REG_TWI7_GATING_MASK 0b0

#define TWI7_BGR_REG_TWI7_GATING_PASS 0b1


#define TWI8_BGR_REG 0x00000ea0//TWI8 Bus Gating Reset Register

#define TWI8_BGR_REG_TWI8_RST_OFFSET 16

#define TWI8_BGR_REG_TWI8_RST_CLEAR_MASK (0x00010000)

#define TWI8_BGR_REG_TWI8_RST_ASSERT 0b0

#define TWI8_BGR_REG_TWI8_RST_DE_ASSERT 0b1

#define TWI8_BGR_REG_TWI8_GATING_OFFSET 0

#define TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK (0x00000001)

#define TWI8_BGR_REG_TWI8_GATING_MASK 0b0

#define TWI8_BGR_REG_TWI8_GATING_PASS 0b1


#define TWI9_BGR_REG 0x00000ea4//TWI9 Bus Gating Reset Register

#define TWI9_BGR_REG_TWI9_RST_OFFSET 16

#define TWI9_BGR_REG_TWI9_RST_CLEAR_MASK (0x00010000)

#define TWI9_BGR_REG_TWI9_RST_ASSERT 0b0

#define TWI9_BGR_REG_TWI9_RST_DE_ASSERT 0b1

#define TWI9_BGR_REG_TWI9_GATING_OFFSET 0

#define TWI9_BGR_REG_TWI9_GATING_CLEAR_MASK (0x00000001)

#define TWI9_BGR_REG_TWI9_GATING_MASK 0b0

#define TWI9_BGR_REG_TWI9_GATING_PASS 0b1


#define TWI10_BGR_REG 0x00000ea8//TWI10 Bus Gating Reset Register

#define TWI10_BGR_REG_TWI10_RST_OFFSET 16

#define TWI10_BGR_REG_TWI10_RST_CLEAR_MASK (0x00010000)

#define TWI10_BGR_REG_TWI10_RST_ASSERT 0b0

#define TWI10_BGR_REG_TWI10_RST_DE_ASSERT 0b1

#define TWI10_BGR_REG_TWI10_GATING_OFFSET 0

#define TWI10_BGR_REG_TWI10_GATING_CLEAR_MASK (0x00000001)

#define TWI10_BGR_REG_TWI10_GATING_MASK 0b0

#define TWI10_BGR_REG_TWI10_GATING_PASS 0b1


#define TWI11_BGR_REG 0x00000eac//TWI11 Bus Gating Reset Register

#define TWI11_BGR_REG_TWI11_RST_OFFSET 16

#define TWI11_BGR_REG_TWI11_RST_CLEAR_MASK (0x00010000)

#define TWI11_BGR_REG_TWI11_RST_ASSERT 0b0

#define TWI11_BGR_REG_TWI11_RST_DE_ASSERT 0b1

#define TWI11_BGR_REG_TWI11_GATING_OFFSET 0

#define TWI11_BGR_REG_TWI11_GATING_CLEAR_MASK (0x00000001)

#define TWI11_BGR_REG_TWI11_GATING_MASK 0b0

#define TWI11_BGR_REG_TWI11_GATING_PASS 0b1


#define TWI12_BGR_REG 0x00000eb0//TWI12 Bus Gating Reset Register

#define TWI12_BGR_REG_TWI12_RST_OFFSET 16

#define TWI12_BGR_REG_TWI12_RST_CLEAR_MASK (0x00010000)

#define TWI12_BGR_REG_TWI12_RST_ASSERT 0b0

#define TWI12_BGR_REG_TWI12_RST_DE_ASSERT 0b1

#define TWI12_BGR_REG_TWI12_GATING_OFFSET 0

#define TWI12_BGR_REG_TWI12_GATING_CLEAR_MASK (0x00000001)

#define TWI12_BGR_REG_TWI12_GATING_MASK 0b0

#define TWI12_BGR_REG_TWI12_GATING_PASS 0b1


#define SPI0_CLK_REG 0x00000f00//SPI0 Clock Register

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110

#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPI0_CLK_REG_FACTOR_N_OFFSET 8

#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPI0_CLK_REG_FACTOR_M_OFFSET 0

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPI0_BGR_REG 0x00000f04//SPI0 Bus Gating Reset Register

#define SPI0_BGR_REG_SPI0_RST_OFFSET 16

#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK (0x00010000)

#define SPI0_BGR_REG_SPI0_RST_ASSERT 0b0

#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT 0b1

#define SPI0_BGR_REG_SPI0_GATING_OFFSET 0

#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK (0x00000001)

#define SPI0_BGR_REG_SPI0_GATING_MASK 0b0

#define SPI0_BGR_REG_SPI0_GATING_PASS 0b1


#define SPI1_CLK_REG 0x00000f08//SPI1 Clock Register

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110

#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPI1_CLK_REG_FACTOR_N_OFFSET 8

#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPI1_CLK_REG_FACTOR_M_OFFSET 0

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPI1_BGR_REG 0x00000f0c//SPI1 Bus Gating Reset Register

#define SPI1_BGR_REG_SPI1_RST_OFFSET 16

#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK (0x00010000)

#define SPI1_BGR_REG_SPI1_RST_ASSERT 0b0

#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT 0b1

#define SPI1_BGR_REG_SPI1_GATING_OFFSET 0

#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK (0x00000001)

#define SPI1_BGR_REG_SPI1_GATING_MASK 0b0

#define SPI1_BGR_REG_SPI1_GATING_PASS 0b1


#define SPI2_CLK_REG 0x00000f10//SPI2 Clock Register

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110

#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPI2_CLK_REG_FACTOR_N_OFFSET 8

#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPI2_CLK_REG_FACTOR_M_OFFSET 0

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPI2_BGR_REG 0x00000f14//SPI2 Bus Gating Reset Register

#define SPI2_BGR_REG_SPI2_RST_OFFSET 16

#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK (0x00010000)

#define SPI2_BGR_REG_SPI2_RST_ASSERT 0b0

#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT 0b1

#define SPI2_BGR_REG_SPI2_GATING_OFFSET 0

#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK (0x00000001)

#define SPI2_BGR_REG_SPI2_GATING_MASK 0b0

#define SPI2_BGR_REG_SPI2_GATING_PASS 0b1


#define SPIF_CLK_REG 0x00000f18//SPIF Clock Register

#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1

#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M 0b101

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M 0b110

#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPIF_CLK_REG_FACTOR_N_OFFSET 8

#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPIF_CLK_REG_FACTOR_M_OFFSET 0

#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPIF_BGR_REG 0x00000f1c//SPIF Bus Gating Reset Register

#define SPIF_BGR_REG_SPIF_RST_OFFSET 16

#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK (0x00010000)

#define SPIF_BGR_REG_SPIF_RST_ASSERT 0b0

#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT 0b1

#define SPIF_BGR_REG_SPIF_GATING_OFFSET 0

#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK (0x00000001)

#define SPIF_BGR_REG_SPIF_GATING_MASK 0b0

#define SPIF_BGR_REG_SPIF_GATING_PASS 0b1


#define SPI3_CLK_REG 0x00000f20//SPI3 Clock Register

#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1

#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPI3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110

#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPI3_CLK_REG_FACTOR_N_OFFSET 8

#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPI3_CLK_REG_FACTOR_M_OFFSET 0

#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPI3_BGR_REG 0x00000f24//SPI3 Bus Gating Reset Register

#define SPI3_BGR_REG_SPI3_RST_OFFSET 16

#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK (0x00010000)

#define SPI3_BGR_REG_SPI3_RST_ASSERT 0b0

#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT 0b1

#define SPI3_BGR_REG_SPI3_GATING_OFFSET 0

#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK (0x00000001)

#define SPI3_BGR_REG_SPI3_GATING_MASK 0b0

#define SPI3_BGR_REG_SPI3_GATING_PASS 0b1


#define SPI4_CLK_REG 0x00000f28//SPI4 Clock Register

#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET 31

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON 0b1

#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPI4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b011

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b100

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b101

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b110

#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC 0b111

#define SPI4_CLK_REG_FACTOR_N_OFFSET 8

#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define SPI4_CLK_REG_FACTOR_M_OFFSET 0

#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPI4_BGR_REG 0x00000f2c//SPI4 Bus Gating Reset Register

#define SPI4_BGR_REG_SPI4_RST_OFFSET 16

#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK (0x00010000)

#define SPI4_BGR_REG_SPI4_RST_ASSERT 0b0

#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT 0b1

#define SPI4_BGR_REG_SPI4_GATING_OFFSET 0

#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK (0x00000001)

#define SPI4_BGR_REG_SPI4_GATING_MASK 0b0

#define SPI4_BGR_REG_SPI4_GATING_PASS 0b1


#define GPADC0_24M_CLK_REG 0x00000fc0//GPADC0_24M Clock Register

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET 31

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK (0x80000000)

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF 0b0

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON 0b1

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC 0b001

#define GPADC0_24M_CLK_REG_FACTOR_M_OFFSET 0

#define GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define GPADC0_BGR_REG 0x00000fc4//GPADC0 Bus Gating Reset Register

#define GPADC0_BGR_REG_GPADC0_RST_OFFSET 16

#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK (0x00010000)

#define GPADC0_BGR_REG_GPADC0_RST_ASSERT 0b0

#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT 0b1

#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0

#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK (0x00000001)

#define GPADC0_BGR_REG_GPADC0_GATING_MASK 0b0

#define GPADC0_BGR_REG_GPADC0_GATING_PASS 0b1


#define THS0_BGR_REG 0x00000fe4//THS0 Bus Gating Reset Register

#define THS0_BGR_REG_THS0_RST_OFFSET 16

#define THS0_BGR_REG_THS0_RST_CLEAR_MASK (0x00010000)

#define THS0_BGR_REG_THS0_RST_ASSERT 0b0

#define THS0_BGR_REG_THS0_RST_DE_ASSERT 0b1

#define THS0_BGR_REG_THS0_GATING_OFFSET 0

#define THS0_BGR_REG_THS0_GATING_CLEAR_MASK (0x00000001)

#define THS0_BGR_REG_THS0_GATING_MASK 0b0

#define THS0_BGR_REG_THS0_GATING_PASS 0b1


#define IRRX_CLK_REG 0x00001000//IRRX Clock Register

#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET 31

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK (0x80000000)

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF 0b0

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON 0b1

#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K 0b000

#define IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b001

#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define IRRX_CLK_REG_FACTOR_M_OFFSET 0

#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define IRRX_BGR_REG 0x00001004//IRRX Bus Gating Reset Register

#define IRRX_BGR_REG_IRRX_RST_OFFSET 16

#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK (0x00010000)

#define IRRX_BGR_REG_IRRX_RST_ASSERT 0b0

#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT 0b1

#define IRRX_BGR_REG_IRRX_GATING_OFFSET 0

#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK (0x00000001)

#define IRRX_BGR_REG_IRRX_GATING_MASK 0b0

#define IRRX_BGR_REG_IRRX_GATING_PASS 0b1


#define IRTX_CLK_REG 0x00001008//IRTX Clock Register

#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK (0x80000000)

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0b0

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0b1

#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b001

#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define IRTX_CLK_REG_FACTOR_M_OFFSET 0

#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define IRTX_BGR_REG 0x0000100c//IRTX Bus Gating Reset Register

#define IRTX_BGR_REG_IRTX_RST_OFFSET 16

#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK (0x00010000)

#define IRTX_BGR_REG_IRTX_RST_ASSERT 0b0

#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0b1

#define IRTX_BGR_REG_IRTX_GATING_OFFSET 0

#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK (0x00000001)

#define IRTX_BGR_REG_IRTX_GATING_MASK 0b0

#define IRTX_BGR_REG_IRTX_GATING_PASS 0b1


#define LRADC_BGR_REG 0x00001024//LRADC Bus Gating Reset Register

#define LRADC_BGR_REG_LRADC_RST_OFFSET 16

#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK (0x00010000)

#define LRADC_BGR_REG_LRADC_RST_ASSERT 0b0

#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0b1

#define LRADC_BGR_REG_LRADC_GATING_OFFSET 0

#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK (0x00000001)

#define LRADC_BGR_REG_LRADC_GATING_MASK 0b0

#define LRADC_BGR_REG_LRADC_GATING_PASS 0b1


#define SGPIO_CLK_REG 0x00001060//SGPIO Clock Register

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_OFFSET 31

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLEAR_MASK (0x80000000)

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_OFF 0b0

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_ON 0b1

#define SGPIO_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SGPIO_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SGPIO_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SGPIO_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define SGPIO_CLK_REG_FACTOR_M_OFFSET 0

#define SGPIO_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SGPIO_BGR_REG 0x00001064//SGPIO Bus Gating Reset Register

#define SGPIO_BGR_REG_SGPIO_RST_OFFSET 16

#define SGPIO_BGR_REG_SGPIO_RST_CLEAR_MASK (0x00010000)

#define SGPIO_BGR_REG_SGPIO_RST_ASSERT 0b0

#define SGPIO_BGR_REG_SGPIO_RST_DE_ASSERT 0b1

#define SGPIO_BGR_REG_SGPIO_GATING_OFFSET 0

#define SGPIO_BGR_REG_SGPIO_GATING_CLEAR_MASK (0x00000001)

#define SGPIO_BGR_REG_SGPIO_GATING_MASK 0b0

#define SGPIO_BGR_REG_SGPIO_GATING_PASS 0b1


#define LPC_CLK_REG 0x00001080//LPC Clock Register

#define LPC_CLK_REG_LPC_CLK_GATING_OFFSET 31

#define LPC_CLK_REG_LPC_CLK_GATING_CLEAR_MASK (0x80000000)

#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_OFF 0b0

#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_ON 0b1

#define LPC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define LPC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b000

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b001

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b010

#define LPC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

#define LPC_CLK_REG_FACTOR_M_OFFSET 0

#define LPC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define LPC_BGR_REG 0x00001084//LPC Bus Gating Reset Register

#define LPC_BGR_REG_LPC_RST_OFFSET 16

#define LPC_BGR_REG_LPC_RST_CLEAR_MASK (0x00010000)

#define LPC_BGR_REG_LPC_RST_ASSERT 0b0

#define LPC_BGR_REG_LPC_RST_DE_ASSERT 0b1

#define LPC_BGR_REG_LPC_GATING_OFFSET 0

#define LPC_BGR_REG_LPC_GATING_CLEAR_MASK (0x00000001)

#define LPC_BGR_REG_LPC_GATING_MASK 0b0

#define LPC_BGR_REG_LPC_GATING_PASS 0b1


#define I2SPCM0_CLK_REG 0x00001200//I2SPCM0 Clock Register

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_OFFSET 31

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM0_BGR_REG 0x0000120c//I2SPCM0 Bus Gating Reset Register

#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET 16

#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK (0x00010000)

#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT 0b0

#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT 0b1

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET 0

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK (0x00000001)

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK 0b0

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS 0b1


#define I2SPCM1_CLK_REG 0x00001210//I2SPCM1 Clock Register

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET 31

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM1_BGR_REG 0x0000121c//I2SPCM1 Bus Gating Reset Register

#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16

#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK (0x00010000)

#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT 0b0

#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT 0b1

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK (0x00000001)

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK 0b0

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS 0b1


#define I2SPCM2_CLK_REG 0x00001220//I2SPCM2 Clock Register

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET 31

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM2_ASRC_CLK_REG 0x00001224//I2SPCM2_ASRC Clock Register

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET 31

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM2_BGR_REG 0x0000122c//I2SPCM2 Bus Gating Reset Register

#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16

#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK (0x00010000)

#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT 0b0

#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT 0b1

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK (0x00000001)

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK 0b0

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS 0b1

#define I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT 0x2


#define I2SPCM3_CLK_REG 0x00001230//I2SPCM3 Clock Register

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET 31

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM3_BGR_REG 0x0000123c//I2SPCM3 Bus Gating Reset Register

#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16

#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK (0x00010000)

#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT 0b0

#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT 0b1

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK (0x00000001)

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK 0b0

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS 0b1

#define I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT 0x3


#define I2SPCM4_CLK_REG 0x00001240//I2SPCM4 Clock Register

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET 31

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK (0x80000000)

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF 0b0

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON 0b1

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define I2SPCM4_CLK_REG_FACTOR_M_OFFSET 0

#define I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define I2SPCM4_BGR_REG 0x0000124c//I2SPCM4 Bus Gating Reset Register

#define I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET 16

#define I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK (0x00010000)

#define I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT 0b0

#define I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT 0b1

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET 0

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK (0x00000001)

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK 0b0

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS 0b1

#define I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT 0x4


#define SPDIF_TX_CLK_REG 0x00001280//SPDIF TX Clock Register

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET 31

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON 0b1

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define SPDIF_TX_CLK_REG_FACTOR_M_OFFSET 0

#define SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPDIF_RX_CLK_REG 0x00001284//SPDIF RX Clock Register

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET 31

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK (0x80000000)

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF 0b0

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON 0b1

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b000

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define SPDIF_RX_CLK_REG_FACTOR_M_OFFSET 0

#define SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SPDIF_BGR_REG 0x0000128c//SPDIF Bus Gating Reset Register

#define SPDIF_BGR_REG_SPDIF_RST_OFFSET 16

#define SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK (0x00010000)

#define SPDIF_BGR_REG_SPDIF_RST_ASSERT 0b0

#define SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT 0b1

#define SPDIF_BGR_REG_SPDIF_GATING_OFFSET 0

#define SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK (0x00000001)

#define SPDIF_BGR_REG_SPDIF_GATING_MASK 0b0

#define SPDIF_BGR_REG_SPDIF_GATING_PASS 0b1


#define DMIC_CLK_REG 0x000012c0//DMIC Clock Register

#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK (0x80000000)

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1

#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2 0b001

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5 0b010

#define DMIC_CLK_REG_FACTOR_M_OFFSET 0

#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define DMIC_BGR_REG 0x000012cc//DMIC Bus Gating Reset Register

#define DMIC_BGR_REG_DMIC_RST_OFFSET 16

#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK (0x00010000)

#define DMIC_BGR_REG_DMIC_RST_ASSERT 0b0

#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT 0b1

#define DMIC_BGR_REG_DMIC_GATING_OFFSET 0

#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK (0x00000001)

#define DMIC_BGR_REG_DMIC_GATING_MASK 0b0

#define DMIC_BGR_REG_DMIC_GATING_PASS 0b1


#define USB0_CLK_REG 0x00001300//USB0 Clock Register

#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK (0x80000000)

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1

#define USB0_CLK_REG_USB0_PHY_RSTN_OFFSET 30

#define USB0_CLK_REG_USB0_PHY_RSTN_CLEAR_MASK (0x40000000)

#define USB0_CLK_REG_USB0_PHY_RSTN_ASSERT 0b0

#define USB0_CLK_REG_USB0_PHY_RSTN_DE_ASSERT 0b1

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK (0x03000000)

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b000

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M 0b001

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K 0b010

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC 0b011


#define USB0_BGR_REG 0x00001304//USB0 Bus Gating Reset Register

#define USB0_BGR_REG_USB0_DEVICE_RST_OFFSET 24

#define USB0_BGR_REG_USB0_DEVICE_RST_CLEAR_MASK (0x01000000)

#define USB0_BGR_REG_USB0_DEVICE_RST_ASSERT 0b0

#define USB0_BGR_REG_USB0_DEVICE_RST_DE_ASSERT 0b1

#define USB0_BGR_REG_USB0_EHCI_RST_OFFSET 20

#define USB0_BGR_REG_USB0_EHCI_RST_CLEAR_MASK (0x00100000)

#define USB0_BGR_REG_USB0_EHCI_RST_ASSERT 0b0

#define USB0_BGR_REG_USB0_EHCI_RST_DE_ASSERT 0b1

#define USB0_BGR_REG_USB0_OHCI_RST_OFFSET 16

#define USB0_BGR_REG_USB0_OHCI_RST_CLEAR_MASK (0x00010000)

#define USB0_BGR_REG_USB0_OHCI_RST_ASSERT 0b0

#define USB0_BGR_REG_USB0_OHCI_RST_DE_ASSERT 0b1

#define USB0_BGR_REG_USB0_DEVICE_GATING_OFFSET 8

#define USB0_BGR_REG_USB0_DEVICE_GATING_CLEAR_MASK (0x00000100)

#define USB0_BGR_REG_USB0_DEVICE_GATING_MASK 0b0

#define USB0_BGR_REG_USB0_DEVICE_GATING_PASS 0b1

#define USB0_BGR_REG_USB0_EHCI_GATING_OFFSET 4

#define USB0_BGR_REG_USB0_EHCI_GATING_CLEAR_MASK (0x00000010)

#define USB0_BGR_REG_USB0_EHCI_GATING_MASK 0b0

#define USB0_BGR_REG_USB0_EHCI_GATING_PASS 0b1

#define USB0_BGR_REG_USB0_OHCI_GATING_OFFSET 0

#define USB0_BGR_REG_USB0_OHCI_GATING_CLEAR_MASK (0x00000001)

#define USB0_BGR_REG_USB0_OHCI_GATING_MASK 0b0

#define USB0_BGR_REG_USB0_OHCI_GATING_PASS 0b1


#define USB1_CLK_REG 0x00001308//USB1 Clock Register

#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31

#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK (0x80000000)

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1

#define USB1_CLK_REG_USB1_PHY_RSTN_OFFSET 30

#define USB1_CLK_REG_USB1_PHY_RSTN_CLEAR_MASK (0x40000000)

#define USB1_CLK_REG_USB1_PHY_RSTN_ASSERT 0b0

#define USB1_CLK_REG_USB1_PHY_RSTN_DE_ASSERT 0b1

#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK (0x03000000)

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b000

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M 0b001

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K 0b010

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC 0b011


#define USB1_BGR_REG 0x0000130c//USB1 Bus Gating Reset Register

#define USB1_BGR_REG_USB1_EHCI_RST_OFFSET 20

#define USB1_BGR_REG_USB1_EHCI_RST_CLEAR_MASK (0x00100000)

#define USB1_BGR_REG_USB1_EHCI_RST_ASSERT 0b0

#define USB1_BGR_REG_USB1_EHCI_RST_DE_ASSERT 0b1

#define USB1_BGR_REG_USB1_OHCI_RST_OFFSET 16

#define USB1_BGR_REG_USB1_OHCI_RST_CLEAR_MASK (0x00010000)

#define USB1_BGR_REG_USB1_OHCI_RST_ASSERT 0b0

#define USB1_BGR_REG_USB1_OHCI_RST_DE_ASSERT 0b1

#define USB1_BGR_REG_USB1_EHCI_GATING_OFFSET 4

#define USB1_BGR_REG_USB1_EHCI_GATING_CLEAR_MASK (0x00000010)

#define USB1_BGR_REG_USB1_EHCI_GATING_MASK 0b0

#define USB1_BGR_REG_USB1_EHCI_GATING_PASS 0b1

#define USB1_BGR_REG_USB1_OHCI_GATING_OFFSET 0

#define USB1_BGR_REG_USB1_OHCI_GATING_CLEAR_MASK (0x00000001)

#define USB1_BGR_REG_USB1_OHCI_GATING_MASK 0b0

#define USB1_BGR_REG_USB1_OHCI_GATING_PASS 0b1


#define USB0_USB1_REF_CLK_REG 0x00001340//USB0_USB1_REF Clock Register

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_OFFSET 31

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_ON 0b1

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b001


#define USB2_U2_REF_CLK_REG 0x00001348//USB2_U2_REF Clock Register

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_OFFSET 31

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_ON 0b1

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b001


#define USB2_SUSPEND_CLK_REG 0x00001350//USB2_SUSPEND Clock Register

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000)

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b1

#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0

#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define USB2_MF_CLK_REG 0x00001354//USB2_MF Clock Register

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1

#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define USB2_MF_CLK_REG_FACTOR_M_OFFSET 0

#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define USB2_BGR_REG 0x0000135c//USB2 Bus Gating Reset Register

#define USB2_BGR_REG_USB2_RST_OFFSET 16

#define USB2_BGR_REG_USB2_RST_CLEAR_MASK (0x00010000)

#define USB2_BGR_REG_USB2_RST_ASSERT 0b0

#define USB2_BGR_REG_USB2_RST_DE_ASSERT 0b1


#define USB2_U3_UTMI_CLK_REG 0x00001360//USB2_U3_UTMI Clock Register

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_OFFSET 31

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_ON 0b1

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define USB2_U3_UTMI_CLK_REG_FACTOR_M_OFFSET 0

#define USB2_U3_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define USB2_U2_PIPE_CLK_REG 0x00001364//USB2_U2_PIPE Clock Register

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_OFFSET 31

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLEAR_MASK (0x80000000)

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_OFF 0b0

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_ON 0b1

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define USB2_U2_PIPE_CLK_REG_FACTOR_M_OFFSET 0

#define USB2_U2_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define PCIE0_AUX_CLK_REG 0x00001380//PCIE0_AUX Clock Register

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET 31

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK (0x80000000)

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF 0b0

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON 0b1

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000)

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b0

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0b1

#define PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET 0

#define PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define PCIE0_AXI_SLV_CLK_REG 0x00001384//PCIE0_AXI_SLV Clock Register

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_OFFSET 31

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLEAR_MASK (0x80000000)

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_OFF 0b0

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_ON 0b1

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b000

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_OFFSET 0

#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define PCIE0_BGR_REG 0x0000138c//PCIE0 Bus Gating Reset Register

#define PCIE0_BGR_REG_PCIE0_RST_OFFSET 17

#define PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK (0x00020000)

#define PCIE0_BGR_REG_PCIE0_RST_ASSERT 0b0

#define PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT 0b1

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET 16

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK (0x00010000)

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT 0b0

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT 0b1


#define SERDES_PHY_CFG_CLK_REG 0x000013c0//SERDES_PHY_CFG Clock Register

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET 31

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK (0x80000000)

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define SERDES_BGR_REG 0x000013c4//SERDES Bus Gating Reset Register

#define SERDES_BGR_REG_SERDES_RST_OFFSET 16

#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK (0x00010000)

#define SERDES_BGR_REG_SERDES_RST_ASSERT 0b0

#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT 0b1


#define GMAC_PTP_CLK_REG 0x00001400//GMAC_PTP Clock Register

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET 31

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK (0x80000000)

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF 0b0

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON 0b1

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define GMAC_PTP_CLK_REG_FACTOR_M_OFFSET 0

#define GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define GMAC0_PHY_CLK_REG 0x00001410//GMAC0_PHY Clock Register

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK (0x80000000)

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1

#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0

#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define GMAC0_BGR_REG 0x0000141c//GMAC0 Bus Gating Reset Register

#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17

#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK (0x00020000)

#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT 0b0

#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT 0b1

#define GMAC0_BGR_REG_GMAC0_RST_OFFSET 16

#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK (0x00010000)

#define GMAC0_BGR_REG_GMAC0_RST_ASSERT 0b0

#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT 0b1

#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0

#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK (0x00000001)

#define GMAC0_BGR_REG_GMAC0_GATING_MASK 0b0

#define GMAC0_BGR_REG_GMAC0_GATING_PASS 0b1


#define GMAC1_PHY_CLK_REG 0x00001420//GMAC1_PHY Clock Register

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK (0x80000000)

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1

#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0

#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define GMAC1_BGR_REG 0x0000142c//GMAC1 Bus Gating Reset Register

#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17

#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK (0x00020000)

#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT 0b0

#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT 0b1

#define GMAC1_BGR_REG_GMAC1_RST_OFFSET 16

#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK (0x00010000)

#define GMAC1_BGR_REG_GMAC1_RST_ASSERT 0b0

#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT 0b1

#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0

#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK (0x00000001)

#define GMAC1_BGR_REG_GMAC1_GATING_MASK 0b0

#define GMAC1_BGR_REG_GMAC1_GATING_PASS 0b1


#define VO0_TCONLCD0_CLK_REG 0x00001500//VO0_TCONLCD0 Clock Register

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK (0x80000000)

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0b0

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0b1

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VO0_TCONLCD0_BGR_REG 0x00001504//VO0_TCONLCD0 Bus Gating Reset Register

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK (0x00010000)

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0b0

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0b1

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK (0x00000001)

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK 0b0

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS 0b1


#define VO0_TCONLCD1_CLK_REG 0x00001508//VO0_TCONLCD1 Clock Register

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET 31

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK (0x80000000)

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF 0b0

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON 0b1

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET 0

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VO0_TCONLCD1_BGR_REG 0x0000150c//VO0_TCONLCD1 Bus Gating Reset Register

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET 16

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK (0x00010000)

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT 0b0

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT 0b1

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET 0

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK (0x00000001)

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK 0b0

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS 0b1


#define VO0_TCONLCD2_CLK_REG 0x00001510//VO0_TCONLCD2 Clock Register

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET 31

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK (0x80000000)

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF 0b0

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON 0b1

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET 0

#define VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VO0_TCONLCD2_BGR_REG 0x00001514//VO0_TCONLCD2 Bus Gating Reset Register

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET 16

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK (0x00010000)

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT 0b0

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT 0b1

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET 0

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK (0x00000001)

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK 0b0

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS 0b1


#define LVDS0_BGR_REG 0x00001544//LVDS0 Bus Gating Reset Register

#define LVDS0_BGR_REG_LVDS0_RST_OFFSET 16

#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK (0x00010000)

#define LVDS0_BGR_REG_LVDS0_RST_ASSERT 0b0

#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT 0b1


#define LVDS1_BGR_REG 0x0000154c//LVDS1 Bus Gating Reset Register

#define LVDS1_BGR_REG_LVDS1_RST_OFFSET 16

#define LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK (0x00010000)

#define LVDS1_BGR_REG_LVDS1_RST_ASSERT 0b0

#define LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT 0b1


#define DSI0_CLK_REG 0x00001580//DSI0 Clock Register

#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK (0x80000000)

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0b1

#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define DSI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010

#define DSI0_CLK_REG_FACTOR_M_OFFSET 0

#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define DSI0_BGR_REG 0x00001584//DSI0 Bus Gating Reset Register

#define DSI0_BGR_REG_DSI0_RST_OFFSET 16

#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK (0x00010000)

#define DSI0_BGR_REG_DSI0_RST_ASSERT 0b0

#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT 0b1

#define DSI0_BGR_REG_DSI0_GATING_OFFSET 0

#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK (0x00000001)

#define DSI0_BGR_REG_DSI0_GATING_MASK 0b0

#define DSI0_BGR_REG_DSI0_GATING_PASS 0b1


#define DSI1_CLK_REG 0x00001588//DSI1 Clock Register

#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET 31

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK (0x80000000)

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF 0b0

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON 0b1

#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define DSI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010

#define DSI1_CLK_REG_FACTOR_M_OFFSET 0

#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define DSI1_BGR_REG 0x0000158c//DSI1 Bus Gating Reset Register

#define DSI1_BGR_REG_DSI1_RST_OFFSET 16

#define DSI1_BGR_REG_DSI1_RST_CLEAR_MASK (0x00010000)

#define DSI1_BGR_REG_DSI1_RST_ASSERT 0b0

#define DSI1_BGR_REG_DSI1_RST_DE_ASSERT 0b1

#define DSI1_BGR_REG_DSI1_GATING_OFFSET 0

#define DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK (0x00000001)

#define DSI1_BGR_REG_DSI1_GATING_MASK 0b0

#define DSI1_BGR_REG_DSI1_GATING_PASS 0b1


#define COMBPHY0_CLK_REG 0x000015c0//COMBPHY0 Clock Register

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET 31

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK (0x80000000)

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0b0

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0b1

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100

#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0

#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define COMBPHY1_CLK_REG 0x000015c4//COMBPHY1 Clock Register

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET 31

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK (0x80000000)

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF 0b0

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON 0b1

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b100

#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET 0

#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define TCONTV0_BGR_REG 0x00001604//TCONTV0 Bus Gating Reset Register

#define TCONTV0_BGR_REG_TCONTV0_RST_OFFSET 16

#define TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK (0x00010000)

#define TCONTV0_BGR_REG_TCONTV0_RST_ASSERT 0b0

#define TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT 0b1

#define TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET 0

#define TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK (0x00000001)

#define TCONTV0_BGR_REG_TCONTV0_GATING_MASK 0b0

#define TCONTV0_BGR_REG_TCONTV0_GATING_PASS 0b1


#define TCONTV1_BGR_REG 0x0000160c//TCONTV1 Bus Gating Reset Register

#define TCONTV1_BGR_REG_TCONTV1_RST_OFFSET 16

#define TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK (0x00010000)

#define TCONTV1_BGR_REG_TCONTV1_RST_ASSERT 0b0

#define TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT 0b1

#define TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET 0

#define TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK (0x00000001)

#define TCONTV1_BGR_REG_TCONTV1_GATING_MASK 0b0

#define TCONTV1_BGR_REG_TCONTV1_GATING_PASS 0b1


#define EDP_TV_CLK_REG 0x00001640//EDP_TV Clock Register

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_OFFSET 31

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLEAR_MASK (0x80000000)

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_OFF 0b0

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_ON 0b1

#define EDP_TV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define EDP_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define EDP_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define EDP_TV_CLK_REG_FACTOR_N_OFFSET 8

#define EDP_TV_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define EDP_TV_CLK_REG_FACTOR_M_OFFSET 0

#define EDP_TV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define EDP_BGR_REG 0x0000164c//EDP Bus Gating Reset Register

#define EDP_BGR_REG_EDP_RST_OFFSET 16

#define EDP_BGR_REG_EDP_RST_CLEAR_MASK (0x00010000)

#define EDP_BGR_REG_EDP_RST_ASSERT 0b0

#define EDP_BGR_REG_EDP_RST_DE_ASSERT 0b1

#define EDP_BGR_REG_EDP_GATING_OFFSET 0

#define EDP_BGR_REG_EDP_GATING_CLEAR_MASK (0x00000001)

#define EDP_BGR_REG_EDP_GATING_MASK 0b0

#define EDP_BGR_REG_EDP_GATING_PASS 0b1


#define HDMI_CEC_CLK_REG 0x00001680//HDMI CEC Clock Register

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET 31

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK (0x80000000)

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF 0b0

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON 0b1

#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET 30

#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK (0x40000000)

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF 0b0

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON 0b1

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K 0b000

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K_PERI0PLL2X_36621_32_768KHZ 0b001


#define HDMI_TV_CLK_REG 0x00001684//HDMI_TV Clock Register

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_OFFSET 31

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLEAR_MASK (0x80000000)

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_OFF 0b0

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_ON 0b1

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b010

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b011

#define HDMI_TV_CLK_REG_FACTOR_N_OFFSET 8

#define HDMI_TV_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define HDMI_TV_CLK_REG_FACTOR_M_OFFSET 0

#define HDMI_TV_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define HDMI_BGR_REG 0x0000168c//HDMI Bus Gating Reset Register

#define HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET 18

#define HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK (0x00040000)

#define HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT 0b0

#define HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT 0b1

#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET 17

#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK (0x00020000)

#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT 0b0

#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT 0b1

#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET 16

#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK (0x00010000)

#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT 0b0

#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT 0b1

#define HDMI_BGR_REG_HDMI_GATING_OFFSET 0

#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK (0x00000001)

#define HDMI_BGR_REG_HDMI_GATING_MASK 0b0

#define HDMI_BGR_REG_HDMI_GATING_PASS 0b1


#define HDMI_SFR_CLK_REG 0x00001690//HDMI SFR Clock Register

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_OFFSET 31

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLEAR_MASK (0x80000000)

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_OFF 0b0

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_ON 0b1

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_HOSC 0b001


#define HDCP_ESM_CLK_REG 0x00001694//HDCP ESM Clock Register

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_OFFSET 31

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLEAR_MASK (0x80000000)

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_OFF 0b0

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_ON 0b1


#define DPSS_TOP0_BGR_REG 0x000016c4//DPSS_TOP0 Bus Gating Reset Register

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET 16

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK (0x00010000)

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT 0b0

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT 0b1

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET 0

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK (0x00000001)

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK 0b0

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS 0b1


#define DPSS_TOP1_BGR_REG 0x000016cc//DPSS_TOP1 Bus Gating Reset Register

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET 16

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK (0x00010000)

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT 0b0

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT 0b1

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET 0

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK (0x00000001)

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK 0b0

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS 0b1


#define VIDEO_OUT0_BGR_REG 0x000016e4//VIDEO_OUT0 Bus Gating Reset Register

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK (0x00010000)

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT 0b0

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT 0b1


#define VIDEO_OUT1_BGR_REG 0x000016ec//VIDEO_OUT1 Bus Gating Reset Register

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET 16

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK (0x00010000)

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT 0b0

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT 0b1


#define LEDC_CLK_REG 0x00001700//LEDC Clock Register

#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK (0x80000000)

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1

#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001

#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0b010

#define LEDC_CLK_REG_FACTOR_M_OFFSET 0

#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define LEDC_BGR_REG 0x00001704//LEDC Bus Gating Reset Register

#define LEDC_BGR_REG_LEDC_RST_OFFSET 16

#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK (0x00010000)

#define LEDC_BGR_REG_LEDC_RST_ASSERT 0b0

#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0b1

#define LEDC_BGR_REG_LEDC_GATING_OFFSET 0

#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK (0x00000001)

#define LEDC_BGR_REG_LEDC_GATING_MASK 0b0

#define LEDC_BGR_REG_LEDC_GATING_PASS 0b1


#define DSC_BGR_REG 0x00001744//DSC Bus Gating Reset Register

#define DSC_BGR_REG_DSC_RST_OFFSET 16

#define DSC_BGR_REG_DSC_RST_CLEAR_MASK (0x00010000)

#define DSC_BGR_REG_DSC_RST_ASSERT 0b0

#define DSC_BGR_REG_DSC_RST_DE_ASSERT 0b1

#define DSC_BGR_REG_DSC_GATING_OFFSET 0

#define DSC_BGR_REG_DSC_GATING_CLEAR_MASK (0x00000001)

#define DSC_BGR_REG_DSC_GATING_MASK 0b0

#define DSC_BGR_REG_DSC_GATING_PASS 0b1


#define CSI_MASTER0_CLK_REG 0x00001800//CSI Master0 Clock Register

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK (0x80000000)

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CSI_MASTER1_CLK_REG 0x00001804//CSI Master1 Clock Register

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK (0x80000000)

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CSI_MASTER2_CLK_REG 0x00001808//CSI Master2 Clock Register

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK (0x80000000)

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X 0b010

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b011

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b101

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X 0b110

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CSI_CLK_REG 0x00001840//CSI Clock Register

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK (0x80000000)

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000

#define CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X 0b001

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b100

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b101

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b110

#define CSI_CLK_REG_FACTOR_M_OFFSET 0

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define CSI_BGR_REG 0x00001844//CSI Bus Gating Reset Register

#define CSI_BGR_REG_CSI_RST_OFFSET 16

#define CSI_BGR_REG_CSI_RST_CLEAR_MASK (0x00010000)

#define CSI_BGR_REG_CSI_RST_ASSERT 0b0

#define CSI_BGR_REG_CSI_RST_DE_ASSERT 0b1

#define CSI_BGR_REG_CSI_GATING_OFFSET 0

#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK (0x00000001)

#define CSI_BGR_REG_CSI_GATING_MASK 0b0

#define CSI_BGR_REG_CSI_GATING_PASS 0b1


#define ISP_CLK_REG 0x00001860//ISP Clock Register

#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31

#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK (0x80000000)

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1

#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0b000

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b100

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b101

#define ISP_CLK_REG_FACTOR_M_OFFSET 0

#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define VIDEO_IN_BGR_REG 0x00001884//VIDEO_IN Bus Gating Reset Register

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET 16

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK (0x00010000)

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT 0b0

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT 0b1


#define DDRPLL_GATE_EN_REG 0x00001904//DDRPLL Gate Enable Register

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET 16

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE 0b0

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE 0b1

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET 0

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO 0b0

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO 0b1


#define PERI0PLL_GATE_EN_REG 0x00001908//PERI0PLL Gate Enable Register

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET 31

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000)

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK (0x08000000)

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK (0x04000000)

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000)

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000)

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK (0x00000800)

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000400)

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100)

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010)

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1


#define PERI1PLL_GATE_EN_REG 0x0000190c//PERI1PLL Gate Enable Register

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET 31

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000)

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK (0x08000000)

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK (0x04000000)

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET 24

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000)

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET 22

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000)

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000800)

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000400)

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET 8

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100)

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET 6

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010)

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1


#define VIDEOPLL_GATE_EN_REG 0x00001910//VIDEOPLL Gate Enable Register

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET 22

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00400000)

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00200000)

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET 20

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00100000)

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET 18

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00040000)

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET 6

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000040)

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000020)

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET 4

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000010)

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET 2

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000004)

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1


#define GPUPLL_GATE_EN_REG 0x00001914//GPUPLL Gate Enable Register

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET 16

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE 0b0

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE 0b1

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET 0

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO 0b0

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO 0b1


#define VEPLL_GATE_EN_REG 0x00001918//VEPLL Gate Enable Register

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET 17

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE 0b0

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE 0b1

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET 16

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE 0b0

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE 0b1

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET 1

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO 0b0

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO 0b1

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET 0

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO 0b0

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO 0b1


#define AUDIOPLL_GATE_EN_REG 0x0000191c//AUDIOPLL Gate Enable Register

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_OFFSET 18

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_CLEAR_MASK (0x00040000)

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_DISABLE 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_ENABLE 0b1

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_OFFSET 17

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_DISABLE 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_ENABLE 0b1

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET 16

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE 0b1

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_OFFSET 2

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_CLEAR_MASK (0x00000004)

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_AUTO 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_NO_AUTO 0b1

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_OFFSET 1

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_AUTO 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_NO_AUTO 0b1

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET 0

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO 0b0

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1


#define NPUPLL_GATE_EN_REG 0x00001920//NPUPLL Gate Enable Register

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET 16

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE 0b0

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE 0b1

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET 0

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO 0b0

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO 0b1


#define DEPLL_GATE_EN_REG 0x00001928//DEPLL Gate Enable Register

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET 17

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK (0x00020000)

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE 0b0

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE 0b1

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET 16

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE 0b0

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE 0b1

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET 1

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000002)

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO 0b0

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO 0b1

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET 0

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO 0b0

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO 0b1


#define DDRPLL_GATE_STAT_REG 0x00001984//DDRPLL Gate Status Register

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET 16

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK (0x00010000)

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE 0b0

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE 0b1


#define PERI0PLL_GATE_STAT_REG 0x00001988//PERI0PLL Gate Status Register

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 27

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK (0x08000000)

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 26

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK (0x04000000)

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 25

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK (0x02000000)

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 24

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000)

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 23

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK (0x00800000)

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 22

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK (0x00400000)

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 21

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 20

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK (0x00100000)

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 19

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK (0x00080000)

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 18

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 17

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK (0x00020000)

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 16

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK (0x00010000)

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1


#define PERI1PLL_GATE_STAT_REG 0x0000198c//PERI1PLL Gate Status Register

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 27

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK (0x08000000)

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 26

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK (0x04000000)

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 25

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK (0x02000000)

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET 24

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000)

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 23

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK (0x00800000)

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET 22

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK (0x00400000)

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 21

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 20

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK (0x00100000)

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 19

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK (0x00080000)

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 18

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 17

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK (0x00020000)

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 16

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK (0x00010000)

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1


#define VIDEOPLL_GATE_STAT_REG 0x00001990//VIDEOPLL Gate Status Register

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET 22

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK (0x00400000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE 0b1

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET 21

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK (0x00200000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE 0b1

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET 20

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK (0x00100000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE 0b1

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET 18

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK (0x00040000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE 0b1

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET 17

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK (0x00020000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE 0b1

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET 16

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000)

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE 0b0

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE 0b1


#define GPUPLL_GATE_STAT_REG 0x00001994//GPUPLL Gate Status Register

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET 16

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK (0x00010000)

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE 0b0

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE 0b1


#define VEPLL_GATE_STAT_REG 0x00001998//VEPLL Gate Status Register

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET 17

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK (0x00020000)

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE 0b0

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE 0b1

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET 16

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK (0x00010000)

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE 0b0

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE 0b1


#define AUDIOPLL_GATE_STAT_REG 0x0000199c//AUDIOPLL Gate Status Register

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_OFFSET 18

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_CLEAR_MASK (0x00040000)

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_DISABLE 0b0

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_ENABLE 0b1

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_OFFSET 17

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_CLEAR_MASK (0x00020000)

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_DISABLE 0b0

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_ENABLE 0b1

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET 16

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000)

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE 0b0

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE 0b1


#define NPUPLL_GATE_STAT_REG 0x000019a0//NPUPLL Gate Status Register

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET 16

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK (0x00010000)

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE 0b0

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE 0b1


#define DEPLL_GATE_STAT_REG 0x000019a8//DEPLL Gate Status Register

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET 17

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK (0x00020000)

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE 0b0

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE 0b1

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET 16

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK (0x00010000)

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE 0b0

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE 0b1


#define CLK24M_GATE_EN_REG 0x00001a00//CLK24M Gate Enable Register

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK (0x00000008)

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0b0

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0b1


#define CM_VI_CFG_REG 0x00001b00//CM VI Enable Configuration Register

#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16

#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK (0x00030000)

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF 0b01

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON 0b10

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE 0b0

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE 0b1


#define CM_DESYS_CFG_REG 0x00001b04//CM DESYS Enable Configuration Register

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET 16

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK (0x00030000)

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF 0b01

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON 0b10

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET 0

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE 0b0

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE 0b1


#define CM_VE_DEC_CFG_REG 0x00001b10//CM VE_DEC Enable Configuration Register

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET 16

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK (0x00030000)

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF 0b01

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON 0b10

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET 0

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE 0b0

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE 0b1


#define CM_VE_ENC_CFG_REG 0x00001b14//CM VE_ENC Enable Configuration Register

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET 16

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK (0x00030000)

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF 0b01

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON 0b10

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET 0

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE 0b0

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE 0b1


#define CM_NPU_CFG_REG 0x00001b1c//CM NPU Enable Configuration Register

#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16

#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK (0x00030000)

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF 0b01

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON 0b10

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE 0b0

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE 0b1


#define CM_GPU0_CFG_REG 0x00001b24//CM GPU0 Enable Configuration Register

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET 16

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK (0x00030000)

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF 0b01

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON 0b10

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET 0

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE 0b0

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE 0b1


#define CM_PCIE0_CFG_REG 0x00001b28//CM PCIE0 Enable Configuration Register

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET 16

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK (0x00030000)

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF 0b01

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON 0b10

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET 0

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE 0b0

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE 0b1


#define CM_USB2_CFG_REG 0x00001b30//CM USB2 Enable Configuration Register

#define CM_USB2_CFG_REG_CM_USB2_STATUS_OFFSET 16

#define CM_USB2_CFG_REG_CM_USB2_STATUS_CLEAR_MASK (0x00030000)

#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_OFF 0b01

#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_ON 0b10

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_OFFSET 0

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_DISABLE 0b0

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_ENABLE 0b1


#define CM_VO_CFG_REG 0x00001b34//CM VO Enable Configuration Register

#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16

#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK (0x00030000)

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF 0b01

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON 0b10

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE 0b0

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE 0b1


#define CM_VO1_CFG_REG 0x00001b38//CM VO1 Enable Configuration Register

#define CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET 16

#define CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK (0x00030000)

#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF 0b01

#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON 0b10

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET 0

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK (0x00000001)

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE 0b0

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE 0b1


#define APB2JTAG_CLK_REG 0x00001c00//APB2JTAG Clock Register

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_OFFSET 31

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLEAR_MASK (0x80000000)

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_OFF 0b0

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_ON 0b1

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M 0b000

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b011

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b101

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define APB2JTAG_CLK_REG_FACTOR_M_OFFSET 0

#define APB2JTAG_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)


#define APB2JTAG_BGR_REG 0x00001c04//APB2JTAG Bus Gating Reset Register

#define APB2JTAG_BGR_REG_APB2JTAG_RST_OFFSET 16

#define APB2JTAG_BGR_REG_APB2JTAG_RST_CLEAR_MASK (0x00010000)

#define APB2JTAG_BGR_REG_APB2JTAG_RST_ASSERT 0b0

#define APB2JTAG_BGR_REG_APB2JTAG_RST_DE_ASSERT 0b1


#define CCU_SEC_SWITCH_REG 0x00001f00//CCU Security Switch Register

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK (0x00000004)

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK (0x00000002)

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK (0x00000001)

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1


#define SYSDAP_REQ_CTRL_REG 0x00001f10//SYSDAP REQ Control Register

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK (0x00000001)


#define PLL_CFG0_REG 0x00001f20//PLL Configuration0 Register

#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0

#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK (0xffffffff)


#define PLL_CFG1_REG 0x00001f24//PLL Configuration1 Register

#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0

#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK (0xffffffff)


#define PLL_CFG2_REG 0x00001f28//PLL Configuration2 Register

#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0

#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK (0xffffffff)


#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c//PLL Lock Debug Control Register

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK (0x80000000)

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK (0x07f00000)

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL 0b0000000

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0b0000001

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL 0b0000010

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL 0b0000011

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL 0b0000100

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0000101

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0000110

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL 0b0000111

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL 0b0001001

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL 0b0001010

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0001011

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0b0001100

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL 0b0001101

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b0100000

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL 0b1000000

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL 0b1000001

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL 0b1000010

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL 0b1000011

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL0 0b1100000

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL1 0b1100001

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_HDMIPLL 0b1110000


#define CCU_FAN_GATE_REG 0x00001f30//CCU FANOUT CLOCK GATE Register

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK (0x00000008)

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK (0x00000004)

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK (0x00000002)

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK (0x00000001)

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1


#define CLK27M_FAN_REG 0x00001f34//CLK27M FANOUT Register

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK (0x80000000)

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK (0x03000000)

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X 0b010

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK (0x00001f00)

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK (0x0000001f)


#define CLK_FAN_REG 0x00001f38//CLK FANOUT Register

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK (0x80000000)

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1

#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK (0x000003e0)

#define CLK_FAN_REG_PCLK_DIV_OFFSET 0

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK (0x0000001f)


#define CCU_FAN_REG 0x00001f3c//CCU FANOUT Register

#define CCU_FAN_REG_CLK_FANOUT3_EN_OFFSET 24

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK (0x01000000)

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK (0x00800000)

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK (0x00400000)

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK (0x00200000)

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0b0

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0b1

#define CCU_FAN_REG_CLK_FANOUT3_SEL_OFFSET 9

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK (0x00000e00)

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M 0b011

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK27M 0b101

#define CCU_FAN_REG_CLK_FANOUT3_SEL_PCLK 0b110

#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK (0x000001c0)

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M 0b011

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0b101

#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0b110

#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK (0x00000038)

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M 0b011

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0b101

#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0b110

#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK (0x00000007)

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2 0b001

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M 0b011

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0b101

#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0b110


#define BUS_CLK_DBG_REG 0x00001f50//Bus Clock Debug Register

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK (0x00000007)

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK 0b000

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK 0b001

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK 0b010

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK 0b011

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK 0b100

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK 0b101

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR0_CLK 0b110

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_HDR0_CLK 0b111


#define CCU_VERSION_REG 0x00001ff0//CCU Version Register

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK (0xffff0000)

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK (0x0000ffff)


/* cpu pll */

#define PLL_CPU_CTRL_REG_PLL_EN_OFFSET 31

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27


#define APB2_CLK_RATE_N_1 (0x0 << 8)

#define APB2_CLK_RATE_N_2 (0x1 << 8)

#define APB2_CLK_RATE_N_4 (0x2 << 8)

#define APB2_CLK_RATE_N_8 (0x3 << 8)

#define APB2_CLK_RATE_N_MASK (3 << 8)

#define APB2_CLK_RATE_M(m) (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)

#define APB2_CLK_RATE_M_MASK (3 << APB1_CLK_REG_FACTOR_M_OFFSET)


#define SUNXI_MEMC_CLK_RST (SUNXI_MEMC_COMMON_BASE + 0x10)

#define MEMC_REG_PLLREF_CLK_EN (1U << 13)

#define MEMC_REG_HDR_CLK1_EN (1U << 10)

#define MEMC_REG_HDR_CLK0_EN (1U << 9)

#define MEMC_REG_HCLK1_EN (1U << 8)

#define CCU_MMC_CTRL_M(x) (x)

#define CCU_MMC_CTRL_N(x) ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)

#define CCU_MMC_CTRL_OSCM24 (SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PLL6X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PLL_PERIPH2X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI0_400M_freq (400000000)

#define CCU_MMC_CTRL_PERI0_300M_freq (300000000)

#define CCU_MMC_CTRL_PERI0_800M_freq (800000000)

#define CCU_MMC_CTRL_PERI0_600M_freq (600000000)

#define CCU_MMC_CTRL_PERI0_400M (0x1 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI0_300M (0x2 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI0_800M (0x1 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI0_600M (0x2 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI1_400M (0x3 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI1_300M (0x4 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI1_800M (0x3 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_PERI1_600M (0x4 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CCU_MMC_CTRL_ENABLE (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)

/* if doesn't have these delays */

#define CCU_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)

#define CCU_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)


/* Module gate/reset shift*/

#define RESET_SHIFT (16)

#define GATING_SHIFT (0)


/*CE*/

#define CE_CLK_SRC_MASK (0x7)

#define CE_CLK_SRC_SEL_BIT (CE_CLK_REG_CLK_SRC_SEL_OFFSET)

#define CE_CLK_SRC (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)


#define CE_CLK_DIV_RATION_N_BIT (8)

#define CE_CLK_DIV_RATION_N_MASK (0x3)

#define CE_CLK_DIV_RATION_N (0)


#define CE_CLK_DIV_RATION_M_BIT (CE_CLK_REG_FACTOR_M_OFFSET)

//@TODO

#define CE_CLK_DIV_RATION_M_MASK (CE_CLK_REG_FACTOR_M_CLEAR_MASK)

#define CE_CLK_DIV_RATION_M (0)


#define CE_SCLK_ONOFF_BIT (CE_CLK_REG_CE_CLK_GATING_OFFSET)

//@TODO

#define CE_SCLK_ON (CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF)


//@TODO

#define CE_GATING_PASS (CE_BGR_REG_CE_GATING_MASK)

#define CE_GATING_BIT (CE_BGR_REG_CE_GATING_OFFSET)


#define CE_RST_BIT (CE_BGR_REG_CE_RST_OFFSET)

//@TODO

#define CE_DEASSERT (CE_BGR_REG_CE_SYS_RST_ASSERT)

#define CE_SYS_RST_BIT (CE_BGR_REG_CE_SYS_RST_OFFSET)

#define CE_SYS_GATING_BIT (CE_BGR_REG_CE_SYS_GATING_OFFSET)


#define CE_MBUS_GATING_MASK (1)

#define CE_MBUS_GATING_BIT (MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET)

#define CE_MBUS_GATING (1)


#define USBEHCI0_RST_BIT 20

#define USBEHCI0_GATIING_BIT 4

#define USBPHY0_RST_BIT 30

#define USBPHY0_SCLK_GATING_BIT 31


#define USBEHCI1_RST_BIT 20

#define USBEHCI1_GATIING_BIT 4

#define USBPHY1_RST_BIT 30

#define USBPHY1_SCLK_GATING_BIT 31


#define CCU_PLL_CPU_L_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x1000)

#define CCU_PLL_CPU_L_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x101c)

#define CCU_PLL_CPU_B_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x2000)

#define CCU_PLL_CPU_B_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x201c)

#define CCU_PLL_CPU_DSU_CTRL_REG (SUNXI_CPU_PLL_CFG_BASE + 0x3000)

#define CCU_PLL_DSU_CLK_REG (SUNXI_CPU_PLL_CFG_BASE + 0x301c)


/* storage */

#define CCU_MBUS_MST_CLK_GATING_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

#define CCU_MBUS_GATE_ENABLE_REG (SUNXI_CCU_BASE + MBUS_GATE_EN_REG)


#define CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG)

#define CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG)

#define CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG)

#define CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_BGR_REG)

/* nsi */

#define CCU_NSI_CLK_GREG (SUNXI_CCU_BASE + NSI_CLK_REG)

#define CCU_NSI_BGR_REG (SUNXI_CCU_BASE + NSI_BGR_REG)

#define CCU_PLL_PERI0_CTRL_REG (SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG)

#define CCU_PLL_PERI1_CTRL_REG (SUNXI_CCU_BASE + PLL_PERI1_CTRL_REG)


/*normal interface*/

#define CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_BGR_REG)


/*DMA*/

#define DMA_GATING_BASE CCU_DMA_BGR_REG

#define DMA_GATING_PASS (1)

#define DMA_GATING_BIT (0)


/*gpadc gate and reset reg*/

#define CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC0_BGR_REG)

#define CCU_GPADC_24M_REG (SUNXI_CCU_BASE + GPADC0_24M_CLK_REG)


/*lpadc gate and reset reg*/

#define CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + LRADC_BGR_REG)


/* RTC */

#define RTC_LOSC_CTRL_REG (SUNXI_RTC_BASE)

#define XO_CONTROL0_REG 0x0160

#define RTC_XO_CONTROL0_REG (SUNXI_RTC_BASE + XO_CONTROL0_REG)


#define LOSC_CONTROL_KEY_FIFLD 0x16aa0000

#define LOSC_AUTO_SWT_32K_SEL_EN_MASK (0x00004000)

#define LOSC_AUTO_SWT_32K_SEL_EN (1U << 14)

#define LOSC_AUTO_SWT_32K_SEL_DISABLE (0U << 14)

#define EXT_LOSC_GSM_HIGH (0x0000000C)

#define LOSC_SRC_SEL_MASK (0x00000001)

#define LOSC_SRC_SEL_32K (1U << 0)

#define LOSC_SRC_SEL_16M (0U << 0)


#endif// __SUN60IW2_REG_CCU_H__

reg-ncat.h