SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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Macros
reg-ccu.h File Reference
#include <reg-ncat.h>
Include dependency graph for reg-ccu.h:

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Macros

#define PLL_REF_CTRL_REG   0x00000000
 
#define PLL_REF_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_REF_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_REF_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_REF_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_REF_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_REF_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET   24
 
#define PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE   0b0
 
#define PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE   0b1
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   16
 
#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x007f0000)
 
#define PLL_REF_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_REF_LOCK_CTRL_REG   0x00000004
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET   4
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING   0b1
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_REF_BIAS_REG   0x00000010
 
#define PLL_REF_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_DDR_CTRL_REG   0x00000020
 
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_DDR_LOCK_CTRL_REG   0x00000024
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET   4
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING   0b1
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_DDR_PAT0_CTRL_REG   0x00000028
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_DDR_PAT1_CTRL_REG   0x0000002c
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_DDR_BIAS_REG   0x00000030
 
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_PERI0_CTRL_REG   0x000000a0
 
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET   25
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK   (0x02000000)
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET   2
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK   (0x0000001c)
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_PERI0_LOCK_CTRL_REG   0x000000a4
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET   4
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING   0b1
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_PERI0_PAT0_CTRL_REG   0x000000a8
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_PERI0_PAT1_CTRL_REG   0x000000ac
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_PERI0_BIAS_REG   0x00000b0
 
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_PERI1_CTRL_REG   0x000000c0
 
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET   25
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK   (0x02000000)
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET   2
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK   (0x0000001c)
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_PERI1_LOCK_CTRL_REG   0x000000c4
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET   4
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING   0b1
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_PERI1_PAT0_CTRL_REG   0x000000c8
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_PERI1_PAT1_CTRL_REG   0x000000cc
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_PERI1_BIAS_REG   0x000000d0
 
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_GPU0_CTRL_REG   0x000000e0
 
#define PLL_GPU0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_GPU0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_GPU0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_GPU0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_GPU0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20
 
#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_GPU0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_GPU0_LOCK_CTRL_REG   0x000000e4
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET   4
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING   0b1
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_GPU0_PAT0_CTRL_REG   0x000000e8
 
#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_GPU0_PAT1_CTRL_REG   0x000000ec
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_GPU0_BIAS_REG   0x000000f0
 
#define PLL_GPU0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_VIDEO0_CTRL_REG   0x00000120
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_VIDEO0_LOCK_CTRL_REG   0x00000124
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET   4
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING   0b1
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000128
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO0_PAT1_CTRL_REG   0x0000012c
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO0_BIAS_REG   0x00000130
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_VIDEO1_CTRL_REG   0x00000140
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_VIDEO1_LOCK_CTRL_REG   0x00000144
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET   4
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING   0b1
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO1_BIAS_REG   0x00000150
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_VIDEO2_CTRL_REG   0x00000160
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_VIDEO2_LOCK_CTRL_REG   0x00000164
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET   4
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING   0b1
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000168
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO2_PAT1_CTRL_REG   0x0000016c
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VIDEO2_BIAS_REG   0x00000170
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_VE0_CTRL_REG   0x00000220
 
#define PLL_VE0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VE0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VE0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_VE0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20
 
#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_VE0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_VE0_LOCK_CTRL_REG   0x00000224
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET   4
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING   0b1
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_VE0_PAT0_CTRL_REG   0x00000228
 
#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VE0_PAT1_CTRL_REG   0x0000022c
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VE0_BIAS_REG   0x00000230
 
#define PLL_VE0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_VE1_CTRL_REG   0x00000240
 
#define PLL_VE1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VE1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VE1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_VE1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20
 
#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_VE1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_VE1_LOCK_CTRL_REG   0x00000244
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET   4
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING   0b1
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_VE1_PAT0_CTRL_REG   0x00000248
 
#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VE1_PAT1_CTRL_REG   0x0000024c
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_VE1_BIAS_REG   0x00000250
 
#define PLL_VE1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_AUDIO0_CTRL_REG   0x00000260
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   16
 
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x007f0000)
 
#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_AUDIO0_LOCK_CTRL_REG   0x00000264
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET   4
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING   0b1
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_AUDIO0_PAT0_CTRL_REG   0x00000268
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_AUDIO0_PAT1_CTRL_REG   0x0000026c
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_AUDIO0_BIAS_REG   0x00000270
 
#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_AUDIO1_CTRL_REG   0x00000280
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET   20
 
#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK   (0x00700000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET   16
 
#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK   (0x00070000)
 
#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_AUDIO1_LOCK_CTRL_REG   0x00000284
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_OFFSET   4
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_PENDING   0b1
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_AUDIO1_PAT0_CTRL_REG   0x00000288
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_AUDIO1_PAT1_CTRL_REG   0x0000028c
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_AUDIO1_BIAS_REG   0x00000290
 
#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_NPU_CTRL_REG   0x000002a0
 
#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_NPU_LOCK_CTRL_REG   0x000002a4
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET   4
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING   0b1
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_NPU_PAT0_CTRL_REG   0x000002a8
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_NPU_PAT1_CTRL_REG   0x000002ac
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_NPU_BIAS_REG   0x000002b0
 
#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define PLL_DE_CTRL_REG   0x000002e0
 
#define PLL_DE_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DE_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_DE_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)
 
#define PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)
 
#define PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_DE_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_DE_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)
 
#define PLL_DE_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1
 
#define PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET   24
 
#define PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)
 
#define PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC   0b0
 
#define PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16
 
#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)
 
#define PLL_DE_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)
 
#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)
 
#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)
 
#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET   1
 
#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)
 
#define PLL_DE_LOCK_CTRL_REG   0x000002e4
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET   4
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK   (0x00000010)
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT   0b0
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING   0b1
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET   0
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE   0b0
 
#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE   0b1
 
#define PLL_DE_PAT0_CTRL_REG   0x000002e8
 
#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10
 
#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11
 
#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)
 
#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19
 
#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)
 
#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)
 
#define PLL_DE_PAT1_CTRL_REG   0x000002ec
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110
 
#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111
 
#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27
 
#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)
 
#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26
 
#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)
 
#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0
 
#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1
 
#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25
 
#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)
 
#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0
 
#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1
 
#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)
 
#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)
 
#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)
 
#define PLL_DE_BIAS_REG   0x000002f0
 
#define PLL_DE_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)
 
#define AHB_CLK_REG   0x00000500
 
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)
 
#define AHB_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define AHB_CLK_REG_FACTOR_M_OFFSET   0
 
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define APB0_CLK_REG   0x00000510
 
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)
 
#define APB0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define APB0_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define APB1_CLK_REG   0x00000518
 
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)
 
#define APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11
 
#define APB1_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define APB_UART_CLK_REG   0x00000538
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b011
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS   0b100
 
#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define TRACE_CLK_REG   0x00000540
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET   31
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TRACE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010
 
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011
 
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define TRACE_CLK_REG_FACTOR_M_OFFSET   0
 
#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define GIC_CLK_REG   0x00000560
 
#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET   31
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define GIC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define GIC_CLK_REG_FACTOR_M_OFFSET   0
 
#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CPU_PERI_CLK_REG   0x00000568
 
#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_OFFSET   31
 
#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100
 
#define CPU_PERI_CLK_REG_FACTOR_M_OFFSET   0
 
#define CPU_PERI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define ITS0_BGR_REG   0x00000574
 
#define ITS0_BGR_REG_ITS_PCIE0_RST_OFFSET   16
 
#define ITS0_BGR_REG_ITS_PCIE0_RST_CLEAR_MASK   (0x00010000)
 
#define ITS0_BGR_REG_ITS_PCIE0_RST_ASSERT   0b0
 
#define ITS0_BGR_REG_ITS_PCIE0_RST_DE_ASSERT   0b1
 
#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_OFFSET   1
 
#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_CLEAR_MASK   (0x00000002)
 
#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_MASK   0b0
 
#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_PASS   0b1
 
#define NSI_CLK_REG   0x00000580
 
#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET   31
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NSI_CLK_REG_NSI_RST_OFFSET   30
 
#define NSI_CLK_REG_NSI_RST_CLEAR_MASK   (0x40000000)
 
#define NSI_CLK_REG_NSI_RST_ASSERT   0b0
 
#define NSI_CLK_REG_NSI_RST_DE_ASSERT   0b1
 
#define NSI_CLK_REG_NSI_DFS_EN_OFFSET   28
 
#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK   (0x10000000)
 
#define NSI_CLK_REG_NSI_DFS_EN_DISABLE   0b0
 
#define NSI_CLK_REG_NSI_DFS_EN_ENABLE   0b1
 
#define NSI_CLK_REG_NSI_UPD_OFFSET   27
 
#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK   (0x08000000)
 
#define NSI_CLK_REG_NSI_UPD_INVALID   0b0
 
#define NSI_CLK_REG_NSI_UPD_VALID   0b1
 
#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET   24
 
#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK   (0x07000000)
 
#define NSI_CLK_REG_NSI_CLK_SEL_SYS_CLK24M   0b000
 
#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL   0b001
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M   0b010
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M   0b011
 
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M   0b100
 
#define NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X   0b101
 
#define NSI_CLK_REG_NSI_DIV1_OFFSET   0
 
#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK   (0x0000001f)
 
#define NSI_BGR_REG   0x00000584
 
#define NSI_BGR_REG_NSI_CFG_RST_OFFSET   16
 
#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK   (0x00010000)
 
#define NSI_BGR_REG_NSI_CFG_RST_ASSERT   0b0
 
#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT   0b1
 
#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET   0
 
#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK   (0x00000001)
 
#define NSI_BGR_REG_NSI_CFG_GATING_MASK   0b0
 
#define NSI_BGR_REG_NSI_CFG_GATING_PASS   0b1
 
#define MBUS_CLK_REG   0x00000588
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET   31
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON   0b1
 
#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET   28
 
#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK   (0x10000000)
 
#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE   0b0
 
#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE   0b1
 
#define MBUS_CLK_REG_MBUS_UPD_OFFSET   27
 
#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK   (0x08000000)
 
#define MBUS_CLK_REG_MBUS_UPD_INVALID   0b0
 
#define MBUS_CLK_REG_MBUS_UPD_VALID   0b1
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET   24
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK   (0x07000000)
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_CLK24M   0b000
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M   0b001
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL   0b010
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M   0b011
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M   0b100
 
#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL   0b101
 
#define MBUS_CLK_REG_MBUS_DIV1_OFFSET   0
 
#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK   (0x0000001f)
 
#define IOMMU0_BGR_REG   0x0000058c
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_OFFSET   16
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_CLEAR_MASK   (0x00010000)
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_ASSERT   0b0
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_DE_ASSERT   0b1
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_OFFSET   2
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_CLEAR_MASK   (0x00000004)
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_MASK   0b0
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_PASS   0b1
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_OFFSET   1
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_CLEAR_MASK   (0x00000002)
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_MASK   0b0
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_PASS   0b1
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_OFFSET   0
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_CLEAR_MASK   (0x00000001)
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_MASK   0b0
 
#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_PASS   0b1
 
#define MSI_LITE0_BGR_REG   0x00000594
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_OFFSET   17
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_CLEAR_MASK   (0x00020000)
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_ASSERT   0b0
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_DE_ASSERT   0b1
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_OFFSET   16
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_CLEAR_MASK   (0x00010000)
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_ASSERT   0b0
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_DE_ASSERT   0b1
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET   0
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK   (0x00000001)
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK   0b0
 
#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS   0b1
 
#define MSI_LITE1_BGR_REG   0x0000059c
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_OFFSET   17
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_CLEAR_MASK   (0x00020000)
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_ASSERT   0b0
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_DE_ASSERT   0b1
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_OFFSET   16
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_CLEAR_MASK   (0x00010000)
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_ASSERT   0b0
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_DE_ASSERT   0b1
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET   0
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK   (0x00000001)
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK   0b0
 
#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS   0b1
 
#define MSI_LITE2_BGR_REG   0x000005a4
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_OFFSET   17
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_CLEAR_MASK   (0x00020000)
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_ASSERT   0b0
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_DE_ASSERT   0b1
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_OFFSET   16
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_CLEAR_MASK   (0x00010000)
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_ASSERT   0b0
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_DE_ASSERT   0b1
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_OFFSET   0
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_CLEAR_MASK   (0x00000001)
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_MASK   0b0
 
#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_PASS   0b1
 
#define IOMMU1_BGR_REG   0x000005b4
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_OFFSET   16
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_CLEAR_MASK   (0x00010000)
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_ASSERT   0b0
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_DE_ASSERT   0b1
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_OFFSET   2
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_CLEAR_MASK   (0x00000004)
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_MASK   0b0
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_PASS   0b1
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_OFFSET   1
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_CLEAR_MASK   (0x00000002)
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_MASK   0b0
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_PASS   0b1
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_OFFSET   0
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_CLEAR_MASK   (0x00000001)
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_MASK   0b0
 
#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_PASS   0b1
 
#define AHB_MAT_CLK_GATING_REG   0x000005c0
 
#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_OFFSET   31
 
#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_CLEAR_MASK   (0x80000000)
 
#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_OFFSET   29
 
#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_CLEAR_MASK   (0x20000000)
 
#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28
 
#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   (0x10000000)
 
#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_OFFSET   24
 
#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_CLEAR_MASK   (0x01000000)
 
#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_OFFSET   16
 
#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_OFFSET   9
 
#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000200)
 
#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_OFFSET   8
 
#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000100)
 
#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_OFFSET   7
 
#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000080)
 
#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_OFFSET   6
 
#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000040)
 
#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_OFFSET   5
 
#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000020)
 
#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_OFFSET   4
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000010)
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_OFFSET   3
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000008)
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2
 
#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000004)
 
#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET   1
 
#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000002)
 
#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET   0
 
#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000001)
 
#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG   0x000005e0
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET   31
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x80000000)
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_OFFSET   30
 
#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x40000000)
 
#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET   29
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x20000000)
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET   28
 
#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x10000000)
 
#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   24
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x01000000)
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   18
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00040000)
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET   16
 
#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET   14
 
#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00004000)
 
#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET   12
 
#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00001000)
 
#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET   11
 
#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000800)
 
#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_OFFSET   1
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000002)
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_OFFSET   0
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000001)
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_GATE_EN_REG   0x000005e4
 
#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_OFFSET   18
 
#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_CLEAR_MASK   (0x00040000)
 
#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET   12
 
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK   (0x00001000)
 
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET   11
 
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK   (0x00000800)
 
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET   9
 
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK   (0x00000200)
 
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET   8
 
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK   (0x00000100)
 
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_NAND_MCLK_EN_OFFSET   5
 
#define MBUS_GATE_EN_REG_NAND_MCLK_EN_CLEAR_MASK   (0x00000020)
 
#define MBUS_GATE_EN_REG_NAND_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_NAND_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET   3
 
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK   (0x00000008)
 
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET   2
 
#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK   (0x00000004)
 
#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG   0b1
 
#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_OFFSET   1
 
#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_CLEAR_MASK   (0x00000002)
 
#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_PASS   0b1
 
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET   0
 
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK   (0x00000001)
 
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK   0b0
 
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS   0b1
 
#define DMA0_BGR_REG   0x00000704
 
#define DMA0_BGR_REG_DMA0_RST_OFFSET   16
 
#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK   (0x00010000)
 
#define DMA0_BGR_REG_DMA0_RST_ASSERT   0b0
 
#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT   0b1
 
#define DMA0_BGR_REG_DMA0_GATING_OFFSET   0
 
#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK   (0x00000001)
 
#define DMA0_BGR_REG_DMA0_GATING_MASK   0b0
 
#define DMA0_BGR_REG_DMA0_GATING_PASS   0b1
 
#define DMA1_BGR_REG   0x0000070c
 
#define DMA1_BGR_REG_DMA1_RST_OFFSET   16
 
#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK   (0x00010000)
 
#define DMA1_BGR_REG_DMA1_RST_ASSERT   0b0
 
#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT   0b1
 
#define DMA1_BGR_REG_DMA1_GATING_OFFSET   0
 
#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK   (0x00000001)
 
#define DMA1_BGR_REG_DMA1_GATING_MASK   0b0
 
#define DMA1_BGR_REG_DMA1_GATING_PASS   0b1
 
#define SPINLOCK_BGR_REG   0x00000724
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   (0x00010000)
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0b0
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0b1
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   (0x00000001)
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0b0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0b1
 
#define MSGBOX0_BGR_REG   0x00000744
 
#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET   16
 
#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK   (0x00010000)
 
#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT   0b0
 
#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT   0b1
 
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET   0
 
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   (0x00000001)
 
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK   0b0
 
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS   0b1
 
#define PWM0_BGR_REG   0x00000784
 
#define PWM0_BGR_REG_PWM0_RST_OFFSET   16
 
#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK   (0x00010000)
 
#define PWM0_BGR_REG_PWM0_RST_ASSERT   0b0
 
#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT   0b1
 
#define PWM0_BGR_REG_PWM0_GATING_OFFSET   0
 
#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK   (0x00000001)
 
#define PWM0_BGR_REG_PWM0_GATING_MASK   0b0
 
#define PWM0_BGR_REG_PWM0_GATING_PASS   0b1
 
#define PWM1_BGR_REG   0x0000078c
 
#define PWM1_BGR_REG_PWM1_RST_OFFSET   16
 
#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK   (0x00010000)
 
#define PWM1_BGR_REG_PWM1_RST_ASSERT   0b0
 
#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT   0b1
 
#define PWM1_BGR_REG_PWM1_GATING_OFFSET   0
 
#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK   (0x00000001)
 
#define PWM1_BGR_REG_PWM1_GATING_MASK   0b0
 
#define PWM1_BGR_REG_PWM1_GATING_PASS   0b1
 
#define DBGSYS_BGR_REG   0x000007a4
 
#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16
 
#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   (0x00010000)
 
#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0b0
 
#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0b1
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   (0x00000001)
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0b0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0b1
 
#define SYSDAP_BGR_REG   0x000007ac
 
#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET   16
 
#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK   (0x00010000)
 
#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT   0b0
 
#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG   0b1
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET   0
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK   (0x00000001)
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK   0b0
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG   0b1
 
#define TIMER0_CLK0_CLK_REG   0x00000800
 
#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK0_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK1_CLK_REG   0x00000804
 
#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK1_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK2_CLK_REG   0x00000808
 
#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK2_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK3_CLK_REG   0x0000080c
 
#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK3_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK4_CLK_REG   0x00000810
 
#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK4_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK5_CLK_REG   0x00000814
 
#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK5_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK6_CLK_REG   0x00000818
 
#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK6_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK7_CLK_REG   0x0000081c
 
#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK7_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK8_CLK_REG   0x00000820
 
#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK8_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_CLK9_CLK_REG   0x00000824
 
#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE   0b0
 
#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE   0b1
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K   0b010
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC   0b100
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET   0
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__1   0b000
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__2   0b001
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__4   0b010
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__8   0b011
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__16   0b100
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__32   0b101
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__64   0b110
 
#define TIMER0_CLK9_CLK_REG_FACTOR_P__128   0b111
 
#define TIMER0_BGR_REG   0x00000850
 
#define TIMER0_BGR_REG_TIMER0_RST_OFFSET   16
 
#define TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK   (0x00010000)
 
#define TIMER0_BGR_REG_TIMER0_RST_ASSERT   0b0
 
#define TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT   0b1
 
#define TIMER0_BGR_REG_TIMER0_GATING_OFFSET   0
 
#define TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK   (0x00000001)
 
#define TIMER0_BGR_REG_TIMER0_GATING_MASK   0b0
 
#define TIMER0_BGR_REG_TIMER0_GATING_PASS   0b1
 
#define AVS_CLK_REG   0x00000880
 
#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AVS_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AVS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define AVS_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define AVS_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define DE0_CLK_REG   0x00000a00
 
#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET   31
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b000
 
#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X   0b001
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b110
 
#define DE0_CLK_REG_FACTOR_M_OFFSET   0
 
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define DE0_BGR_REG   0x00000a04
 
#define DE0_BGR_REG_DE0_RST_OFFSET   16
 
#define DE0_BGR_REG_DE0_RST_CLEAR_MASK   (0x00010000)
 
#define DE0_BGR_REG_DE0_RST_ASSERT   0b0
 
#define DE0_BGR_REG_DE0_RST_DE_ASSERT   0b1
 
#define DE0_BGR_REG_DE0_GATING_OFFSET   0
 
#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK   (0x00000001)
 
#define DE0_BGR_REG_DE0_GATING_MASK   0b0
 
#define DE0_BGR_REG_DE0_GATING_PASS   0b1
 
#define DI_CLK_REG   0x00000a20
 
#define DI_CLK_REG_DI_CLK_GATING_OFFSET   31
 
#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define DI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000
 
#define DI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010
 
#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b011
 
#define DI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b100
 
#define DI_CLK_REG_FACTOR_M_OFFSET   0
 
#define DI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define DI_BGR_REG   0x00000a24
 
#define DI_BGR_REG_DI_RST_OFFSET   16
 
#define DI_BGR_REG_DI_RST_CLEAR_MASK   (0x00010000)
 
#define DI_BGR_REG_DI_RST_ASSERT   0b0
 
#define DI_BGR_REG_DI_RST_DE_ASSERT   0b1
 
#define DI_BGR_REG_DI_GATING_OFFSET   0
 
#define DI_BGR_REG_DI_GATING_CLEAR_MASK   (0x00000001)
 
#define DI_BGR_REG_DI_GATING_MASK   0b0
 
#define DI_BGR_REG_DI_GATING_PASS   0b1
 
#define G2D_CLK_REG   0x00000a40
 
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1
 
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b010
 
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011
 
#define G2D_CLK_REG_FACTOR_M_OFFSET   0
 
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define G2D_BGR_REG   0x00000a44
 
#define G2D_BGR_REG_G2D_RST_OFFSET   16
 
#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   (0x00010000)
 
#define G2D_BGR_REG_G2D_RST_ASSERT   0b0
 
#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0b1
 
#define G2D_BGR_REG_G2D_GATING_OFFSET   0
 
#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   (0x00000001)
 
#define G2D_BGR_REG_G2D_GATING_MASK   0b0
 
#define G2D_BGR_REG_G2D_GATING_PASS   0b1
 
#define EINK_CLK_REG   0x00000a60
 
#define EINK_CLK_REG_EINK_CLK_GATING_OFFSET   31
 
#define EINK_CLK_REG_EINK_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_ON   0b1
 
#define EINK_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define EINK_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b000
 
#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define EINK_CLK_REG_FACTOR_M_OFFSET   0
 
#define EINK_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define EINK_PANEL_CLK_REG   0x00000a64
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET   31
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON   0b1
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b001
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b010
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b011
 
#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100
 
#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET   0
 
#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define EINK_BGR_REG   0x00000a6c
 
#define EINK_BGR_REG_EINK_RST_OFFSET   16
 
#define EINK_BGR_REG_EINK_RST_CLEAR_MASK   (0x00010000)
 
#define EINK_BGR_REG_EINK_RST_ASSERT   0b0
 
#define EINK_BGR_REG_EINK_RST_DE_ASSERT   0b1
 
#define EINK_BGR_REG_EINK_GATING_OFFSET   0
 
#define EINK_BGR_REG_EINK_GATING_CLEAR_MASK   (0x00000001)
 
#define EINK_BGR_REG_EINK_GATING_MASK   0b0
 
#define EINK_BGR_REG_EINK_GATING_PASS   0b1
 
#define DE_SYS_BGR_REG   0x00000a74
 
#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET   16
 
#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK   (0x00010000)
 
#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT   0b0
 
#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT   0b1
 
#define VE_ENC0_CLK_REG   0x00000a80
 
#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET   31
 
#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL   0b000
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL   0b001
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b010
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b100
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b101
 
#define VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL   0b110
 
#define VE_ENC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VE_DEC_CLK_REG   0x00000a88
 
#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET   31
 
#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL   0b000
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL   0b001
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b010
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b100
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b101
 
#define VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL   0b110
 
#define VE_DEC_CLK_REG_FACTOR_M_OFFSET   0
 
#define VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VE_BGR_REG   0x00000a8c
 
#define VE_BGR_REG_VE_DEC_RST_OFFSET   18
 
#define VE_BGR_REG_VE_DEC_RST_CLEAR_MASK   (0x00040000)
 
#define VE_BGR_REG_VE_DEC_RST_ASSERT   0b0
 
#define VE_BGR_REG_VE_DEC_RST_DE_ASSERT   0b1
 
#define VE_BGR_REG_VE_ENC0_RST_OFFSET   16
 
#define VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK   (0x00010000)
 
#define VE_BGR_REG_VE_ENC0_RST_ASSERT   0b0
 
#define VE_BGR_REG_VE_ENC0_RST_DE_ASSERT   0b1
 
#define VE_BGR_REG_VE_DEC_GATING_OFFSET   2
 
#define VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK   (0x00000004)
 
#define VE_BGR_REG_VE_DEC_GATING_MASK   0b0
 
#define VE_BGR_REG_VE_DEC_GATING_PASS   0b1
 
#define VE_BGR_REG_VE_ENC0_GATING_OFFSET   0
 
#define VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK   (0x00000001)
 
#define VE_BGR_REG_VE_ENC0_GATING_MASK   0b0
 
#define VE_BGR_REG_VE_ENC0_GATING_PASS   0b1
 
#define CE_CLK_REG   0x00000ac0
 
#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31
 
#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG   0b1
 
#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define CE_CLK_REG_FACTOR_M_OFFSET   0
 
#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CE_BGR_REG   0x00000ac4
 
#define CE_BGR_REG_CE_SYS_RST_OFFSET   17
 
#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   (0x00020000)
 
#define CE_BGR_REG_CE_SYS_RST_ASSERT   0b0
 
#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG   0b1
 
#define CE_BGR_REG_CE_RST_OFFSET   16
 
#define CE_BGR_REG_CE_RST_CLEAR_MASK   (0x00010000)
 
#define CE_BGR_REG_CE_RST_ASSERT   0b0
 
#define CE_BGR_REG_CE_RST_SECURE_DEBUG   0b1
 
#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1
 
#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   (0x00000002)
 
#define CE_BGR_REG_CE_SYS_GATING_MASK   0b0
 
#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG   0b1
 
#define CE_BGR_REG_CE_GATING_OFFSET   0
 
#define CE_BGR_REG_CE_GATING_CLEAR_MASK   (0x00000001)
 
#define CE_BGR_REG_CE_GATING_MASK   0b0
 
#define CE_BGR_REG_CE_GATING_SECURE_DEBUG   0b1
 
#define NPU_CLK_REG   0x00000b00
 
#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL   0b000
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define NPU_CLK_REG_CLK_SRC_SEL_VE0PLL   0b100
 
#define NPU_CLK_REG_CLK_SRC_SEL_VE1PLL   0b101
 
#define NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b110
 
#define NPU_CLK_REG_FACTOR_M_OFFSET   0
 
#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define NPU_BGR_REG   0x00000b04
 
#define NPU_BGR_REG_NPU_SRAM_RST_OFFSET   19
 
#define NPU_BGR_REG_NPU_SRAM_RST_CLEAR_MASK   (0x00080000)
 
#define NPU_BGR_REG_NPU_SRAM_RST_ASSERT   0b0
 
#define NPU_BGR_REG_NPU_SRAM_RST_DE_ASSERT   0b1
 
#define NPU_BGR_REG_NPU_AHB_RST_OFFSET   18
 
#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK   (0x00040000)
 
#define NPU_BGR_REG_NPU_AHB_RST_ASSERT   0b0
 
#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT   0b1
 
#define NPU_BGR_REG_NPU_AXI_RST_OFFSET   17
 
#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK   (0x00020000)
 
#define NPU_BGR_REG_NPU_AXI_RST_ASSERT   0b0
 
#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT   0b1
 
#define NPU_BGR_REG_NPU_CORE_RST_OFFSET   16
 
#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK   (0x00010000)
 
#define NPU_BGR_REG_NPU_CORE_RST_ASSERT   0b0
 
#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT   0b1
 
#define NPU_BGR_REG_NPU_GATING_OFFSET   0
 
#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK   (0x00000001)
 
#define NPU_BGR_REG_NPU_GATING_MASK   0b0
 
#define NPU_BGR_REG_NPU_GATING_PASS   0b1
 
#define DRAM0_CLK_REG   0x00000c00
 
#define DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET   31
 
#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DRAM0_CLK_REG_DRAM0_UPD_OFFSET   27
 
#define DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK   (0x08000000)
 
#define DRAM0_CLK_REG_DRAM0_UPD_INVALID   0b0
 
#define DRAM0_CLK_REG_DRAM0_UPD_VALID   0b1
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET   24
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK   (0x07000000)
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL   0b000
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M   0b001
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M   0b010
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X   0b011
 
#define DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL   0b100
 
#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET   16
 
#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK   (0x00010000)
 
#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY   0b0
 
#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_8   0b1
 
#define DRAM0_CLK_REG_DRAM0_DIV1_OFFSET   0
 
#define DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK   (0x0000001f)
 
#define DRAM0_BGR_REG   0x00000c0c
 
#define DRAM0_BGR_REG_DRAM0_RST_OFFSET   16
 
#define DRAM0_BGR_REG_DRAM0_RST_CLEAR_MASK   (0x00010000)
 
#define DRAM0_BGR_REG_DRAM0_RST_ASSERT   0b0
 
#define DRAM0_BGR_REG_DRAM0_RST_DE_ASSERT   0b1
 
#define DRAM0_BGR_REG_DRAM0_GATING_OFFSET   0
 
#define DRAM0_BGR_REG_DRAM0_GATING_CLEAR_MASK   (0x00000001)
 
#define DRAM0_BGR_REG_DRAM0_GATING_MASK   0b0
 
#define DRAM0_BGR_REG_DRAM0_GATING_PASS   0b1
 
#define NAND0_CLK0_CLK_REG   0x00000c80
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET   31
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET   0
 
#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define NAND0_CLK1_CLK_REG   0x00000c84
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET   31
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET   0
 
#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define NAND0_BGR_REG   0x00000c8c
 
#define NAND0_BGR_REG_NAND0_RST_OFFSET   16
 
#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK   (0x00010000)
 
#define NAND0_BGR_REG_NAND0_RST_ASSERT   0b0
 
#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT   0b1
 
#define NAND0_BGR_REG_NAND0_GATING_OFFSET   0
 
#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK   (0x00000001)
 
#define NAND0_BGR_REG_NAND0_GATING_MASK   0b0
 
#define NAND0_BGR_REG_NAND0_GATING_PASS   0b1
 
#define SMHC0_CLK_REG   0x00000d00
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SMHC0_BGR_REG   0x00000d0c
 
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   16
 
#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK   (0x00010000)
 
#define SMHC0_BGR_REG_SMHC0_RST_ASSERT   0b0
 
#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT   0b1
 
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET   0
 
#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK   (0x00000001)
 
#define SMHC0_BGR_REG_SMHC0_GATING_MASK   0b0
 
#define SMHC0_BGR_REG_SMHC0_GATING_PASS   0b1
 
#define SMHC1_CLK_REG   0x00000d10
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SMHC1_BGR_REG   0x00000d1c
 
#define SMHC1_BGR_REG_SMHC1_RST_OFFSET   16
 
#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK   (0x00010000)
 
#define SMHC1_BGR_REG_SMHC1_RST_ASSERT   0b0
 
#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT   0b1
 
#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET   0
 
#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK   (0x00000001)
 
#define SMHC1_BGR_REG_SMHC1_GATING_MASK   0b0
 
#define SMHC1_BGR_REG_SMHC1_GATING_PASS   0b1
 
#define SMHC2_CLK_REG   0x00000d20
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100
 
#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SMHC2_BGR_REG   0x00000d2c
 
#define SMHC2_BGR_REG_SMHC2_RST_OFFSET   16
 
#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK   (0x00010000)
 
#define SMHC2_BGR_REG_SMHC2_RST_ASSERT   0b0
 
#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT   0b1
 
#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET   0
 
#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK   (0x00000001)
 
#define SMHC2_BGR_REG_SMHC2_GATING_MASK   0b0
 
#define SMHC2_BGR_REG_SMHC2_GATING_PASS   0b1
 
#define SMHC3_CLK_REG   0x00000d30
 
#define SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET   31
 
#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011
 
#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100
 
#define SMHC3_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SMHC3_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SMHC3_BGR_REG   0x00000d3c
 
#define SMHC3_BGR_REG_SMHC3_RST_OFFSET   16
 
#define SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK   (0x00010000)
 
#define SMHC3_BGR_REG_SMHC3_RST_ASSERT   0b0
 
#define SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT   0b1
 
#define SMHC3_BGR_REG_SMHC3_GATING_OFFSET   0
 
#define SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK   (0x00000001)
 
#define SMHC3_BGR_REG_SMHC3_GATING_MASK   0b0
 
#define SMHC3_BGR_REG_SMHC3_GATING_PASS   0b1
 
#define UFS_AXI_CLK_REG   0x00000d80
 
#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET   31
 
#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000
 
#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define UFS_AXI_CLK_REG_FACTOR_M_OFFSET   0
 
#define UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define UFS_CFG_CLK_REG   0x00000d84
 
#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_OFFSET   31
 
#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_ON   0b1
 
#define UFS_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define UFS_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define UFS_CFG_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b000
 
#define UFS_CFG_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define UFS_CFG_CLK_REG_FACTOR_M_OFFSET   0
 
#define UFS_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define UFS_BGR_REG   0x00000d8c
 
#define UFS_BGR_REG_UFS_CORE_RST_OFFSET   19
 
#define UFS_BGR_REG_UFS_CORE_RST_CLEAR_MASK   (0x00080000)
 
#define UFS_BGR_REG_UFS_CORE_RST_ASSERT   0b0
 
#define UFS_BGR_REG_UFS_CORE_RST_DE_ASSERT   0b1
 
#define UFS_BGR_REG_UFS_PHY_RST_OFFSET   18
 
#define UFS_BGR_REG_UFS_PHY_RST_CLEAR_MASK   (0x00040000)
 
#define UFS_BGR_REG_UFS_PHY_RST_ASSERT   0b0
 
#define UFS_BGR_REG_UFS_PHY_RST_DE_ASSERT   0b1
 
#define UFS_BGR_REG_UFS_AXI_RST_OFFSET   17
 
#define UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK   (0x00020000)
 
#define UFS_BGR_REG_UFS_AXI_RST_ASSERT   0b0
 
#define UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT   0b1
 
#define UFS_BGR_REG_UFS_RST_OFFSET   16
 
#define UFS_BGR_REG_UFS_RST_CLEAR_MASK   (0x00010000)
 
#define UFS_BGR_REG_UFS_RST_ASSERT   0b0
 
#define UFS_BGR_REG_UFS_RST_DE_ASSERT   0b1
 
#define UFS_BGR_REG_UFS_GATING_OFFSET   0
 
#define UFS_BGR_REG_UFS_GATING_CLEAR_MASK   (0x00000001)
 
#define UFS_BGR_REG_UFS_GATING_MASK   0b0
 
#define UFS_BGR_REG_UFS_GATING_PASS   0b1
 
#define UFS_REF_CLK_EN_REG   0x00000d90
 
#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_OFFSET   0
 
#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_CLEAR_MASK   (0x00000001)
 
#define UART0_BGR_REG   0x00000e00
 
#define UART0_BGR_REG_UART0_RST_OFFSET   16
 
#define UART0_BGR_REG_UART0_RST_CLEAR_MASK   (0x00010000)
 
#define UART0_BGR_REG_UART0_RST_ASSERT   0b0
 
#define UART0_BGR_REG_UART0_RST_DE_ASSERT   0b1
 
#define UART0_BGR_REG_UART0_GATING_OFFSET   0
 
#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK   (0x00000001)
 
#define UART0_BGR_REG_UART0_GATING_MASK   0b0
 
#define UART0_BGR_REG_UART0_GATING_PASS   0b1
 
#define UART1_BGR_REG   0x00000e04
 
#define UART1_BGR_REG_UART1_RST_OFFSET   16
 
#define UART1_BGR_REG_UART1_RST_CLEAR_MASK   (0x00010000)
 
#define UART1_BGR_REG_UART1_RST_ASSERT   0b0
 
#define UART1_BGR_REG_UART1_RST_DE_ASSERT   0b1
 
#define UART1_BGR_REG_UART1_GATING_OFFSET   0
 
#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK   (0x00000001)
 
#define UART1_BGR_REG_UART1_GATING_MASK   0b0
 
#define UART1_BGR_REG_UART1_GATING_PASS   0b1
 
#define UART2_BGR_REG   0x00000e08
 
#define UART2_BGR_REG_UART2_RST_OFFSET   16
 
#define UART2_BGR_REG_UART2_RST_CLEAR_MASK   (0x00010000)
 
#define UART2_BGR_REG_UART2_RST_ASSERT   0b0
 
#define UART2_BGR_REG_UART2_RST_DE_ASSERT   0b1
 
#define UART2_BGR_REG_UART2_GATING_OFFSET   0
 
#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK   (0x00000001)
 
#define UART2_BGR_REG_UART2_GATING_MASK   0b0
 
#define UART2_BGR_REG_UART2_GATING_PASS   0b1
 
#define UART3_BGR_REG   0x00000e0c
 
#define UART3_BGR_REG_UART3_RST_OFFSET   16
 
#define UART3_BGR_REG_UART3_RST_CLEAR_MASK   (0x00010000)
 
#define UART3_BGR_REG_UART3_RST_ASSERT   0b0
 
#define UART3_BGR_REG_UART3_RST_DE_ASSERT   0b1
 
#define UART3_BGR_REG_UART3_GATING_OFFSET   0
 
#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK   (0x00000001)
 
#define UART3_BGR_REG_UART3_GATING_MASK   0b0
 
#define UART3_BGR_REG_UART3_GATING_PASS   0b1
 
#define UART4_BGR_REG   0x00000e10
 
#define UART4_BGR_REG_UART4_RST_OFFSET   16
 
#define UART4_BGR_REG_UART4_RST_CLEAR_MASK   (0x00010000)
 
#define UART4_BGR_REG_UART4_RST_ASSERT   0b0
 
#define UART4_BGR_REG_UART4_RST_DE_ASSERT   0b1
 
#define UART4_BGR_REG_UART4_GATING_OFFSET   0
 
#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK   (0x00000001)
 
#define UART4_BGR_REG_UART4_GATING_MASK   0b0
 
#define UART4_BGR_REG_UART4_GATING_PASS   0b1
 
#define UART5_BGR_REG   0x00000e14
 
#define UART5_BGR_REG_UART5_RST_OFFSET   16
 
#define UART5_BGR_REG_UART5_RST_CLEAR_MASK   (0x00010000)
 
#define UART5_BGR_REG_UART5_RST_ASSERT   0b0
 
#define UART5_BGR_REG_UART5_RST_DE_ASSERT   0b1
 
#define UART5_BGR_REG_UART5_GATING_OFFSET   0
 
#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK   (0x00000001)
 
#define UART5_BGR_REG_UART5_GATING_MASK   0b0
 
#define UART5_BGR_REG_UART5_GATING_PASS   0b1
 
#define UART6_BGR_REG   0x00000e18
 
#define UART6_BGR_REG_UART6_RST_OFFSET   16
 
#define UART6_BGR_REG_UART6_RST_CLEAR_MASK   (0x00010000)
 
#define UART6_BGR_REG_UART6_RST_ASSERT   0b0
 
#define UART6_BGR_REG_UART6_RST_DE_ASSERT   0b1
 
#define UART6_BGR_REG_UART6_GATING_OFFSET   0
 
#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK   (0x00000001)
 
#define UART6_BGR_REG_UART6_GATING_MASK   0b0
 
#define UART6_BGR_REG_UART6_GATING_PASS   0b1
 
#define TWI0_BGR_REG   0x00000e80
 
#define TWI0_BGR_REG_TWI0_RST_OFFSET   16
 
#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK   (0x00010000)
 
#define TWI0_BGR_REG_TWI0_RST_ASSERT   0b0
 
#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT   0b1
 
#define TWI0_BGR_REG_TWI0_GATING_OFFSET   0
 
#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI0_BGR_REG_TWI0_GATING_MASK   0b0
 
#define TWI0_BGR_REG_TWI0_GATING_PASS   0b1
 
#define TWI1_BGR_REG   0x00000e84
 
#define TWI1_BGR_REG_TWI1_RST_OFFSET   16
 
#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK   (0x00010000)
 
#define TWI1_BGR_REG_TWI1_RST_ASSERT   0b0
 
#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT   0b1
 
#define TWI1_BGR_REG_TWI1_GATING_OFFSET   0
 
#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI1_BGR_REG_TWI1_GATING_MASK   0b0
 
#define TWI1_BGR_REG_TWI1_GATING_PASS   0b1
 
#define TWI2_BGR_REG   0x00000e88
 
#define TWI2_BGR_REG_TWI2_RST_OFFSET   16
 
#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK   (0x00010000)
 
#define TWI2_BGR_REG_TWI2_RST_ASSERT   0b0
 
#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT   0b1
 
#define TWI2_BGR_REG_TWI2_GATING_OFFSET   0
 
#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI2_BGR_REG_TWI2_GATING_MASK   0b0
 
#define TWI2_BGR_REG_TWI2_GATING_PASS   0b1
 
#define TWI3_BGR_REG   0x00000e8c
 
#define TWI3_BGR_REG_TWI3_RST_OFFSET   16
 
#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK   (0x00010000)
 
#define TWI3_BGR_REG_TWI3_RST_ASSERT   0b0
 
#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT   0b1
 
#define TWI3_BGR_REG_TWI3_GATING_OFFSET   0
 
#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI3_BGR_REG_TWI3_GATING_MASK   0b0
 
#define TWI3_BGR_REG_TWI3_GATING_PASS   0b1
 
#define TWI4_BGR_REG   0x00000e90
 
#define TWI4_BGR_REG_TWI4_RST_OFFSET   16
 
#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK   (0x00010000)
 
#define TWI4_BGR_REG_TWI4_RST_ASSERT   0b0
 
#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT   0b1
 
#define TWI4_BGR_REG_TWI4_GATING_OFFSET   0
 
#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI4_BGR_REG_TWI4_GATING_MASK   0b0
 
#define TWI4_BGR_REG_TWI4_GATING_PASS   0b1
 
#define TWI5_BGR_REG   0x00000e94
 
#define TWI5_BGR_REG_TWI5_RST_OFFSET   16
 
#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK   (0x00010000)
 
#define TWI5_BGR_REG_TWI5_RST_ASSERT   0b0
 
#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT   0b1
 
#define TWI5_BGR_REG_TWI5_GATING_OFFSET   0
 
#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI5_BGR_REG_TWI5_GATING_MASK   0b0
 
#define TWI5_BGR_REG_TWI5_GATING_PASS   0b1
 
#define TWI6_BGR_REG   0x00000e98
 
#define TWI6_BGR_REG_TWI6_RST_OFFSET   16
 
#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK   (0x00010000)
 
#define TWI6_BGR_REG_TWI6_RST_ASSERT   0b0
 
#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT   0b1
 
#define TWI6_BGR_REG_TWI6_GATING_OFFSET   0
 
#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI6_BGR_REG_TWI6_GATING_MASK   0b0
 
#define TWI6_BGR_REG_TWI6_GATING_PASS   0b1
 
#define TWI7_BGR_REG   0x00000e9c
 
#define TWI7_BGR_REG_TWI7_RST_OFFSET   16
 
#define TWI7_BGR_REG_TWI7_RST_CLEAR_MASK   (0x00010000)
 
#define TWI7_BGR_REG_TWI7_RST_ASSERT   0b0
 
#define TWI7_BGR_REG_TWI7_RST_DE_ASSERT   0b1
 
#define TWI7_BGR_REG_TWI7_GATING_OFFSET   0
 
#define TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI7_BGR_REG_TWI7_GATING_MASK   0b0
 
#define TWI7_BGR_REG_TWI7_GATING_PASS   0b1
 
#define TWI8_BGR_REG   0x00000ea0
 
#define TWI8_BGR_REG_TWI8_RST_OFFSET   16
 
#define TWI8_BGR_REG_TWI8_RST_CLEAR_MASK   (0x00010000)
 
#define TWI8_BGR_REG_TWI8_RST_ASSERT   0b0
 
#define TWI8_BGR_REG_TWI8_RST_DE_ASSERT   0b1
 
#define TWI8_BGR_REG_TWI8_GATING_OFFSET   0
 
#define TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI8_BGR_REG_TWI8_GATING_MASK   0b0
 
#define TWI8_BGR_REG_TWI8_GATING_PASS   0b1
 
#define TWI9_BGR_REG   0x00000ea4
 
#define TWI9_BGR_REG_TWI9_RST_OFFSET   16
 
#define TWI9_BGR_REG_TWI9_RST_CLEAR_MASK   (0x00010000)
 
#define TWI9_BGR_REG_TWI9_RST_ASSERT   0b0
 
#define TWI9_BGR_REG_TWI9_RST_DE_ASSERT   0b1
 
#define TWI9_BGR_REG_TWI9_GATING_OFFSET   0
 
#define TWI9_BGR_REG_TWI9_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI9_BGR_REG_TWI9_GATING_MASK   0b0
 
#define TWI9_BGR_REG_TWI9_GATING_PASS   0b1
 
#define TWI10_BGR_REG   0x00000ea8
 
#define TWI10_BGR_REG_TWI10_RST_OFFSET   16
 
#define TWI10_BGR_REG_TWI10_RST_CLEAR_MASK   (0x00010000)
 
#define TWI10_BGR_REG_TWI10_RST_ASSERT   0b0
 
#define TWI10_BGR_REG_TWI10_RST_DE_ASSERT   0b1
 
#define TWI10_BGR_REG_TWI10_GATING_OFFSET   0
 
#define TWI10_BGR_REG_TWI10_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI10_BGR_REG_TWI10_GATING_MASK   0b0
 
#define TWI10_BGR_REG_TWI10_GATING_PASS   0b1
 
#define TWI11_BGR_REG   0x00000eac
 
#define TWI11_BGR_REG_TWI11_RST_OFFSET   16
 
#define TWI11_BGR_REG_TWI11_RST_CLEAR_MASK   (0x00010000)
 
#define TWI11_BGR_REG_TWI11_RST_ASSERT   0b0
 
#define TWI11_BGR_REG_TWI11_RST_DE_ASSERT   0b1
 
#define TWI11_BGR_REG_TWI11_GATING_OFFSET   0
 
#define TWI11_BGR_REG_TWI11_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI11_BGR_REG_TWI11_GATING_MASK   0b0
 
#define TWI11_BGR_REG_TWI11_GATING_PASS   0b1
 
#define TWI12_BGR_REG   0x00000eb0
 
#define TWI12_BGR_REG_TWI12_RST_OFFSET   16
 
#define TWI12_BGR_REG_TWI12_RST_CLEAR_MASK   (0x00010000)
 
#define TWI12_BGR_REG_TWI12_RST_ASSERT   0b0
 
#define TWI12_BGR_REG_TWI12_RST_DE_ASSERT   0b1
 
#define TWI12_BGR_REG_TWI12_GATING_OFFSET   0
 
#define TWI12_BGR_REG_TWI12_GATING_CLEAR_MASK   (0x00000001)
 
#define TWI12_BGR_REG_TWI12_GATING_MASK   0b0
 
#define TWI12_BGR_REG_TWI12_GATING_PASS   0b1
 
#define SPI0_CLK_REG   0x00000f00
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110
 
#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPI0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPI0_BGR_REG   0x00000f04
 
#define SPI0_BGR_REG_SPI0_RST_OFFSET   16
 
#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK   (0x00010000)
 
#define SPI0_BGR_REG_SPI0_RST_ASSERT   0b0
 
#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT   0b1
 
#define SPI0_BGR_REG_SPI0_GATING_OFFSET   0
 
#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK   (0x00000001)
 
#define SPI0_BGR_REG_SPI0_GATING_MASK   0b0
 
#define SPI0_BGR_REG_SPI0_GATING_PASS   0b1
 
#define SPI1_CLK_REG   0x00000f08
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110
 
#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPI1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPI1_BGR_REG   0x00000f0c
 
#define SPI1_BGR_REG_SPI1_RST_OFFSET   16
 
#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK   (0x00010000)
 
#define SPI1_BGR_REG_SPI1_RST_ASSERT   0b0
 
#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT   0b1
 
#define SPI1_BGR_REG_SPI1_GATING_OFFSET   0
 
#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK   (0x00000001)
 
#define SPI1_BGR_REG_SPI1_GATING_MASK   0b0
 
#define SPI1_BGR_REG_SPI1_GATING_PASS   0b1
 
#define SPI2_CLK_REG   0x00000f10
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110
 
#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPI2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPI2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPI2_BGR_REG   0x00000f14
 
#define SPI2_BGR_REG_SPI2_RST_OFFSET   16
 
#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK   (0x00010000)
 
#define SPI2_BGR_REG_SPI2_RST_ASSERT   0b0
 
#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT   0b1
 
#define SPI2_BGR_REG_SPI2_GATING_OFFSET   0
 
#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK   (0x00000001)
 
#define SPI2_BGR_REG_SPI2_GATING_MASK   0b0
 
#define SPI2_BGR_REG_SPI2_GATING_PASS   0b1
 
#define SPIF_CLK_REG   0x00000f18
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M   0b101
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M   0b110
 
#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPIF_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPIF_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPIF_BGR_REG   0x00000f1c
 
#define SPIF_BGR_REG_SPIF_RST_OFFSET   16
 
#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK   (0x00010000)
 
#define SPIF_BGR_REG_SPIF_RST_ASSERT   0b0
 
#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT   0b1
 
#define SPIF_BGR_REG_SPIF_GATING_OFFSET   0
 
#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK   (0x00000001)
 
#define SPIF_BGR_REG_SPIF_GATING_MASK   0b0
 
#define SPIF_BGR_REG_SPIF_GATING_PASS   0b1
 
#define SPI3_CLK_REG   0x00000f20
 
#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET   31
 
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPI3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101
 
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110
 
#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPI3_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPI3_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPI3_BGR_REG   0x00000f24
 
#define SPI3_BGR_REG_SPI3_RST_OFFSET   16
 
#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK   (0x00010000)
 
#define SPI3_BGR_REG_SPI3_RST_ASSERT   0b0
 
#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT   0b1
 
#define SPI3_BGR_REG_SPI3_GATING_OFFSET   0
 
#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK   (0x00000001)
 
#define SPI3_BGR_REG_SPI3_GATING_MASK   0b0
 
#define SPI3_BGR_REG_SPI3_GATING_PASS   0b1
 
#define SPI4_CLK_REG   0x00000f28
 
#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET   31
 
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPI4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101
 
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110
 
#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC   0b111
 
#define SPI4_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define SPI4_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPI4_BGR_REG   0x00000f2c
 
#define SPI4_BGR_REG_SPI4_RST_OFFSET   16
 
#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK   (0x00010000)
 
#define SPI4_BGR_REG_SPI4_RST_ASSERT   0b0
 
#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT   0b1
 
#define SPI4_BGR_REG_SPI4_GATING_OFFSET   0
 
#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK   (0x00000001)
 
#define SPI4_BGR_REG_SPI4_GATING_MASK   0b0
 
#define SPI4_BGR_REG_SPI4_GATING_PASS   0b1
 
#define GPADC0_24M_CLK_REG   0x00000fc0
 
#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET   31
 
#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define GPADC0_24M_CLK_REG_FACTOR_M_OFFSET   0
 
#define GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define GPADC0_BGR_REG   0x00000fc4
 
#define GPADC0_BGR_REG_GPADC0_RST_OFFSET   16
 
#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK   (0x00010000)
 
#define GPADC0_BGR_REG_GPADC0_RST_ASSERT   0b0
 
#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT   0b1
 
#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET   0
 
#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK   (0x00000001)
 
#define GPADC0_BGR_REG_GPADC0_GATING_MASK   0b0
 
#define GPADC0_BGR_REG_GPADC0_GATING_PASS   0b1
 
#define THS0_BGR_REG   0x00000fe4
 
#define THS0_BGR_REG_THS0_RST_OFFSET   16
 
#define THS0_BGR_REG_THS0_RST_CLEAR_MASK   (0x00010000)
 
#define THS0_BGR_REG_THS0_RST_ASSERT   0b0
 
#define THS0_BGR_REG_THS0_RST_DE_ASSERT   0b1
 
#define THS0_BGR_REG_THS0_GATING_OFFSET   0
 
#define THS0_BGR_REG_THS0_GATING_CLEAR_MASK   (0x00000001)
 
#define THS0_BGR_REG_THS0_GATING_MASK   0b0
 
#define THS0_BGR_REG_THS0_GATING_PASS   0b1
 
#define IRRX_CLK_REG   0x00001000
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET   31
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K   0b000
 
#define IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b001
 
#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define IRRX_CLK_REG_FACTOR_M_OFFSET   0
 
#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define IRRX_BGR_REG   0x00001004
 
#define IRRX_BGR_REG_IRRX_RST_OFFSET   16
 
#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK   (0x00010000)
 
#define IRRX_BGR_REG_IRRX_RST_ASSERT   0b0
 
#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT   0b1
 
#define IRRX_BGR_REG_IRRX_GATING_OFFSET   0
 
#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK   (0x00000001)
 
#define IRRX_BGR_REG_IRRX_GATING_MASK   0b0
 
#define IRRX_BGR_REG_IRRX_GATING_PASS   0b1
 
#define IRTX_CLK_REG   0x00001008
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET   31
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b001
 
#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define IRTX_CLK_REG_FACTOR_M_OFFSET   0
 
#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define IRTX_BGR_REG   0x0000100c
 
#define IRTX_BGR_REG_IRTX_RST_OFFSET   16
 
#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK   (0x00010000)
 
#define IRTX_BGR_REG_IRTX_RST_ASSERT   0b0
 
#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT   0b1
 
#define IRTX_BGR_REG_IRTX_GATING_OFFSET   0
 
#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK   (0x00000001)
 
#define IRTX_BGR_REG_IRTX_GATING_MASK   0b0
 
#define IRTX_BGR_REG_IRTX_GATING_PASS   0b1
 
#define LRADC_BGR_REG   0x00001024
 
#define LRADC_BGR_REG_LRADC_RST_OFFSET   16
 
#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK   (0x00010000)
 
#define LRADC_BGR_REG_LRADC_RST_ASSERT   0b0
 
#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT   0b1
 
#define LRADC_BGR_REG_LRADC_GATING_OFFSET   0
 
#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK   (0x00000001)
 
#define LRADC_BGR_REG_LRADC_GATING_MASK   0b0
 
#define LRADC_BGR_REG_LRADC_GATING_PASS   0b1
 
#define SGPIO_CLK_REG   0x00001060
 
#define SGPIO_CLK_REG_SGPIO_CLK_GATING_OFFSET   31
 
#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SGPIO_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SGPIO_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SGPIO_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SGPIO_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define SGPIO_CLK_REG_FACTOR_M_OFFSET   0
 
#define SGPIO_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SGPIO_BGR_REG   0x00001064
 
#define SGPIO_BGR_REG_SGPIO_RST_OFFSET   16
 
#define SGPIO_BGR_REG_SGPIO_RST_CLEAR_MASK   (0x00010000)
 
#define SGPIO_BGR_REG_SGPIO_RST_ASSERT   0b0
 
#define SGPIO_BGR_REG_SGPIO_RST_DE_ASSERT   0b1
 
#define SGPIO_BGR_REG_SGPIO_GATING_OFFSET   0
 
#define SGPIO_BGR_REG_SGPIO_GATING_CLEAR_MASK   (0x00000001)
 
#define SGPIO_BGR_REG_SGPIO_GATING_MASK   0b0
 
#define SGPIO_BGR_REG_SGPIO_GATING_PASS   0b1
 
#define LPC_CLK_REG   0x00001080
 
#define LPC_CLK_REG_LPC_CLK_GATING_OFFSET   31
 
#define LPC_CLK_REG_LPC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define LPC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define LPC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b000
 
#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b001
 
#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b010
 
#define LPC_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011
 
#define LPC_CLK_REG_FACTOR_M_OFFSET   0
 
#define LPC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define LPC_BGR_REG   0x00001084
 
#define LPC_BGR_REG_LPC_RST_OFFSET   16
 
#define LPC_BGR_REG_LPC_RST_CLEAR_MASK   (0x00010000)
 
#define LPC_BGR_REG_LPC_RST_ASSERT   0b0
 
#define LPC_BGR_REG_LPC_RST_DE_ASSERT   0b1
 
#define LPC_BGR_REG_LPC_GATING_OFFSET   0
 
#define LPC_BGR_REG_LPC_GATING_CLEAR_MASK   (0x00000001)
 
#define LPC_BGR_REG_LPC_GATING_MASK   0b0
 
#define LPC_BGR_REG_LPC_GATING_PASS   0b1
 
#define I2SPCM0_CLK_REG   0x00001200
 
#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_OFFSET   31
 
#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM0_BGR_REG   0x0000120c
 
#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET   16
 
#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK   (0x00010000)
 
#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT   0b0
 
#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT   0b1
 
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET   0
 
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK   (0x00000001)
 
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK   0b0
 
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS   0b1
 
#define I2SPCM1_CLK_REG   0x00001210
 
#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET   31
 
#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM1_BGR_REG   0x0000121c
 
#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET   16
 
#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK   (0x00010000)
 
#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT   0b0
 
#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT   0b1
 
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET   0
 
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK   (0x00000001)
 
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK   0b0
 
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS   0b1
 
#define I2SPCM2_CLK_REG   0x00001220
 
#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET   31
 
#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM2_ASRC_CLK_REG   0x00001224
 
#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET   31
 
#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011
 
#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100
 
#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM2_BGR_REG   0x0000122c
 
#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET   16
 
#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK   (0x00010000)
 
#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT   0b0
 
#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT   0b1
 
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET   0
 
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK   (0x00000001)
 
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK   0b0
 
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS   0b1
 
#define I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT   0x2
 
#define I2SPCM3_CLK_REG   0x00001230
 
#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET   31
 
#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM3_BGR_REG   0x0000123c
 
#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET   16
 
#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK   (0x00010000)
 
#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT   0b0
 
#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT   0b1
 
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET   0
 
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK   (0x00000001)
 
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK   0b0
 
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS   0b1
 
#define I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT   0x3
 
#define I2SPCM4_CLK_REG   0x00001240
 
#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET   31
 
#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011
 
#define I2SPCM4_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define I2SPCM4_BGR_REG   0x0000124c
 
#define I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET   16
 
#define I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK   (0x00010000)
 
#define I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT   0b0
 
#define I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT   0b1
 
#define I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET   0
 
#define I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK   (0x00000001)
 
#define I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK   0b0
 
#define I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS   0b1
 
#define I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT   0x4
 
#define SPDIF_TX_CLK_REG   0x00001280
 
#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET   31
 
#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define SPDIF_TX_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPDIF_RX_CLK_REG   0x00001284
 
#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET   31
 
#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b000
 
#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010
 
#define SPDIF_RX_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SPDIF_BGR_REG   0x0000128c
 
#define SPDIF_BGR_REG_SPDIF_RST_OFFSET   16
 
#define SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK   (0x00010000)
 
#define SPDIF_BGR_REG_SPDIF_RST_ASSERT   0b0
 
#define SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT   0b1
 
#define SPDIF_BGR_REG_SPDIF_GATING_OFFSET   0
 
#define SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK   (0x00000001)
 
#define SPDIF_BGR_REG_SPDIF_GATING_MASK   0b0
 
#define SPDIF_BGR_REG_SPDIF_GATING_PASS   0b1
 
#define DMIC_CLK_REG   0x000012c0
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET   31
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001
 
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010
 
#define DMIC_CLK_REG_FACTOR_M_OFFSET   0
 
#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define DMIC_BGR_REG   0x000012cc
 
#define DMIC_BGR_REG_DMIC_RST_OFFSET   16
 
#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK   (0x00010000)
 
#define DMIC_BGR_REG_DMIC_RST_ASSERT   0b0
 
#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT   0b1
 
#define DMIC_BGR_REG_DMIC_GATING_OFFSET   0
 
#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK   (0x00000001)
 
#define DMIC_BGR_REG_DMIC_GATING_MASK   0b0
 
#define DMIC_BGR_REG_DMIC_GATING_PASS   0b1
 
#define USB0_CLK_REG   0x00001300
 
#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31
 
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   (0x80000000)
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1
 
#define USB0_CLK_REG_USB0_PHY_RSTN_OFFSET   30
 
#define USB0_CLK_REG_USB0_PHY_RSTN_CLEAR_MASK   (0x40000000)
 
#define USB0_CLK_REG_USB0_PHY_RSTN_ASSERT   0b0
 
#define USB0_CLK_REG_USB0_PHY_RSTN_DE_ASSERT   0b1
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   (0x03000000)
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b000
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M   0b001
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K   0b010
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC   0b011
 
#define USB0_BGR_REG   0x00001304
 
#define USB0_BGR_REG_USB0_DEVICE_RST_OFFSET   24
 
#define USB0_BGR_REG_USB0_DEVICE_RST_CLEAR_MASK   (0x01000000)
 
#define USB0_BGR_REG_USB0_DEVICE_RST_ASSERT   0b0
 
#define USB0_BGR_REG_USB0_DEVICE_RST_DE_ASSERT   0b1
 
#define USB0_BGR_REG_USB0_EHCI_RST_OFFSET   20
 
#define USB0_BGR_REG_USB0_EHCI_RST_CLEAR_MASK   (0x00100000)
 
#define USB0_BGR_REG_USB0_EHCI_RST_ASSERT   0b0
 
#define USB0_BGR_REG_USB0_EHCI_RST_DE_ASSERT   0b1
 
#define USB0_BGR_REG_USB0_OHCI_RST_OFFSET   16
 
#define USB0_BGR_REG_USB0_OHCI_RST_CLEAR_MASK   (0x00010000)
 
#define USB0_BGR_REG_USB0_OHCI_RST_ASSERT   0b0
 
#define USB0_BGR_REG_USB0_OHCI_RST_DE_ASSERT   0b1
 
#define USB0_BGR_REG_USB0_DEVICE_GATING_OFFSET   8
 
#define USB0_BGR_REG_USB0_DEVICE_GATING_CLEAR_MASK   (0x00000100)
 
#define USB0_BGR_REG_USB0_DEVICE_GATING_MASK   0b0
 
#define USB0_BGR_REG_USB0_DEVICE_GATING_PASS   0b1
 
#define USB0_BGR_REG_USB0_EHCI_GATING_OFFSET   4
 
#define USB0_BGR_REG_USB0_EHCI_GATING_CLEAR_MASK   (0x00000010)
 
#define USB0_BGR_REG_USB0_EHCI_GATING_MASK   0b0
 
#define USB0_BGR_REG_USB0_EHCI_GATING_PASS   0b1
 
#define USB0_BGR_REG_USB0_OHCI_GATING_OFFSET   0
 
#define USB0_BGR_REG_USB0_OHCI_GATING_CLEAR_MASK   (0x00000001)
 
#define USB0_BGR_REG_USB0_OHCI_GATING_MASK   0b0
 
#define USB0_BGR_REG_USB0_OHCI_GATING_PASS   0b1
 
#define USB1_CLK_REG   0x00001308
 
#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31
 
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   (0x80000000)
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0b0
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0b1
 
#define USB1_CLK_REG_USB1_PHY_RSTN_OFFSET   30
 
#define USB1_CLK_REG_USB1_PHY_RSTN_CLEAR_MASK   (0x40000000)
 
#define USB1_CLK_REG_USB1_PHY_RSTN_ASSERT   0b0
 
#define USB1_CLK_REG_USB1_PHY_RSTN_DE_ASSERT   0b1
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   (0x03000000)
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b000
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M   0b001
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K   0b010
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC   0b011
 
#define USB1_BGR_REG   0x0000130c
 
#define USB1_BGR_REG_USB1_EHCI_RST_OFFSET   20
 
#define USB1_BGR_REG_USB1_EHCI_RST_CLEAR_MASK   (0x00100000)
 
#define USB1_BGR_REG_USB1_EHCI_RST_ASSERT   0b0
 
#define USB1_BGR_REG_USB1_EHCI_RST_DE_ASSERT   0b1
 
#define USB1_BGR_REG_USB1_OHCI_RST_OFFSET   16
 
#define USB1_BGR_REG_USB1_OHCI_RST_CLEAR_MASK   (0x00010000)
 
#define USB1_BGR_REG_USB1_OHCI_RST_ASSERT   0b0
 
#define USB1_BGR_REG_USB1_OHCI_RST_DE_ASSERT   0b1
 
#define USB1_BGR_REG_USB1_EHCI_GATING_OFFSET   4
 
#define USB1_BGR_REG_USB1_EHCI_GATING_CLEAR_MASK   (0x00000010)
 
#define USB1_BGR_REG_USB1_EHCI_GATING_MASK   0b0
 
#define USB1_BGR_REG_USB1_EHCI_GATING_PASS   0b1
 
#define USB1_BGR_REG_USB1_OHCI_GATING_OFFSET   0
 
#define USB1_BGR_REG_USB1_OHCI_GATING_CLEAR_MASK   (0x00000001)
 
#define USB1_BGR_REG_USB1_OHCI_GATING_MASK   0b0
 
#define USB1_BGR_REG_USB1_OHCI_GATING_PASS   0b1
 
#define USB0_USB1_REF_CLK_REG   0x00001340
 
#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_OFFSET   31
 
#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define USB2_U2_REF_CLK_REG   0x00001348
 
#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_OFFSET   31
 
#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define USB2_SUSPEND_CLK_REG   0x00001350
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x01000000)
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K   0b0
 
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b1
 
#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define USB2_MF_CLK_REG   0x00001354
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET   31
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define USB2_MF_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define USB2_BGR_REG   0x0000135c
 
#define USB2_BGR_REG_USB2_RST_OFFSET   16
 
#define USB2_BGR_REG_USB2_RST_CLEAR_MASK   (0x00010000)
 
#define USB2_BGR_REG_USB2_RST_ASSERT   0b0
 
#define USB2_BGR_REG_USB2_RST_DE_ASSERT   0b1
 
#define USB2_U3_UTMI_CLK_REG   0x00001360
 
#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_OFFSET   31
 
#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001
 
#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define USB2_U3_UTMI_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_U3_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define USB2_U2_PIPE_CLK_REG   0x00001364
 
#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_OFFSET   31
 
#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define USB2_U2_PIPE_CLK_REG_FACTOR_M_OFFSET   0
 
#define USB2_U2_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define PCIE0_AUX_CLK_REG   0x00001380
 
#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET   31
 
#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x01000000)
 
#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b0
 
#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K   0b1
 
#define PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET   0
 
#define PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define PCIE0_AXI_SLV_CLK_REG   0x00001384
 
#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_OFFSET   31
 
#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000
 
#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010
 
#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_OFFSET   0
 
#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define PCIE0_BGR_REG   0x0000138c
 
#define PCIE0_BGR_REG_PCIE0_RST_OFFSET   17
 
#define PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK   (0x00020000)
 
#define PCIE0_BGR_REG_PCIE0_RST_ASSERT   0b0
 
#define PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT   0b1
 
#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET   16
 
#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK   (0x00010000)
 
#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT   0b0
 
#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT   0b1
 
#define SERDES_PHY_CFG_CLK_REG   0x000013c0
 
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET   31
 
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b001
 
#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET   0
 
#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define SERDES_BGR_REG   0x000013c4
 
#define SERDES_BGR_REG_SERDES_RST_OFFSET   16
 
#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK   (0x00010000)
 
#define SERDES_BGR_REG_SERDES_RST_ASSERT   0b0
 
#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT   0b1
 
#define GMAC_PTP_CLK_REG   0x00001400
 
#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET   31
 
#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define GMAC_PTP_CLK_REG_FACTOR_M_OFFSET   0
 
#define GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define GMAC0_PHY_CLK_REG   0x00001410
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET   31
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET   0
 
#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define GMAC0_BGR_REG   0x0000141c
 
#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET   17
 
#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK   (0x00020000)
 
#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT   0b0
 
#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT   0b1
 
#define GMAC0_BGR_REG_GMAC0_RST_OFFSET   16
 
#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK   (0x00010000)
 
#define GMAC0_BGR_REG_GMAC0_RST_ASSERT   0b0
 
#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT   0b1
 
#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET   0
 
#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK   (0x00000001)
 
#define GMAC0_BGR_REG_GMAC0_GATING_MASK   0b0
 
#define GMAC0_BGR_REG_GMAC0_GATING_PASS   0b1
 
#define GMAC1_PHY_CLK_REG   0x00001420
 
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET   31
 
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET   0
 
#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define GMAC1_BGR_REG   0x0000142c
 
#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET   17
 
#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK   (0x00020000)
 
#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT   0b0
 
#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT   0b1
 
#define GMAC1_BGR_REG_GMAC1_RST_OFFSET   16
 
#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK   (0x00010000)
 
#define GMAC1_BGR_REG_GMAC1_RST_ASSERT   0b0
 
#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT   0b1
 
#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET   0
 
#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK   (0x00000001)
 
#define GMAC1_BGR_REG_GMAC1_GATING_MASK   0b0
 
#define GMAC1_BGR_REG_GMAC1_GATING_PASS   0b1
 
#define VO0_TCONLCD0_CLK_REG   0x00001500
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET   31
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VO0_TCONLCD0_BGR_REG   0x00001504
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET   16
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK   (0x00010000)
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT   0b0
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT   0b1
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET   0
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK   (0x00000001)
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK   0b0
 
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS   0b1
 
#define VO0_TCONLCD1_CLK_REG   0x00001508
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET   31
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VO0_TCONLCD1_BGR_REG   0x0000150c
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET   16
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK   (0x00010000)
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT   0b0
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT   0b1
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET   0
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK   (0x00000001)
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK   0b0
 
#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS   0b1
 
#define VO0_TCONLCD2_CLK_REG   0x00001510
 
#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET   31
 
#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VO0_TCONLCD2_BGR_REG   0x00001514
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET   16
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK   (0x00010000)
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT   0b0
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT   0b1
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET   0
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK   (0x00000001)
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK   0b0
 
#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS   0b1
 
#define LVDS0_BGR_REG   0x00001544
 
#define LVDS0_BGR_REG_LVDS0_RST_OFFSET   16
 
#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK   (0x00010000)
 
#define LVDS0_BGR_REG_LVDS0_RST_ASSERT   0b0
 
#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT   0b1
 
#define LVDS1_BGR_REG   0x0000154c
 
#define LVDS1_BGR_REG_LVDS1_RST_OFFSET   16
 
#define LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK   (0x00010000)
 
#define LVDS1_BGR_REG_LVDS1_RST_ASSERT   0b0
 
#define LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT   0b1
 
#define DSI0_CLK_REG   0x00001580
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET   31
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define DSI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010
 
#define DSI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define DSI0_BGR_REG   0x00001584
 
#define DSI0_BGR_REG_DSI0_RST_OFFSET   16
 
#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK   (0x00010000)
 
#define DSI0_BGR_REG_DSI0_RST_ASSERT   0b0
 
#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT   0b1
 
#define DSI0_BGR_REG_DSI0_GATING_OFFSET   0
 
#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK   (0x00000001)
 
#define DSI0_BGR_REG_DSI0_GATING_MASK   0b0
 
#define DSI0_BGR_REG_DSI0_GATING_PASS   0b1
 
#define DSI1_CLK_REG   0x00001588
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET   31
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define DSI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001
 
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010
 
#define DSI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define DSI1_BGR_REG   0x0000158c
 
#define DSI1_BGR_REG_DSI1_RST_OFFSET   16
 
#define DSI1_BGR_REG_DSI1_RST_CLEAR_MASK   (0x00010000)
 
#define DSI1_BGR_REG_DSI1_RST_ASSERT   0b0
 
#define DSI1_BGR_REG_DSI1_RST_DE_ASSERT   0b1
 
#define DSI1_BGR_REG_DSI1_GATING_OFFSET   0
 
#define DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK   (0x00000001)
 
#define DSI1_BGR_REG_DSI1_GATING_MASK   0b0
 
#define DSI1_BGR_REG_DSI1_GATING_PASS   0b1
 
#define COMBPHY0_CLK_REG   0x000015c0
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET   31
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100
 
#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET   0
 
#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define COMBPHY1_CLK_REG   0x000015c4
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET   31
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100
 
#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET   0
 
#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define TCONTV0_BGR_REG   0x00001604
 
#define TCONTV0_BGR_REG_TCONTV0_RST_OFFSET   16
 
#define TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK   (0x00010000)
 
#define TCONTV0_BGR_REG_TCONTV0_RST_ASSERT   0b0
 
#define TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT   0b1
 
#define TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET   0
 
#define TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK   (0x00000001)
 
#define TCONTV0_BGR_REG_TCONTV0_GATING_MASK   0b0
 
#define TCONTV0_BGR_REG_TCONTV0_GATING_PASS   0b1
 
#define TCONTV1_BGR_REG   0x0000160c
 
#define TCONTV1_BGR_REG_TCONTV1_RST_OFFSET   16
 
#define TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK   (0x00010000)
 
#define TCONTV1_BGR_REG_TCONTV1_RST_ASSERT   0b0
 
#define TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT   0b1
 
#define TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET   0
 
#define TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK   (0x00000001)
 
#define TCONTV1_BGR_REG_TCONTV1_GATING_MASK   0b0
 
#define TCONTV1_BGR_REG_TCONTV1_GATING_PASS   0b1
 
#define EDP_TV_CLK_REG   0x00001640
 
#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_OFFSET   31
 
#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_ON   0b1
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define EDP_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define EDP_TV_CLK_REG_FACTOR_N_OFFSET   8
 
#define EDP_TV_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define EDP_TV_CLK_REG_FACTOR_M_OFFSET   0
 
#define EDP_TV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define EDP_BGR_REG   0x0000164c
 
#define EDP_BGR_REG_EDP_RST_OFFSET   16
 
#define EDP_BGR_REG_EDP_RST_CLEAR_MASK   (0x00010000)
 
#define EDP_BGR_REG_EDP_RST_ASSERT   0b0
 
#define EDP_BGR_REG_EDP_RST_DE_ASSERT   0b1
 
#define EDP_BGR_REG_EDP_GATING_OFFSET   0
 
#define EDP_BGR_REG_EDP_GATING_CLEAR_MASK   (0x00000001)
 
#define EDP_BGR_REG_EDP_GATING_MASK   0b0
 
#define EDP_BGR_REG_EDP_GATING_PASS   0b1
 
#define HDMI_CEC_CLK_REG   0x00001680
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET   31
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET   30
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK   (0x40000000)
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF   0b0
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON   0b1
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K   0b000
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K_PERI0PLL2X_36621_32_768KHZ   0b001
 
#define HDMI_TV_CLK_REG   0x00001684
 
#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_OFFSET   31
 
#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010
 
#define HDMI_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011
 
#define HDMI_TV_CLK_REG_FACTOR_N_OFFSET   8
 
#define HDMI_TV_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define HDMI_TV_CLK_REG_FACTOR_M_OFFSET   0
 
#define HDMI_TV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define HDMI_BGR_REG   0x0000168c
 
#define HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET   18
 
#define HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK   (0x00040000)
 
#define HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT   0b0
 
#define HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT   0b1
 
#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET   17
 
#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK   (0x00020000)
 
#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT   0b0
 
#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT   0b1
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET   16
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK   (0x00010000)
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT   0b0
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT   0b1
 
#define HDMI_BGR_REG_HDMI_GATING_OFFSET   0
 
#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK   (0x00000001)
 
#define HDMI_BGR_REG_HDMI_GATING_MASK   0b0
 
#define HDMI_BGR_REG_HDMI_GATING_PASS   0b1
 
#define HDMI_SFR_CLK_REG   0x00001690
 
#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_OFFSET   31
 
#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_ON   0b1
 
#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_HOSC   0b001
 
#define HDCP_ESM_CLK_REG   0x00001694
 
#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_OFFSET   31
 
#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DPSS_TOP0_BGR_REG   0x000016c4
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET   16
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK   (0x00010000)
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT   0b0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT   0b1
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET   0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK   (0x00000001)
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK   0b0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS   0b1
 
#define DPSS_TOP1_BGR_REG   0x000016cc
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET   16
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK   (0x00010000)
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT   0b0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT   0b1
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET   0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK   (0x00000001)
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK   0b0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS   0b1
 
#define VIDEO_OUT0_BGR_REG   0x000016e4
 
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET   16
 
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK   (0x00010000)
 
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT   0b0
 
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT   0b1
 
#define VIDEO_OUT1_BGR_REG   0x000016ec
 
#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET   16
 
#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK   (0x00010000)
 
#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT   0b0
 
#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT   0b1
 
#define LEDC_CLK_REG   0x00001700
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b001
 
#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC   0b010
 
#define LEDC_CLK_REG_FACTOR_M_OFFSET   0
 
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define LEDC_BGR_REG   0x00001704
 
#define LEDC_BGR_REG_LEDC_RST_OFFSET   16
 
#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK   (0x00010000)
 
#define LEDC_BGR_REG_LEDC_RST_ASSERT   0b0
 
#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT   0b1
 
#define LEDC_BGR_REG_LEDC_GATING_OFFSET   0
 
#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK   (0x00000001)
 
#define LEDC_BGR_REG_LEDC_GATING_MASK   0b0
 
#define LEDC_BGR_REG_LEDC_GATING_PASS   0b1
 
#define DSC_BGR_REG   0x00001744
 
#define DSC_BGR_REG_DSC_RST_OFFSET   16
 
#define DSC_BGR_REG_DSC_RST_CLEAR_MASK   (0x00010000)
 
#define DSC_BGR_REG_DSC_RST_ASSERT   0b0
 
#define DSC_BGR_REG_DSC_RST_DE_ASSERT   0b1
 
#define DSC_BGR_REG_DSC_GATING_OFFSET   0
 
#define DSC_BGR_REG_DSC_GATING_CLEAR_MASK   (0x00000001)
 
#define DSC_BGR_REG_DSC_GATING_MASK   0b0
 
#define DSC_BGR_REG_DSC_GATING_PASS   0b1
 
#define CSI_MASTER0_CLK_REG   0x00001800
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CSI_MASTER1_CLK_REG   0x00001804
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CSI_MASTER2_CLK_REG   0x00001808
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CSI_CLK_REG   0x00001840
 
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000
 
#define CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X   0b001
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b100
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110
 
#define CSI_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define CSI_BGR_REG   0x00001844
 
#define CSI_BGR_REG_CSI_RST_OFFSET   16
 
#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   (0x00010000)
 
#define CSI_BGR_REG_CSI_RST_ASSERT   0b0
 
#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0b1
 
#define CSI_BGR_REG_CSI_GATING_OFFSET   0
 
#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   (0x00000001)
 
#define CSI_BGR_REG_CSI_GATING_MASK   0b0
 
#define CSI_BGR_REG_CSI_GATING_PASS   0b1
 
#define ISP_CLK_REG   0x00001860
 
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0b1
 
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b100
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b101
 
#define ISP_CLK_REG_FACTOR_M_OFFSET   0
 
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define VIDEO_IN_BGR_REG   0x00001884
 
#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET   16
 
#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK   (0x00010000)
 
#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT   0b0
 
#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT   0b1
 
#define DDRPLL_GATE_EN_REG   0x00001904
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET   16
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE   0b0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE   0b1
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET   0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO   0b0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG   0x00001908
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET   31
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK   (0x80000000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   (0x08000000)
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   (0x04000000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   (0x02000000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   (0x01000000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   (0x00800000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   (0x00400000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   (0x00200000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   (0x00100000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   (0x00080000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   (0x00040000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   (0x00000800)
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   (0x00000400)
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   (0x00000200)
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000100)
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   (0x00000080)
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000020)
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   (0x00000008)
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000004)
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG   0x0000190c
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET   31
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK   (0x80000000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET   27
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK   (0x08000000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET   26
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK   (0x04000000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET   25
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK   (0x02000000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK   (0x01000000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET   23
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK   (0x00800000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET   22
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK   (0x00400000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK   (0x00200000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET   20
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK   (0x00100000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET   19
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK   (0x00080000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK   (0x00040000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET   17
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET   16
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET   11
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK   (0x00000800)
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET   10
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000400)
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK   (0x00000200)
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000100)
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK   (0x00000080)
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000020)
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK   (0x00000008)
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000004)
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO   0b0
 
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG   0x00001910
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET   22
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00400000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET   21
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00200000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET   20
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00100000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET   18
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00040000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET   17
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET   16
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET   6
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET   5
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000020)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET   4
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET   2
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000004)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET   1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET   0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define GPUPLL_GATE_EN_REG   0x00001914
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET   16
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE   0b0
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE   0b1
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET   0
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO   0b0
 
#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VEPLL_GATE_EN_REG   0x00001918
 
#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET   17
 
#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE   0b0
 
#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE   0b1
 
#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET   16
 
#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE   0b0
 
#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE   0b1
 
#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET   1
 
#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO   0b0
 
#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET   0
 
#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO   0b0
 
#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG   0x0000191c
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_OFFSET   18
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_CLEAR_MASK   (0x00040000)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_OFFSET   17
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET   16
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_OFFSET   2
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_CLEAR_MASK   (0x00000004)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_OFFSET   1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET   0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define NPUPLL_GATE_EN_REG   0x00001920
 
#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET   16
 
#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET   0
 
#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define DEPLL_GATE_EN_REG   0x00001928
 
#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET   17
 
#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00020000)
 
#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE   0b0
 
#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE   0b1
 
#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET   16
 
#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)
 
#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET   1
 
#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)
 
#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO   0b0
 
#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET   0
 
#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)
 
#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define DDRPLL_GATE_STAT_REG   0x00001984
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET   16
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE   0b0
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG   0x00001988
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET   27
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK   (0x08000000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET   26
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK   (0x04000000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET   25
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK   (0x02000000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET   24
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK   (0x01000000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET   23
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK   (0x00800000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET   22
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK   (0x00400000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET   21
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK   (0x00200000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET   20
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK   (0x00100000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET   19
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK   (0x00080000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET   18
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK   (0x00040000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET   17
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE   0b1
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET   16
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE   0b0
 
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG   0x0000198c
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET   27
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK   (0x08000000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET   26
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK   (0x04000000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET   25
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK   (0x02000000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET   24
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK   (0x01000000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET   23
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK   (0x00800000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET   22
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK   (0x00400000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET   21
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK   (0x00200000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET   20
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK   (0x00100000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET   19
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK   (0x00080000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET   18
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK   (0x00040000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET   17
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE   0b1
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET   16
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE   0b0
 
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG   0x00001990
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET   22
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK   (0x00400000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET   21
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK   (0x00200000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET   20
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK   (0x00100000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET   18
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK   (0x00040000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET   17
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET   16
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE   0b1
 
#define GPUPLL_GATE_STAT_REG   0x00001994
 
#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET   16
 
#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE   0b0
 
#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE   0b1
 
#define VEPLL_GATE_STAT_REG   0x00001998
 
#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET   17
 
#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE   0b0
 
#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE   0b1
 
#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET   16
 
#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE   0b0
 
#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG   0x0000199c
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_OFFSET   18
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_CLEAR_MASK   (0x00040000)
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_OFFSET   17
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET   16
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE   0b1
 
#define NPUPLL_GATE_STAT_REG   0x000019a0
 
#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET   16
 
#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE   0b0
 
#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE   0b1
 
#define DEPLL_GATE_STAT_REG   0x000019a8
 
#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET   17
 
#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK   (0x00020000)
 
#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE   0b0
 
#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE   0b1
 
#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET   16
 
#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)
 
#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE   0b0
 
#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE   0b1
 
#define CLK24M_GATE_EN_REG   0x00001a00
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   (0x00000008)
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0b0
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0b1
 
#define CM_VI_CFG_REG   0x00001b00
 
#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET   16
 
#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF   0b01
 
#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON   0b10
 
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET   0
 
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE   0b0
 
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE   0b1
 
#define CM_DESYS_CFG_REG   0x00001b04
 
#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET   16
 
#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF   0b01
 
#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON   0b10
 
#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET   0
 
#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE   0b0
 
#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE   0b1
 
#define CM_VE_DEC_CFG_REG   0x00001b10
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET   16
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF   0b01
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON   0b10
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET   0
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE   0b0
 
#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE   0b1
 
#define CM_VE_ENC_CFG_REG   0x00001b14
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET   16
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF   0b01
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON   0b10
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET   0
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE   0b0
 
#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE   0b1
 
#define CM_NPU_CFG_REG   0x00001b1c
 
#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET   16
 
#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF   0b01
 
#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON   0b10
 
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET   0
 
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE   0b0
 
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE   0b1
 
#define CM_GPU0_CFG_REG   0x00001b24
 
#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET   16
 
#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF   0b01
 
#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON   0b10
 
#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET   0
 
#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE   0b0
 
#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE   0b1
 
#define CM_PCIE0_CFG_REG   0x00001b28
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET   16
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF   0b01
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON   0b10
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET   0
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE   0b0
 
#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE   0b1
 
#define CM_USB2_CFG_REG   0x00001b30
 
#define CM_USB2_CFG_REG_CM_USB2_STATUS_OFFSET   16
 
#define CM_USB2_CFG_REG_CM_USB2_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_OFF   0b01
 
#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_ON   0b10
 
#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_OFFSET   0
 
#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_DISABLE   0b0
 
#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_ENABLE   0b1
 
#define CM_VO_CFG_REG   0x00001b34
 
#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET   16
 
#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF   0b01
 
#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON   0b10
 
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET   0
 
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE   0b0
 
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE   0b1
 
#define CM_VO1_CFG_REG   0x00001b38
 
#define CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET   16
 
#define CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK   (0x00030000)
 
#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF   0b01
 
#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON   0b10
 
#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET   0
 
#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK   (0x00000001)
 
#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE   0b0
 
#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE   0b1
 
#define APB2JTAG_CLK_REG   0x00001c00
 
#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_OFFSET   31
 
#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLEAR_MASK   (0x80000000)
 
#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_ON   0b1
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b101
 
#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110
 
#define APB2JTAG_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB2JTAG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)
 
#define APB2JTAG_BGR_REG   0x00001c04
 
#define APB2JTAG_BGR_REG_APB2JTAG_RST_OFFSET   16
 
#define APB2JTAG_BGR_REG_APB2JTAG_RST_CLEAR_MASK   (0x00010000)
 
#define APB2JTAG_BGR_REG_APB2JTAG_RST_ASSERT   0b0
 
#define APB2JTAG_BGR_REG_APB2JTAG_RST_DE_ASSERT   0b1
 
#define CCU_SEC_SWITCH_REG   0x00001f00
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   (0x00000004)
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   (0x00000002)
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   (0x00000001)
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1
 
#define SYSDAP_REQ_CTRL_REG   0x00001f10
 
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET   0
 
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK   (0x00000001)
 
#define PLL_CFG0_REG   0x00001f20
 
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0
 
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   (0xffffffff)
 
#define PLL_CFG1_REG   0x00001f24
 
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0
 
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   (0xffffffff)
 
#define PLL_CFG2_REG   0x00001f28
 
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0
 
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   (0xffffffff)
 
#define PLL_LOCK_DBG_CTRL_REG   0x00001f2c
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   (0x80000000)
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0b0
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0b1
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   (0x07f00000)
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL   0b0000000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL   0b0000001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL   0b0000010
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL   0b0000011
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL   0b0000100
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL   0b0000101
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL   0b0000110
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL   0b0000111
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL   0b0001001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL   0b0001010
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL   0b0001011
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL   0b0001100
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL   0b0001101
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL   0b0100000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL   0b1000000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL   0b1000001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL   0b1000010
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL   0b1000011
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL0   0b1100000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL1   0b1100001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_HDMIPLL   0b1110000
 
#define CCU_FAN_GATE_REG   0x00001f30
 
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   (0x00000008)
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   (0x00000004)
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   (0x00000002)
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   (0x00000001)
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG   0x00001f34
 
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31
 
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   (0x80000000)
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   (0x03000000)
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X   0b000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X   0b001
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X   0b010
 
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8
 
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   (0x00001f00)
 
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0
 
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   (0x0000001f)
 
#define CLK_FAN_REG   0x00001f38
 
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   (0x80000000)
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1
 
#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5
 
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   (0x000003e0)
 
#define CLK_FAN_REG_PCLK_DIV_OFFSET   0
 
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   (0x0000001f)
 
#define CCU_FAN_REG   0x00001f3c
 
#define CCU_FAN_REG_CLK_FANOUT3_EN_OFFSET   24
 
#define CCU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK   (0x01000000)
 
#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   (0x00800000)
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   (0x00400000)
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   (0x00200000)
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_OFFSET   9
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK   (0x00000e00)
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M   0b011
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT3_SEL_PCLK   0b110
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   (0x000001c0)
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M   0b011
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0b110
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   (0x00000038)
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M   0b011
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0b110
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   (0x00000007)
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M   0b011
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0b110
 
#define BUS_CLK_DBG_REG   0x00001f50
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET   0
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK   (0x00000007)
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK   0b000
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK   0b001
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK   0b010
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK   0b011
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK   0b100
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK   0b101
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR0_CLK   0b110
 
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_HDR0_CLK   0b111
 
#define CCU_VERSION_REG   0x00001ff0
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   (0xffff0000)
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   (0x0000ffff)
 
#define PLL_CPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define APB2_CLK_RATE_N_1   (0x0 << 8)
 
#define APB2_CLK_RATE_N_2   (0x1 << 8)
 
#define APB2_CLK_RATE_N_4   (0x2 << 8)
 
#define APB2_CLK_RATE_N_8   (0x3 << 8)
 
#define APB2_CLK_RATE_N_MASK   (3 << 8)
 
#define APB2_CLK_RATE_M(m)   (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define SUNXI_MEMC_CLK_RST   (SUNXI_MEMC_COMMON_BASE + 0x10)
 
#define MEMC_REG_PLLREF_CLK_EN   (1U << 13)
 
#define MEMC_REG_HDR_CLK1_EN   (1U << 10)
 
#define MEMC_REG_HDR_CLK0_EN   (1U << 9)
 
#define MEMC_REG_HCLK1_EN   (1U << 8)
 
#define CCU_MMC_CTRL_M(x)   (x)
 
#define CCU_MMC_CTRL_N(x)   ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
 
#define CCU_MMC_CTRL_OSCM24   (SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PLL6X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PLL_PERIPH2X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI0_400M_freq   (400000000)
 
#define CCU_MMC_CTRL_PERI0_300M_freq   (300000000)
 
#define CCU_MMC_CTRL_PERI0_800M_freq   (800000000)
 
#define CCU_MMC_CTRL_PERI0_600M_freq   (600000000)
 
#define CCU_MMC_CTRL_PERI0_400M   (0x1 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI0_300M   (0x2 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI0_800M   (0x1 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI0_600M   (0x2 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI1_400M   (0x3 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI1_300M   (0x4 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI1_800M   (0x3 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PERI1_600M   (0x4 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_ENABLE   (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
 
#define CCU_MMC_CTRL_OCLK_DLY(a)   ((void) (a), 0)
 
#define CCU_MMC_CTRL_SCLK_DLY(a)   ((void) (a), 0)
 
#define RESET_SHIFT   (16)
 
#define GATING_SHIFT   (0)
 
#define CE_CLK_SRC_MASK   (0x7)
 
#define CE_CLK_SRC_SEL_BIT   (CE_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CE_CLK_SRC   (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)
 
#define CE_CLK_DIV_RATION_N_BIT   (8)
 
#define CE_CLK_DIV_RATION_N_MASK   (0x3)
 
#define CE_CLK_DIV_RATION_N   (0)
 
#define CE_CLK_DIV_RATION_M_BIT   (CE_CLK_REG_FACTOR_M_OFFSET)
 
#define CE_CLK_DIV_RATION_M_MASK   (CE_CLK_REG_FACTOR_M_CLEAR_MASK)
 
#define CE_CLK_DIV_RATION_M   (0)
 
#define CE_SCLK_ONOFF_BIT   (CE_CLK_REG_CE_CLK_GATING_OFFSET)
 
#define CE_SCLK_ON   (CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF)
 
#define CE_GATING_PASS   (CE_BGR_REG_CE_GATING_MASK)
 
#define CE_GATING_BIT   (CE_BGR_REG_CE_GATING_OFFSET)
 
#define CE_RST_BIT   (CE_BGR_REG_CE_RST_OFFSET)
 
#define CE_DEASSERT   (CE_BGR_REG_CE_SYS_RST_ASSERT)
 
#define CE_SYS_RST_BIT   (CE_BGR_REG_CE_SYS_RST_OFFSET)
 
#define CE_SYS_GATING_BIT   (CE_BGR_REG_CE_SYS_GATING_OFFSET)
 
#define CE_MBUS_GATING_MASK   (1)
 
#define CE_MBUS_GATING_BIT   (MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET)
 
#define CE_MBUS_GATING   (1)
 
#define USBEHCI0_RST_BIT   20
 
#define USBEHCI0_GATIING_BIT   4
 
#define USBPHY0_RST_BIT   30
 
#define USBPHY0_SCLK_GATING_BIT   31
 
#define USBEHCI1_RST_BIT   20
 
#define USBEHCI1_GATIING_BIT   4
 
#define USBPHY1_RST_BIT   30
 
#define USBPHY1_SCLK_GATING_BIT   31
 
#define CCU_PLL_CPU_L_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x1000)
 
#define CCU_PLL_CPU_L_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x101c)
 
#define CCU_PLL_CPU_B_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x2000)
 
#define CCU_PLL_CPU_B_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x201c)
 
#define CCU_PLL_CPU_DSU_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x3000)
 
#define CCU_PLL_DSU_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x301c)
 
#define CCU_MBUS_MST_CLK_GATING_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)
 
#define CCU_MBUS_GATE_ENABLE_REG   (SUNXI_CCU_BASE + MBUS_GATE_EN_REG)
 
#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)
 
#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)
 
#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + SMHC2_CLK_REG)
 
#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC0_BGR_REG)
 
#define CCU_NSI_CLK_GREG   (SUNXI_CCU_BASE + NSI_CLK_REG)
 
#define CCU_NSI_BGR_REG   (SUNXI_CCU_BASE + NSI_BGR_REG)
 
#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG)
 
#define CCU_PLL_PERI1_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI1_CTRL_REG)
 
#define CCU_UART_BGR_REG   (SUNXI_CCU_BASE + UART0_BGR_REG)
 
#define DMA_GATING_BASE   CCU_DMA_BGR_REG
 
#define DMA_GATING_PASS   (1)
 
#define DMA_GATING_BIT   (0)
 
#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC0_BGR_REG)
 
#define CCU_GPADC_24M_REG   (SUNXI_CCU_BASE + GPADC0_24M_CLK_REG)
 
#define CCU_LRADC_BGR_REG   (SUNXI_CCU_BASE + LRADC_BGR_REG)
 
#define RTC_LOSC_CTRL_REG   (SUNXI_RTC_BASE)
 
#define XO_CONTROL0_REG   0x0160
 
#define RTC_XO_CONTROL0_REG   (SUNXI_RTC_BASE + XO_CONTROL0_REG)
 
#define LOSC_CONTROL_KEY_FIFLD   0x16aa0000
 
#define LOSC_AUTO_SWT_32K_SEL_EN_MASK   (0x00004000)
 
#define LOSC_AUTO_SWT_32K_SEL_EN   (1U << 14)
 
#define LOSC_AUTO_SWT_32K_SEL_DISABLE   (0U << 14)
 
#define EXT_LOSC_GSM_HIGH   (0x0000000C)
 
#define LOSC_SRC_SEL_MASK   (0x00000001)
 
#define LOSC_SRC_SEL_32K   (1U << 0)
 
#define LOSC_SRC_SEL_16M   (0U << 0)
 

Macro Definition Documentation

◆ AHB_CLK_REG

#define AHB_CLK_REG   0x00000500

◆ AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK32K

#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ AHB_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define AHB_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00

◆ AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ AHB_CLK_REG_FACTOR_M_OFFSET

#define AHB_CLK_REG_FACTOR_M_OFFSET   0

◆ AHB_MAT_CLK_GATING_REG

#define AHB_MAT_CLK_GATING_REG   0x000005c0

◆ AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_CLEAR_MASK   (0x80000000)

◆ AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_OFFSET

#define AHB_MAT_CLK_GATING_REG_AHB_MONITOR_EN_OFFSET   31

◆ AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   (0x10000000)

◆ AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28

◆ AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000020)

◆ AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_DE_AHB_GATE_SW_CFG_OFFSET   5

◆ AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000080)

◆ AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_GPU0_AHB_GATE_SW_CFG_OFFSET   7

◆ AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_MSILITE0_AHB_GATE_SW_CFG_OFFSET   16

◆ AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000040)

◆ AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_NPU_AHB_GATE_SW_CFG_OFFSET   6

◆ AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_CLEAR_MASK   (0x20000000)

◆ AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_OFFSET

#define AHB_MAT_CLK_GATING_REG_SD_MONITOR_EN_OFFSET   29

◆ AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000100)

◆ AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_SERDES_AHB_GATE_SW_CFG_OFFSET   8

◆ AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_CLEAR_MASK   (0x01000000)

◆ AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_STORE_AHB_GATE_SW_CFG_OFFSET   24

◆ AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000200)

◆ AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_USB0_USB1_SYS_AHB_GATE_SW_CFG_OFFSET   9

◆ AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000001)

◆ AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET   0

◆ AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000002)

◆ AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET   1

◆ AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000004)

◆ AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2

◆ AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000008)

◆ AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_VID_OUT0_AHB_GATE_SW_CFG_OFFSET   3

◆ AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_CLEAR_MASK   (0x00000010)

◆ AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_DISABLE

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_ENABLE

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_OFFSET

#define AHB_MAT_CLK_GATING_REG_VID_OUT1_AHB_GATE_SW_CFG_OFFSET   4

◆ APB0_CLK_REG

#define APB0_CLK_REG   0x00000510

◆ APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ APB0_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ APB0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define APB0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00

◆ APB0_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ APB0_CLK_REG_FACTOR_M_OFFSET

#define APB0_CLK_REG_FACTOR_M_OFFSET   0

◆ APB1_CLK_REG

#define APB1_CLK_REG   0x00000518

◆ APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x03000000)

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ APB1_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b11

◆ APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define APB1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b00

◆ APB1_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ APB1_CLK_REG_FACTOR_M_OFFSET

#define APB1_CLK_REG_FACTOR_M_OFFSET   0

◆ APB2_CLK_RATE_M

#define APB2_CLK_RATE_M (   m)    (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_M_MASK

#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_N_1

#define APB2_CLK_RATE_N_1   (0x0 << 8)

◆ APB2_CLK_RATE_N_2

#define APB2_CLK_RATE_N_2   (0x1 << 8)

◆ APB2_CLK_RATE_N_4

#define APB2_CLK_RATE_N_4   (0x2 << 8)

◆ APB2_CLK_RATE_N_8

#define APB2_CLK_RATE_N_8   (0x3 << 8)

◆ APB2_CLK_RATE_N_MASK

#define APB2_CLK_RATE_N_MASK   (3 << 8)

◆ APB2JTAG_BGR_REG

#define APB2JTAG_BGR_REG   0x00001c04

◆ APB2JTAG_BGR_REG_APB2JTAG_RST_ASSERT

#define APB2JTAG_BGR_REG_APB2JTAG_RST_ASSERT   0b0

◆ APB2JTAG_BGR_REG_APB2JTAG_RST_CLEAR_MASK

#define APB2JTAG_BGR_REG_APB2JTAG_RST_CLEAR_MASK   (0x00010000)

◆ APB2JTAG_BGR_REG_APB2JTAG_RST_DE_ASSERT

#define APB2JTAG_BGR_REG_APB2JTAG_RST_DE_ASSERT   0b1

◆ APB2JTAG_BGR_REG_APB2JTAG_RST_OFFSET

#define APB2JTAG_BGR_REG_APB2JTAG_RST_OFFSET   16

◆ APB2JTAG_CLK_REG

#define APB2JTAG_CLK_REG   0x00001c00

◆ APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLEAR_MASK

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_OFF

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_OFF   0b0

◆ APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_ON

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_CLOCK_IS_ON   0b1

◆ APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_OFFSET

#define APB2JTAG_CLK_REG_APB2JTAG_CLK_GATING_OFFSET   31

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b101

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b110

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b100

◆ APB2JTAG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define APB2JTAG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ APB2JTAG_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB2JTAG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ APB2JTAG_CLK_REG_FACTOR_M_OFFSET

#define APB2JTAG_CLK_REG_FACTOR_M_OFFSET   0

◆ APB_UART_CLK_REG

#define APB_UART_CLK_REG   0x00000538

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS   0b100

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0b011

◆ APB_UART_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define APB_UART_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ APB_UART_CLK_REG_FACTOR_M_OFFSET

#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOPLL_GATE_EN_REG

#define AUDIOPLL_GATE_EN_REG   0x0000191c

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET   0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET   16

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_AUTO_GATE_EN_OFFSET   1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV2_GATE_SW_CFG_OFFSET   17

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_CLEAR_MASK   (0x00000004)

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_AUTO_GATE_EN_OFFSET   2

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_CLEAR_MASK   (0x00040000)

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIO1PLL_DIV5_GATE_SW_CFG_OFFSET   18

◆ AUDIOPLL_GATE_STAT_REG

#define AUDIOPLL_GATE_STAT_REG   0x0000199c

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET   16

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV2_GATE_STAT_OFFSET   17

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_CLEAR_MASK   (0x00040000)

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIO1PLL_DIV5_GATE_STAT_OFFSET   18

◆ AVS_CLK_REG

#define AVS_CLK_REG   0x00000880

◆ AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK

#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0b1

◆ AVS_CLK_REG_AVS_CLK_GATING_OFFSET

#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31

◆ AVS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AVS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ AVS_CLK_REG_CLK_SRC_SEL_HOSC

#define AVS_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ AVS_CLK_REG_CLK_SRC_SEL_OFFSET

#define AVS_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AVS_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define AVS_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ BUS_CLK_DBG_REG

#define BUS_CLK_DBG_REG   0x00001f50

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK   0b000

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK   0b001

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK   0b010

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK   0b011

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK   (0x00000007)

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR0_CLK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR0_CLK   0b110

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_HDR0_CLK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_HDR0_CLK   0b111

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK   0b100

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK   0b101

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET   0

◆ CCU_FAN_GATE_REG

#define CCU_FAN_GATE_REG   0x00001f30

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   (0x00000002)

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK12M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   (0x00000004)

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK16M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   (0x00000001)

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK24M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   (0x00000008)

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK25M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3

◆ CCU_FAN_REG

#define CCU_FAN_REG   0x00001f3c

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   (0x00200000)

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   (0x00000007)

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M   0b011

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0b110

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   (0x00400000)

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   (0x00000038)

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M   0b011

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0b110

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   (0x00800000)

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   (0x000001c0)

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M   0b011

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0b110

◆ CCU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK   (0x01000000)

◆ CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT3_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT3_EN_OFFSET   24

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK   (0x00000e00)

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M   0b011

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT3_SEL_OFFSET   9

◆ CCU_FAN_REG_CLK_FANOUT3_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT3_SEL_PCLK   0b110

◆ CCU_GPADC_24M_REG

#define CCU_GPADC_24M_REG   (SUNXI_CCU_BASE + GPADC0_24M_CLK_REG)

◆ CCU_GPADC_BGR_REG

#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC0_BGR_REG)

◆ CCU_LRADC_BGR_REG

#define CCU_LRADC_BGR_REG   (SUNXI_CCU_BASE + LRADC_BGR_REG)

◆ CCU_MBUS_GATE_ENABLE_REG

#define CCU_MBUS_GATE_ENABLE_REG   (SUNXI_CCU_BASE + MBUS_GATE_EN_REG)

◆ CCU_MBUS_MST_CLK_GATING_REG

#define CCU_MBUS_MST_CLK_GATING_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

◆ CCU_MMC_CTRL_ENABLE

#define CCU_MMC_CTRL_ENABLE   (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)

◆ CCU_MMC_CTRL_M

#define CCU_MMC_CTRL_M (   x)    (x)

◆ CCU_MMC_CTRL_N

#define CCU_MMC_CTRL_N (   x)    ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)

◆ CCU_MMC_CTRL_OCLK_DLY

#define CCU_MMC_CTRL_OCLK_DLY (   a)    ((void) (a), 0)

◆ CCU_MMC_CTRL_OSCM24

#define CCU_MMC_CTRL_OSCM24   (SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI0_300M

#define CCU_MMC_CTRL_PERI0_300M   (0x2 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI0_300M_freq

#define CCU_MMC_CTRL_PERI0_300M_freq   (300000000)

◆ CCU_MMC_CTRL_PERI0_400M

#define CCU_MMC_CTRL_PERI0_400M   (0x1 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI0_400M_freq

#define CCU_MMC_CTRL_PERI0_400M_freq   (400000000)

◆ CCU_MMC_CTRL_PERI0_600M

#define CCU_MMC_CTRL_PERI0_600M   (0x2 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI0_600M_freq

#define CCU_MMC_CTRL_PERI0_600M_freq   (600000000)

◆ CCU_MMC_CTRL_PERI0_800M

#define CCU_MMC_CTRL_PERI0_800M   (0x1 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI0_800M_freq

#define CCU_MMC_CTRL_PERI0_800M_freq   (800000000)

◆ CCU_MMC_CTRL_PERI1_300M

#define CCU_MMC_CTRL_PERI1_300M   (0x4 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI1_400M

#define CCU_MMC_CTRL_PERI1_400M   (0x3 << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI1_600M

#define CCU_MMC_CTRL_PERI1_600M   (0x4 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PERI1_800M

#define CCU_MMC_CTRL_PERI1_800M   (0x3 << SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PLL6X2

#define CCU_MMC_CTRL_PLL6X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PLL_PERIPH2X2

#define CCU_MMC_CTRL_PLL_PERIPH2X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_SCLK_DLY

#define CCU_MMC_CTRL_SCLK_DLY (   a)    ((void) (a), 0)

◆ CCU_NSI_BGR_REG

#define CCU_NSI_BGR_REG   (SUNXI_CCU_BASE + NSI_BGR_REG)

◆ CCU_NSI_CLK_GREG

#define CCU_NSI_CLK_GREG   (SUNXI_CCU_BASE + NSI_CLK_REG)

◆ CCU_PLL_CPU_B_CLK_REG

#define CCU_PLL_CPU_B_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x201c)

◆ CCU_PLL_CPU_B_CTRL_REG

#define CCU_PLL_CPU_B_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x2000)

◆ CCU_PLL_CPU_DSU_CTRL_REG

#define CCU_PLL_CPU_DSU_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x3000)

◆ CCU_PLL_CPU_L_CLK_REG

#define CCU_PLL_CPU_L_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x101c)

◆ CCU_PLL_CPU_L_CTRL_REG

#define CCU_PLL_CPU_L_CTRL_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x1000)

◆ CCU_PLL_DSU_CLK_REG

#define CCU_PLL_DSU_CLK_REG   (SUNXI_CPU_PLL_CFG_BASE + 0x301c)

◆ CCU_PLL_PERI0_CTRL_REG

#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI0_CTRL_REG)

◆ CCU_PLL_PERI1_CTRL_REG

#define CCU_PLL_PERI1_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI1_CTRL_REG)

◆ CCU_SDMMC0_CLK_REG

#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)

◆ CCU_SDMMC1_CLK_REG

#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)

◆ CCU_SDMMC2_CLK_REG

#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + SMHC2_CLK_REG)

◆ CCU_SEC_SWITCH_REG

#define CCU_SEC_SWITCH_REG   0x00001f00

◆ CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   (0x00000002)

◆ CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   (0x00000004)

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   (0x00000001)

◆ CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0

◆ CCU_SMHC0_BGR_REG

#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC0_BGR_REG)

◆ CCU_UART_BGR_REG

#define CCU_UART_BGR_REG   (SUNXI_CCU_BASE + UART0_BGR_REG)

◆ CCU_VERSION_REG

#define CCU_VERSION_REG   0x00001ff0

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   (0xffff0000)

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16

◆ CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   (0x0000ffff)

◆ CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0

◆ CE_BGR_REG

#define CE_BGR_REG   0x00000ac4

◆ CE_BGR_REG_CE_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_GATING_CLEAR_MASK   (0x00000001)

◆ CE_BGR_REG_CE_GATING_MASK

#define CE_BGR_REG_CE_GATING_MASK   0b0

◆ CE_BGR_REG_CE_GATING_OFFSET

#define CE_BGR_REG_CE_GATING_OFFSET   0

◆ CE_BGR_REG_CE_GATING_SECURE_DEBUG

#define CE_BGR_REG_CE_GATING_SECURE_DEBUG   0b1

◆ CE_BGR_REG_CE_RST_ASSERT

#define CE_BGR_REG_CE_RST_ASSERT   0b0

◆ CE_BGR_REG_CE_RST_CLEAR_MASK

#define CE_BGR_REG_CE_RST_CLEAR_MASK   (0x00010000)

◆ CE_BGR_REG_CE_RST_OFFSET

#define CE_BGR_REG_CE_RST_OFFSET   16

◆ CE_BGR_REG_CE_RST_SECURE_DEBUG

#define CE_BGR_REG_CE_RST_SECURE_DEBUG   0b1

◆ CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   (0x00000002)

◆ CE_BGR_REG_CE_SYS_GATING_MASK

#define CE_BGR_REG_CE_SYS_GATING_MASK   0b0

◆ CE_BGR_REG_CE_SYS_GATING_OFFSET

#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1

◆ CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG

#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG   0b1

◆ CE_BGR_REG_CE_SYS_RST_ASSERT

#define CE_BGR_REG_CE_SYS_RST_ASSERT   0b0

◆ CE_BGR_REG_CE_SYS_RST_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   (0x00020000)

◆ CE_BGR_REG_CE_SYS_RST_OFFSET

#define CE_BGR_REG_CE_SYS_RST_OFFSET   17

◆ CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG

#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG   0b1

◆ CE_CLK_DIV_RATION_M

#define CE_CLK_DIV_RATION_M   (0)

◆ CE_CLK_DIV_RATION_M_BIT

#define CE_CLK_DIV_RATION_M_BIT   (CE_CLK_REG_FACTOR_M_OFFSET)

◆ CE_CLK_DIV_RATION_M_MASK

#define CE_CLK_DIV_RATION_M_MASK   (CE_CLK_REG_FACTOR_M_CLEAR_MASK)

◆ CE_CLK_DIV_RATION_N

#define CE_CLK_DIV_RATION_N   (0)

◆ CE_CLK_DIV_RATION_N_BIT

#define CE_CLK_DIV_RATION_N_BIT   (8)

◆ CE_CLK_DIV_RATION_N_MASK

#define CE_CLK_DIV_RATION_N_MASK   (0x3)

◆ CE_CLK_REG

#define CE_CLK_REG   0x00000ac0

◆ CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK

#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CE_CLK_REG_CE_CLK_GATING_OFFSET

#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31

◆ CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG

#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG   0b1

◆ CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CE_CLK_REG_CLK_SRC_SEL_OFFSET

#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ CE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define CE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ CE_CLK_REG_FACTOR_M_CLEAR_MASK

#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CE_CLK_REG_FACTOR_M_OFFSET

#define CE_CLK_REG_FACTOR_M_OFFSET   0

◆ CE_CLK_SRC

#define CE_CLK_SRC   (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)

◆ CE_CLK_SRC_MASK

#define CE_CLK_SRC_MASK   (0x7)

◆ CE_CLK_SRC_SEL_BIT

#define CE_CLK_SRC_SEL_BIT   (CE_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CE_DEASSERT

#define CE_DEASSERT   (CE_BGR_REG_CE_SYS_RST_ASSERT)

◆ CE_GATING_BIT

#define CE_GATING_BIT   (CE_BGR_REG_CE_GATING_OFFSET)

◆ CE_GATING_PASS

#define CE_GATING_PASS   (CE_BGR_REG_CE_GATING_MASK)

◆ CE_MBUS_GATING

#define CE_MBUS_GATING   (1)

◆ CE_MBUS_GATING_BIT

#define CE_MBUS_GATING_BIT   (MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET)

◆ CE_MBUS_GATING_MASK

#define CE_MBUS_GATING_MASK   (1)

◆ CE_RST_BIT

#define CE_RST_BIT   (CE_BGR_REG_CE_RST_OFFSET)

◆ CE_SCLK_ON

#define CE_SCLK_ON   (CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF)

◆ CE_SCLK_ONOFF_BIT

#define CE_SCLK_ONOFF_BIT   (CE_CLK_REG_CE_CLK_GATING_OFFSET)

◆ CE_SYS_GATING_BIT

#define CE_SYS_GATING_BIT   (CE_BGR_REG_CE_SYS_GATING_OFFSET)

◆ CE_SYS_RST_BIT

#define CE_SYS_RST_BIT   (CE_BGR_REG_CE_SYS_RST_OFFSET)

◆ CLK24M_GATE_EN_REG

#define CLK24M_GATE_EN_REG   0x00001a00

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   (0x00000008)

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0b0

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0b1

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3

◆ CLK27M_FAN_REG

#define CLK27M_FAN_REG   0x00001f34

◆ CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   (0x0000001f)

◆ CLK27M_FAN_REG_CLK27M_DIV0_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0

◆ CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   (0x00001f00)

◆ CLK27M_FAN_REG_CLK27M_DIV1_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8

◆ CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   (0x80000000)

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1

◆ CLK27M_FAN_REG_CLK27M_EN_OFFSET

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   (0x03000000)

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X   0b000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X   0b001

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X   0b010

◆ CLK_FAN_REG

#define CLK_FAN_REG   0x00001f38

◆ CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   (0x000003e0)

◆ CLK_FAN_REG_PCLK_DIV1_OFFSET

#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5

◆ CLK_FAN_REG_PCLK_DIV_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   (0x0000001f)

◆ CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   (0x80000000)

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1

◆ CLK_FAN_REG_PCLK_DIV_EN_OFFSET

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31

◆ CLK_FAN_REG_PCLK_DIV_OFFSET

#define CLK_FAN_REG_PCLK_DIV_OFFSET   0

◆ CM_DESYS_CFG_REG

#define CM_DESYS_CFG_REG   0x00001b04

◆ CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE   0b0

◆ CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE   0b1

◆ CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET

#define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET   0

◆ CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET   16

◆ CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF   0b01

◆ CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON

#define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON   0b10

◆ CM_GPU0_CFG_REG

#define CM_GPU0_CFG_REG   0x00001b24

◆ CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE   0b0

◆ CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE   0b1

◆ CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET

#define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET   0

◆ CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET   16

◆ CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF   0b01

◆ CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON

#define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON   0b10

◆ CM_NPU_CFG_REG

#define CM_NPU_CFG_REG   0x00001b1c

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE   0b0

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE   0b1

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET   0

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK

#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET

#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET   16

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF   0b01

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON   0b10

◆ CM_PCIE0_CFG_REG

#define CM_PCIE0_CFG_REG   0x00001b28

◆ CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE   0b0

◆ CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE   0b1

◆ CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET

#define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET   0

◆ CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET   16

◆ CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF   0b01

◆ CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON

#define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON   0b10

◆ CM_USB2_CFG_REG

#define CM_USB2_CFG_REG   0x00001b30

◆ CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_CLEAR_MASK

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_DISABLE

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_DISABLE   0b0

◆ CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_ENABLE

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_ENABLE   0b1

◆ CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_OFFSET

#define CM_USB2_CFG_REG_CM_USB2_MODULE_MODE_OFFSET   0

◆ CM_USB2_CFG_REG_CM_USB2_STATUS_CLEAR_MASK

#define CM_USB2_CFG_REG_CM_USB2_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_USB2_CFG_REG_CM_USB2_STATUS_OFFSET

#define CM_USB2_CFG_REG_CM_USB2_STATUS_OFFSET   16

◆ CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_OFF

#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_OFF   0b01

◆ CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_ON

#define CM_USB2_CFG_REG_CM_USB2_STATUS_POWER_ON   0b10

◆ CM_VE_DEC_CFG_REG

#define CM_VE_DEC_CFG_REG   0x00001b10

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE   0b0

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE   0b1

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET   0

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET   16

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF   0b01

◆ CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON

#define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON   0b10

◆ CM_VE_ENC_CFG_REG

#define CM_VE_ENC_CFG_REG   0x00001b14

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE   0b0

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE   0b1

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET   0

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET   16

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF   0b01

◆ CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON

#define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON   0b10

◆ CM_VI_CFG_REG

#define CM_VI_CFG_REG   0x00001b00

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE   0b0

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE   0b1

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET   0

◆ CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK

#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_VI_CFG_REG_CM_VI_STATUS_OFFSET

#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET   16

◆ CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF   0b01

◆ CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON   0b10

◆ CM_VO1_CFG_REG

#define CM_VO1_CFG_REG   0x00001b38

◆ CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE   0b0

◆ CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE   0b1

◆ CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET

#define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET   0

◆ CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK

#define CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET

#define CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET   16

◆ CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF

#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF   0b01

◆ CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON

#define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON   0b10

◆ CM_VO_CFG_REG

#define CM_VO_CFG_REG   0x00001b34

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK   (0x00000001)

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE   0b0

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE   0b1

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET   0

◆ CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK

#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK   (0x00030000)

◆ CM_VO_CFG_REG_CM_VO_STATUS_OFFSET

#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET   16

◆ CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF   0b01

◆ CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON   0b10

◆ COMBPHY0_CLK_REG

#define COMBPHY0_CLK_REG   0x000015c0

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON   0b1

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET   31

◆ COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK

#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ COMBPHY0_CLK_REG_FACTOR_M_OFFSET

#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET   0

◆ COMBPHY1_CLK_REG

#define COMBPHY1_CLK_REG   0x000015c4

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b100

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON   0b1

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET   31

◆ COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK

#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ COMBPHY1_CLK_REG_FACTOR_M_OFFSET

#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET   0

◆ CPU_PERI_CLK_REG

#define CPU_PERI_CLK_REG   0x00000568

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_CLK32K

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ CPU_PERI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define CPU_PERI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLEAR_MASK

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_OFF

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_ON

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_CLOCK_IS_ON   0b1

◆ CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_OFFSET

#define CPU_PERI_CLK_REG_CPU_PERI_CLK_GATING_OFFSET   31

◆ CPU_PERI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CPU_PERI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CPU_PERI_CLK_REG_FACTOR_M_OFFSET

#define CPU_PERI_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_BGR_REG

#define CSI_BGR_REG   0x00001844

◆ CSI_BGR_REG_CSI_GATING_CLEAR_MASK

#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   (0x00000001)

◆ CSI_BGR_REG_CSI_GATING_MASK

#define CSI_BGR_REG_CSI_GATING_MASK   0b0

◆ CSI_BGR_REG_CSI_GATING_OFFSET

#define CSI_BGR_REG_CSI_GATING_OFFSET   0

◆ CSI_BGR_REG_CSI_GATING_PASS

#define CSI_BGR_REG_CSI_GATING_PASS   0b1

◆ CSI_BGR_REG_CSI_RST_ASSERT

#define CSI_BGR_REG_CSI_RST_ASSERT   0b0

◆ CSI_BGR_REG_CSI_RST_CLEAR_MASK

#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   (0x00010000)

◆ CSI_BGR_REG_CSI_RST_DE_ASSERT

#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0b1

◆ CSI_BGR_REG_CSI_RST_OFFSET

#define CSI_BGR_REG_CSI_RST_OFFSET   16

◆ CSI_CLK_REG

#define CSI_CLK_REG   0x00001840

◆ CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X   0b001

◆ CSI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b100

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b110

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_CLK_REG_CSI_CLK_GATING_OFFSET

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31

◆ CSI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CSI_CLK_REG_FACTOR_M_OFFSET

#define CSI_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG

#define CSI_MASTER0_CLK_REG   0x00001800

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31

◆ CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER1_CLK_REG

#define CSI_MASTER1_CLK_REG   0x00001804

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31

◆ CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER2_CLK_REG

#define CSI_MASTER2_CLK_REG   0x00001808

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b010

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b001

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b100

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b011

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b110

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b101

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31

◆ CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8

◆ DBGSYS_BGR_REG

#define DBGSYS_BGR_REG   0x000007a4

◆ DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   (0x00000001)

◆ DBGSYS_BGR_REG_DBGSYS_GATING_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0b0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_PASS

#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0b0

◆ DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   (0x00010000)

◆ DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16

◆ DDRPLL_GATE_EN_REG

#define DDRPLL_GATE_EN_REG   0x00001904

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO   0b0

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET   0

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE   0b0

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE   0b1

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET   16

◆ DDRPLL_GATE_STAT_REG

#define DDRPLL_GATE_STAT_REG   0x00001984

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE   0b0

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE   0b1

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET   16

◆ DE0_BGR_REG

#define DE0_BGR_REG   0x00000a04

◆ DE0_BGR_REG_DE0_GATING_CLEAR_MASK

#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK   (0x00000001)

◆ DE0_BGR_REG_DE0_GATING_MASK

#define DE0_BGR_REG_DE0_GATING_MASK   0b0

◆ DE0_BGR_REG_DE0_GATING_OFFSET

#define DE0_BGR_REG_DE0_GATING_OFFSET   0

◆ DE0_BGR_REG_DE0_GATING_PASS

#define DE0_BGR_REG_DE0_GATING_PASS   0b1

◆ DE0_BGR_REG_DE0_RST_ASSERT

#define DE0_BGR_REG_DE0_RST_ASSERT   0b0

◆ DE0_BGR_REG_DE0_RST_CLEAR_MASK

#define DE0_BGR_REG_DE0_RST_CLEAR_MASK   (0x00010000)

◆ DE0_BGR_REG_DE0_RST_DE_ASSERT

#define DE0_BGR_REG_DE0_RST_DE_ASSERT   0b1

◆ DE0_BGR_REG_DE0_RST_OFFSET

#define DE0_BGR_REG_DE0_RST_OFFSET   16

◆ DE0_CLK_REG

#define DE0_CLK_REG   0x00000a00

◆ DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X

#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b000

◆ DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X   0b001

◆ DE0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b011

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b010

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b101

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b110

◆ DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK

#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON   0b1

◆ DE0_CLK_REG_DE0_CLK_GATING_OFFSET

#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET   31

◆ DE0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ DE0_CLK_REG_FACTOR_M_OFFSET

#define DE0_CLK_REG_FACTOR_M_OFFSET   0

◆ DE_SYS_BGR_REG

#define DE_SYS_BGR_REG   0x00000a74

◆ DE_SYS_BGR_REG_DE_SYS_RST_ASSERT

#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT   0b0

◆ DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK

#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK   (0x00010000)

◆ DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT

#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT   0b1

◆ DE_SYS_BGR_REG_DE_SYS_RST_OFFSET

#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET   16

◆ DEPLL_GATE_EN_REG

#define DEPLL_GATE_EN_REG   0x00001928

◆ DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO   0b0

◆ DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET

#define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET   1

◆ DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE   0b0

◆ DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE   0b1

◆ DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET

#define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET   17

◆ DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO   0b0

◆ DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET

#define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET   0

◆ DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE   0b0

◆ DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE   0b1

◆ DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET

#define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET   16

◆ DEPLL_GATE_STAT_REG

#define DEPLL_GATE_STAT_REG   0x000019a8

◆ DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE   0b0

◆ DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE   0b1

◆ DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET

#define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET   17

◆ DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE   0b0

◆ DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE   0b1

◆ DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET

#define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET   16

◆ DI_BGR_REG

#define DI_BGR_REG   0x00000a24

◆ DI_BGR_REG_DI_GATING_CLEAR_MASK

#define DI_BGR_REG_DI_GATING_CLEAR_MASK   (0x00000001)

◆ DI_BGR_REG_DI_GATING_MASK

#define DI_BGR_REG_DI_GATING_MASK   0b0

◆ DI_BGR_REG_DI_GATING_OFFSET

#define DI_BGR_REG_DI_GATING_OFFSET   0

◆ DI_BGR_REG_DI_GATING_PASS

#define DI_BGR_REG_DI_GATING_PASS   0b1

◆ DI_BGR_REG_DI_RST_ASSERT

#define DI_BGR_REG_DI_RST_ASSERT   0b0

◆ DI_BGR_REG_DI_RST_CLEAR_MASK

#define DI_BGR_REG_DI_RST_CLEAR_MASK   (0x00010000)

◆ DI_BGR_REG_DI_RST_DE_ASSERT

#define DI_BGR_REG_DI_RST_DE_ASSERT   0b1

◆ DI_BGR_REG_DI_RST_OFFSET

#define DI_BGR_REG_DI_RST_OFFSET   16

◆ DI_CLK_REG

#define DI_CLK_REG   0x00000a20

◆ DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ DI_CLK_REG_CLK_SRC_SEL_OFFSET

#define DI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010

◆ DI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ DI_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000

◆ DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b011

◆ DI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define DI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b100

◆ DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK

#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON   0b1

◆ DI_CLK_REG_DI_CLK_GATING_OFFSET

#define DI_CLK_REG_DI_CLK_GATING_OFFSET   31

◆ DI_CLK_REG_FACTOR_M_CLEAR_MASK

#define DI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ DI_CLK_REG_FACTOR_M_OFFSET

#define DI_CLK_REG_FACTOR_M_OFFSET   0

◆ DMA0_BGR_REG

#define DMA0_BGR_REG   0x00000704

◆ DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK

#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK   (0x00000001)

◆ DMA0_BGR_REG_DMA0_GATING_MASK

#define DMA0_BGR_REG_DMA0_GATING_MASK   0b0

◆ DMA0_BGR_REG_DMA0_GATING_OFFSET

#define DMA0_BGR_REG_DMA0_GATING_OFFSET   0

◆ DMA0_BGR_REG_DMA0_GATING_PASS

#define DMA0_BGR_REG_DMA0_GATING_PASS   0b1

◆ DMA0_BGR_REG_DMA0_RST_ASSERT

#define DMA0_BGR_REG_DMA0_RST_ASSERT   0b0

◆ DMA0_BGR_REG_DMA0_RST_CLEAR_MASK

#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK   (0x00010000)

◆ DMA0_BGR_REG_DMA0_RST_DE_ASSERT

#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT   0b1

◆ DMA0_BGR_REG_DMA0_RST_OFFSET

#define DMA0_BGR_REG_DMA0_RST_OFFSET   16

◆ DMA1_BGR_REG

#define DMA1_BGR_REG   0x0000070c

◆ DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK

#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK   (0x00000001)

◆ DMA1_BGR_REG_DMA1_GATING_MASK

#define DMA1_BGR_REG_DMA1_GATING_MASK   0b0

◆ DMA1_BGR_REG_DMA1_GATING_OFFSET

#define DMA1_BGR_REG_DMA1_GATING_OFFSET   0

◆ DMA1_BGR_REG_DMA1_GATING_PASS

#define DMA1_BGR_REG_DMA1_GATING_PASS   0b1

◆ DMA1_BGR_REG_DMA1_RST_ASSERT

#define DMA1_BGR_REG_DMA1_RST_ASSERT   0b0

◆ DMA1_BGR_REG_DMA1_RST_CLEAR_MASK

#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK   (0x00010000)

◆ DMA1_BGR_REG_DMA1_RST_DE_ASSERT

#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT   0b1

◆ DMA1_BGR_REG_DMA1_RST_OFFSET

#define DMA1_BGR_REG_DMA1_RST_OFFSET   16

◆ DMA_GATING_BASE

#define DMA_GATING_BASE   CCU_DMA_BGR_REG

◆ DMA_GATING_BIT

#define DMA_GATING_BIT   (0)

◆ DMA_GATING_PASS

#define DMA_GATING_PASS   (1)

◆ DMIC_BGR_REG

#define DMIC_BGR_REG   0x000012cc

◆ DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK

#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK   (0x00000001)

◆ DMIC_BGR_REG_DMIC_GATING_MASK

#define DMIC_BGR_REG_DMIC_GATING_MASK   0b0

◆ DMIC_BGR_REG_DMIC_GATING_OFFSET

#define DMIC_BGR_REG_DMIC_GATING_OFFSET   0

◆ DMIC_BGR_REG_DMIC_GATING_PASS

#define DMIC_BGR_REG_DMIC_GATING_PASS   0b1

◆ DMIC_BGR_REG_DMIC_RST_ASSERT

#define DMIC_BGR_REG_DMIC_RST_ASSERT   0b0

◆ DMIC_BGR_REG_DMIC_RST_CLEAR_MASK

#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK   (0x00010000)

◆ DMIC_BGR_REG_DMIC_RST_DE_ASSERT

#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT   0b1

◆ DMIC_BGR_REG_DMIC_RST_OFFSET

#define DMIC_BGR_REG_DMIC_RST_OFFSET   16

◆ DMIC_CLK_REG

#define DMIC_CLK_REG   0x000012c0

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ DMIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON   0b1

◆ DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET

#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET   31

◆ DMIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ DMIC_CLK_REG_FACTOR_M_OFFSET

#define DMIC_CLK_REG_FACTOR_M_OFFSET   0

◆ DPSS_TOP0_BGR_REG

#define DPSS_TOP0_BGR_REG   0x000016c4

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK   (0x00000001)

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK   0b0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET   0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS   0b1

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT   0b0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK   (0x00010000)

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT   0b1

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET   16

◆ DPSS_TOP1_BGR_REG

#define DPSS_TOP1_BGR_REG   0x000016cc

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK   (0x00000001)

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK   0b0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET   0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS   0b1

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT   0b0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK   (0x00010000)

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT   0b1

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET   16

◆ DRAM0_BGR_REG

#define DRAM0_BGR_REG   0x00000c0c

◆ DRAM0_BGR_REG_DRAM0_GATING_CLEAR_MASK

#define DRAM0_BGR_REG_DRAM0_GATING_CLEAR_MASK   (0x00000001)

◆ DRAM0_BGR_REG_DRAM0_GATING_MASK

#define DRAM0_BGR_REG_DRAM0_GATING_MASK   0b0

◆ DRAM0_BGR_REG_DRAM0_GATING_OFFSET

#define DRAM0_BGR_REG_DRAM0_GATING_OFFSET   0

◆ DRAM0_BGR_REG_DRAM0_GATING_PASS

#define DRAM0_BGR_REG_DRAM0_GATING_PASS   0b1

◆ DRAM0_BGR_REG_DRAM0_RST_ASSERT

#define DRAM0_BGR_REG_DRAM0_RST_ASSERT   0b0

◆ DRAM0_BGR_REG_DRAM0_RST_CLEAR_MASK

#define DRAM0_BGR_REG_DRAM0_RST_CLEAR_MASK   (0x00010000)

◆ DRAM0_BGR_REG_DRAM0_RST_DE_ASSERT

#define DRAM0_BGR_REG_DRAM0_RST_DE_ASSERT   0b1

◆ DRAM0_BGR_REG_DRAM0_RST_OFFSET

#define DRAM0_BGR_REG_DRAM0_RST_OFFSET   16

◆ DRAM0_CLK_REG

#define DRAM0_CLK_REG   0x00000c00

◆ DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON   0b1

◆ DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET

#define DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET   31

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK   (0x07000000)

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL   0b000

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X   0b011

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL   0b100

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET   24

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M   0b010

◆ DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M

#define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M   0b001

◆ DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK   (0x00010000)

◆ DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_8

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_8   0b1

◆ DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY   0b0

◆ DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET

#define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET   16

◆ DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK

#define DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK   (0x0000001f)

◆ DRAM0_CLK_REG_DRAM0_DIV1_OFFSET

#define DRAM0_CLK_REG_DRAM0_DIV1_OFFSET   0

◆ DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK

#define DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK   (0x08000000)

◆ DRAM0_CLK_REG_DRAM0_UPD_INVALID

#define DRAM0_CLK_REG_DRAM0_UPD_INVALID   0b0

◆ DRAM0_CLK_REG_DRAM0_UPD_OFFSET

#define DRAM0_CLK_REG_DRAM0_UPD_OFFSET   27

◆ DRAM0_CLK_REG_DRAM0_UPD_VALID

#define DRAM0_CLK_REG_DRAM0_UPD_VALID   0b1

◆ DSC_BGR_REG

#define DSC_BGR_REG   0x00001744

◆ DSC_BGR_REG_DSC_GATING_CLEAR_MASK

#define DSC_BGR_REG_DSC_GATING_CLEAR_MASK   (0x00000001)

◆ DSC_BGR_REG_DSC_GATING_MASK

#define DSC_BGR_REG_DSC_GATING_MASK   0b0

◆ DSC_BGR_REG_DSC_GATING_OFFSET

#define DSC_BGR_REG_DSC_GATING_OFFSET   0

◆ DSC_BGR_REG_DSC_GATING_PASS

#define DSC_BGR_REG_DSC_GATING_PASS   0b1

◆ DSC_BGR_REG_DSC_RST_ASSERT

#define DSC_BGR_REG_DSC_RST_ASSERT   0b0

◆ DSC_BGR_REG_DSC_RST_CLEAR_MASK

#define DSC_BGR_REG_DSC_RST_CLEAR_MASK   (0x00010000)

◆ DSC_BGR_REG_DSC_RST_DE_ASSERT

#define DSC_BGR_REG_DSC_RST_DE_ASSERT   0b1

◆ DSC_BGR_REG_DSC_RST_OFFSET

#define DSC_BGR_REG_DSC_RST_OFFSET   16

◆ DSI0_BGR_REG

#define DSI0_BGR_REG   0x00001584

◆ DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK

#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK   (0x00000001)

◆ DSI0_BGR_REG_DSI0_GATING_MASK

#define DSI0_BGR_REG_DSI0_GATING_MASK   0b0

◆ DSI0_BGR_REG_DSI0_GATING_OFFSET

#define DSI0_BGR_REG_DSI0_GATING_OFFSET   0

◆ DSI0_BGR_REG_DSI0_GATING_PASS

#define DSI0_BGR_REG_DSI0_GATING_PASS   0b1

◆ DSI0_BGR_REG_DSI0_RST_ASSERT

#define DSI0_BGR_REG_DSI0_RST_ASSERT   0b0

◆ DSI0_BGR_REG_DSI0_RST_CLEAR_MASK

#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK   (0x00010000)

◆ DSI0_BGR_REG_DSI0_RST_DE_ASSERT

#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT   0b1

◆ DSI0_BGR_REG_DSI0_RST_OFFSET

#define DSI0_BGR_REG_DSI0_RST_OFFSET   16

◆ DSI0_CLK_REG

#define DSI0_CLK_REG   0x00001580

◆ DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ DSI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ DSI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define DSI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON   0b1

◆ DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET

#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET   31

◆ DSI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ DSI0_CLK_REG_FACTOR_M_OFFSET

#define DSI0_CLK_REG_FACTOR_M_OFFSET   0

◆ DSI1_BGR_REG

#define DSI1_BGR_REG   0x0000158c

◆ DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK

#define DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK   (0x00000001)

◆ DSI1_BGR_REG_DSI1_GATING_MASK

#define DSI1_BGR_REG_DSI1_GATING_MASK   0b0

◆ DSI1_BGR_REG_DSI1_GATING_OFFSET

#define DSI1_BGR_REG_DSI1_GATING_OFFSET   0

◆ DSI1_BGR_REG_DSI1_GATING_PASS

#define DSI1_BGR_REG_DSI1_GATING_PASS   0b1

◆ DSI1_BGR_REG_DSI1_RST_ASSERT

#define DSI1_BGR_REG_DSI1_RST_ASSERT   0b0

◆ DSI1_BGR_REG_DSI1_RST_CLEAR_MASK

#define DSI1_BGR_REG_DSI1_RST_CLEAR_MASK   (0x00010000)

◆ DSI1_BGR_REG_DSI1_RST_DE_ASSERT

#define DSI1_BGR_REG_DSI1_RST_DE_ASSERT   0b1

◆ DSI1_BGR_REG_DSI1_RST_OFFSET

#define DSI1_BGR_REG_DSI1_RST_OFFSET   16

◆ DSI1_CLK_REG

#define DSI1_CLK_REG   0x00001588

◆ DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ DSI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M   0b010

◆ DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ DSI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define DSI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON   0b1

◆ DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET

#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET   31

◆ DSI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ DSI1_CLK_REG_FACTOR_M_OFFSET

#define DSI1_CLK_REG_FACTOR_M_OFFSET   0

◆ EDP_BGR_REG

#define EDP_BGR_REG   0x0000164c

◆ EDP_BGR_REG_EDP_GATING_CLEAR_MASK

#define EDP_BGR_REG_EDP_GATING_CLEAR_MASK   (0x00000001)

◆ EDP_BGR_REG_EDP_GATING_MASK

#define EDP_BGR_REG_EDP_GATING_MASK   0b0

◆ EDP_BGR_REG_EDP_GATING_OFFSET

#define EDP_BGR_REG_EDP_GATING_OFFSET   0

◆ EDP_BGR_REG_EDP_GATING_PASS

#define EDP_BGR_REG_EDP_GATING_PASS   0b1

◆ EDP_BGR_REG_EDP_RST_ASSERT

#define EDP_BGR_REG_EDP_RST_ASSERT   0b0

◆ EDP_BGR_REG_EDP_RST_CLEAR_MASK

#define EDP_BGR_REG_EDP_RST_CLEAR_MASK   (0x00010000)

◆ EDP_BGR_REG_EDP_RST_DE_ASSERT

#define EDP_BGR_REG_EDP_RST_DE_ASSERT   0b1

◆ EDP_BGR_REG_EDP_RST_OFFSET

#define EDP_BGR_REG_EDP_RST_OFFSET   16

◆ EDP_TV_CLK_REG

#define EDP_TV_CLK_REG   0x00001640

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define EDP_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_OFFSET

#define EDP_TV_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define EDP_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define EDP_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLEAR_MASK

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_OFF

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_OFF   0b0

◆ EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_ON

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_CLOCK_IS_ON   0b1

◆ EDP_TV_CLK_REG_EDP_TV_CLK_GATING_OFFSET

#define EDP_TV_CLK_REG_EDP_TV_CLK_GATING_OFFSET   31

◆ EDP_TV_CLK_REG_FACTOR_M_CLEAR_MASK

#define EDP_TV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ EDP_TV_CLK_REG_FACTOR_M_OFFSET

#define EDP_TV_CLK_REG_FACTOR_M_OFFSET   0

◆ EDP_TV_CLK_REG_FACTOR_N_CLEAR_MASK

#define EDP_TV_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ EDP_TV_CLK_REG_FACTOR_N_OFFSET

#define EDP_TV_CLK_REG_FACTOR_N_OFFSET   8

◆ EINK_BGR_REG

#define EINK_BGR_REG   0x00000a6c

◆ EINK_BGR_REG_EINK_GATING_CLEAR_MASK

#define EINK_BGR_REG_EINK_GATING_CLEAR_MASK   (0x00000001)

◆ EINK_BGR_REG_EINK_GATING_MASK

#define EINK_BGR_REG_EINK_GATING_MASK   0b0

◆ EINK_BGR_REG_EINK_GATING_OFFSET

#define EINK_BGR_REG_EINK_GATING_OFFSET   0

◆ EINK_BGR_REG_EINK_GATING_PASS

#define EINK_BGR_REG_EINK_GATING_PASS   0b1

◆ EINK_BGR_REG_EINK_RST_ASSERT

#define EINK_BGR_REG_EINK_RST_ASSERT   0b0

◆ EINK_BGR_REG_EINK_RST_CLEAR_MASK

#define EINK_BGR_REG_EINK_RST_CLEAR_MASK   (0x00010000)

◆ EINK_BGR_REG_EINK_RST_DE_ASSERT

#define EINK_BGR_REG_EINK_RST_DE_ASSERT   0b1

◆ EINK_BGR_REG_EINK_RST_OFFSET

#define EINK_BGR_REG_EINK_RST_OFFSET   16

◆ EINK_CLK_REG

#define EINK_CLK_REG   0x00000a60

◆ EINK_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define EINK_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ EINK_CLK_REG_CLK_SRC_SEL_OFFSET

#define EINK_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ EINK_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ EINK_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define EINK_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b000

◆ EINK_CLK_REG_EINK_CLK_GATING_CLEAR_MASK

#define EINK_CLK_REG_EINK_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_OFF

#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_OFF   0b0

◆ EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_ON

#define EINK_CLK_REG_EINK_CLK_GATING_CLOCK_IS_ON   0b1

◆ EINK_CLK_REG_EINK_CLK_GATING_OFFSET

#define EINK_CLK_REG_EINK_CLK_GATING_OFFSET   31

◆ EINK_CLK_REG_FACTOR_M_CLEAR_MASK

#define EINK_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ EINK_CLK_REG_FACTOR_M_OFFSET

#define EINK_CLK_REG_FACTOR_M_OFFSET   0

◆ EINK_PANEL_CLK_REG

#define EINK_PANEL_CLK_REG   0x00000a64

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b100

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b001

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b011

◆ EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define EINK_PANEL_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b010

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_OFF   0b0

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_CLOCK_IS_ON   0b1

◆ EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET

#define EINK_PANEL_CLK_REG_EINK_PANEL_CLK_GATING_OFFSET   31

◆ EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK

#define EINK_PANEL_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ EINK_PANEL_CLK_REG_FACTOR_M_OFFSET

#define EINK_PANEL_CLK_REG_FACTOR_M_OFFSET   0

◆ EXT_LOSC_GSM_HIGH

#define EXT_LOSC_GSM_HIGH   (0x0000000C)

◆ G2D_BGR_REG

#define G2D_BGR_REG   0x00000a44

◆ G2D_BGR_REG_G2D_GATING_CLEAR_MASK

#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   (0x00000001)

◆ G2D_BGR_REG_G2D_GATING_MASK

#define G2D_BGR_REG_G2D_GATING_MASK   0b0

◆ G2D_BGR_REG_G2D_GATING_OFFSET

#define G2D_BGR_REG_G2D_GATING_OFFSET   0

◆ G2D_BGR_REG_G2D_GATING_PASS

#define G2D_BGR_REG_G2D_GATING_PASS   0b1

◆ G2D_BGR_REG_G2D_RST_ASSERT

#define G2D_BGR_REG_G2D_RST_ASSERT   0b0

◆ G2D_BGR_REG_G2D_RST_CLEAR_MASK

#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   (0x00010000)

◆ G2D_BGR_REG_G2D_RST_DE_ASSERT

#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0b1

◆ G2D_BGR_REG_G2D_RST_OFFSET

#define G2D_BGR_REG_G2D_RST_OFFSET   16

◆ G2D_CLK_REG

#define G2D_CLK_REG   0x00000a40

◆ G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ G2D_CLK_REG_CLK_SRC_SEL_OFFSET

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b010

◆ G2D_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b011

◆ G2D_CLK_REG_FACTOR_M_CLEAR_MASK

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ G2D_CLK_REG_FACTOR_M_OFFSET

#define G2D_CLK_REG_FACTOR_M_OFFSET   0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1

◆ G2D_CLK_REG_G2D_CLK_GATING_OFFSET

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31

◆ GATING_SHIFT

#define GATING_SHIFT   (0)

◆ GIC_CLK_REG

#define GIC_CLK_REG   0x00000560

◆ GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ GIC_CLK_REG_CLK_SRC_SEL_CLK32K

#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ GIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ GIC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define GIC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ GIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ GIC_CLK_REG_FACTOR_M_OFFSET

#define GIC_CLK_REG_FACTOR_M_OFFSET   0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK

#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON   0b1

◆ GIC_CLK_REG_GIC_CLK_GATING_OFFSET

#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET   31

◆ GMAC0_BGR_REG

#define GMAC0_BGR_REG   0x0000141c

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT

#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT   0b0

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK   (0x00020000)

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT

#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT   0b1

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET

#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET   17

◆ GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK   (0x00000001)

◆ GMAC0_BGR_REG_GMAC0_GATING_MASK

#define GMAC0_BGR_REG_GMAC0_GATING_MASK   0b0

◆ GMAC0_BGR_REG_GMAC0_GATING_OFFSET

#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET   0

◆ GMAC0_BGR_REG_GMAC0_GATING_PASS

#define GMAC0_BGR_REG_GMAC0_GATING_PASS   0b1

◆ GMAC0_BGR_REG_GMAC0_RST_ASSERT

#define GMAC0_BGR_REG_GMAC0_RST_ASSERT   0b0

◆ GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK   (0x00010000)

◆ GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT

#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT   0b1

◆ GMAC0_BGR_REG_GMAC0_RST_OFFSET

#define GMAC0_BGR_REG_GMAC0_RST_OFFSET   16

◆ GMAC0_PHY_CLK_REG

#define GMAC0_PHY_CLK_REG   0x00001410

◆ GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET

#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET   0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON   0b1

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET   31

◆ GMAC1_BGR_REG

#define GMAC1_BGR_REG   0x0000142c

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT

#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT   0b0

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK   (0x00020000)

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT

#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT   0b1

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET

#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET   17

◆ GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK   (0x00000001)

◆ GMAC1_BGR_REG_GMAC1_GATING_MASK

#define GMAC1_BGR_REG_GMAC1_GATING_MASK   0b0

◆ GMAC1_BGR_REG_GMAC1_GATING_OFFSET

#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET   0

◆ GMAC1_BGR_REG_GMAC1_GATING_PASS

#define GMAC1_BGR_REG_GMAC1_GATING_PASS   0b1

◆ GMAC1_BGR_REG_GMAC1_RST_ASSERT

#define GMAC1_BGR_REG_GMAC1_RST_ASSERT   0b0

◆ GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK   (0x00010000)

◆ GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT

#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT   0b1

◆ GMAC1_BGR_REG_GMAC1_RST_OFFSET

#define GMAC1_BGR_REG_GMAC1_RST_OFFSET   16

◆ GMAC1_PHY_CLK_REG

#define GMAC1_PHY_CLK_REG   0x00001420

◆ GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET

#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET   0

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON   0b1

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET   31

◆ GMAC_PTP_CLK_REG

#define GMAC_PTP_CLK_REG   0x00001400

◆ GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ GMAC_PTP_CLK_REG_FACTOR_M_OFFSET

#define GMAC_PTP_CLK_REG_FACTOR_M_OFFSET   0

◆ GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON   0b1

◆ GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET

#define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET   31

◆ GPADC0_24M_CLK_REG

#define GPADC0_24M_CLK_REG   0x00000fc0

◆ GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ GPADC0_24M_CLK_REG_FACTOR_M_OFFSET

#define GPADC0_24M_CLK_REG_FACTOR_M_OFFSET   0

◆ GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON   0b1

◆ GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET

#define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET   31

◆ GPADC0_BGR_REG

#define GPADC0_BGR_REG   0x00000fc4

◆ GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK

#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK   (0x00000001)

◆ GPADC0_BGR_REG_GPADC0_GATING_MASK

#define GPADC0_BGR_REG_GPADC0_GATING_MASK   0b0

◆ GPADC0_BGR_REG_GPADC0_GATING_OFFSET

#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET   0

◆ GPADC0_BGR_REG_GPADC0_GATING_PASS

#define GPADC0_BGR_REG_GPADC0_GATING_PASS   0b1

◆ GPADC0_BGR_REG_GPADC0_RST_ASSERT

#define GPADC0_BGR_REG_GPADC0_RST_ASSERT   0b0

◆ GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK

#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK   (0x00010000)

◆ GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT

#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT   0b1

◆ GPADC0_BGR_REG_GPADC0_RST_OFFSET

#define GPADC0_BGR_REG_GPADC0_RST_OFFSET   16

◆ GPUPLL_GATE_EN_REG

#define GPUPLL_GATE_EN_REG   0x00001914

◆ GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO   0b0

◆ GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET

#define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET   0

◆ GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE   0b0

◆ GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE   0b1

◆ GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET

#define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET   16

◆ GPUPLL_GATE_STAT_REG

#define GPUPLL_GATE_STAT_REG   0x00001994

◆ GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE   0b0

◆ GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE   0b1

◆ GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET

#define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET   16

◆ HDCP_ESM_CLK_REG

#define HDCP_ESM_CLK_REG   0x00001694

◆ HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLEAR_MASK

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_OFF

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_ON

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_CLOCK_IS_ON   0b1

◆ HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_OFFSET

#define HDCP_ESM_CLK_REG_HDCP_ESM_CLK_GATING_OFFSET   31

◆ HDMI_BGR_REG

#define HDMI_BGR_REG   0x0000168c

◆ HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK   (0x00000001)

◆ HDMI_BGR_REG_HDMI_GATING_MASK

#define HDMI_BGR_REG_HDMI_GATING_MASK   0b0

◆ HDMI_BGR_REG_HDMI_GATING_OFFSET

#define HDMI_BGR_REG_HDMI_GATING_OFFSET   0

◆ HDMI_BGR_REG_HDMI_GATING_PASS

#define HDMI_BGR_REG_HDMI_GATING_PASS   0b1

◆ HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT

#define HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT   0b0

◆ HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK   (0x00040000)

◆ HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT

#define HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT   0b1

◆ HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET

#define HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET   18

◆ HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT

#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT   0b0

◆ HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK   (0x00010000)

◆ HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT

#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT   0b1

◆ HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET

#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET   16

◆ HDMI_BGR_REG_HDMI_SUB_RST_ASSERT

#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT   0b0

◆ HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK   (0x00020000)

◆ HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT

#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT   0b1

◆ HDMI_BGR_REG_HDMI_SUB_RST_OFFSET

#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET   17

◆ HDMI_CEC_CLK_REG

#define HDMI_CEC_CLK_REG   0x00001680

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K   0b000

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K_PERI0PLL2X_36621_32_768KHZ

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K_PERI0PLL2X_36621_32_768KHZ   0b001

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON   0b1

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET   31

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK

#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK   (0x40000000)

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF   0b0

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON   0b1

◆ HDMI_CEC_CLK_REG_PERI_GATING_OFFSET

#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET   30

◆ HDMI_SFR_CLK_REG

#define HDMI_SFR_CLK_REG   0x00001690

◆ HDMI_SFR_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ HDMI_SFR_CLK_REG_CLK_SRC_SEL_HOSC

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ HDMI_SFR_CLK_REG_CLK_SRC_SEL_OFFSET

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HDMI_SFR_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define HDMI_SFR_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLEAR_MASK

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_OFF

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_ON

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_CLOCK_IS_ON   0b1

◆ HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_OFFSET

#define HDMI_SFR_CLK_REG_HDMI_SFR_CLK_GATING_OFFSET   31

◆ HDMI_TV_CLK_REG

#define HDMI_TV_CLK_REG   0x00001684

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_OFFSET

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define HDMI_TV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ HDMI_TV_CLK_REG_FACTOR_M_CLEAR_MASK

#define HDMI_TV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ HDMI_TV_CLK_REG_FACTOR_M_OFFSET

#define HDMI_TV_CLK_REG_FACTOR_M_OFFSET   0

◆ HDMI_TV_CLK_REG_FACTOR_N_CLEAR_MASK

#define HDMI_TV_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ HDMI_TV_CLK_REG_FACTOR_N_OFFSET

#define HDMI_TV_CLK_REG_FACTOR_N_OFFSET   8

◆ HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLEAR_MASK

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_OFF

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_OFF   0b0

◆ HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_ON

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_CLOCK_IS_ON   0b1

◆ HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_OFFSET

#define HDMI_TV_CLK_REG_HDMI_TV_CLK_GATING_OFFSET   31

◆ I2SPCM0_BGR_REG

#define I2SPCM0_BGR_REG   0x0000120c

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK   (0x00000001)

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK   0b0

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET   0

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS   0b1

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT

#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT   0b0

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK   (0x00010000)

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT

#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT   0b1

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET

#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET   16

◆ I2SPCM0_CLK_REG

#define I2SPCM0_CLK_REG   0x00001200

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM0_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLEAR_MASK

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_ON

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_OFFSET

#define I2SPCM0_CLK_REG_I2SPCM0_CLK_GATING_OFFSET   31

◆ I2SPCM1_BGR_REG

#define I2SPCM1_BGR_REG   0x0000121c

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK   (0x00000001)

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK   0b0

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET   0

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS   0b1

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT

#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT   0b0

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK   (0x00010000)

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT

#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT   0b1

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET

#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET   16

◆ I2SPCM1_CLK_REG

#define I2SPCM1_CLK_REG   0x00001210

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM1_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET

#define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET   31

◆ I2SPCM2_ASRC_CLK_REG

#define I2SPCM2_ASRC_CLK_REG   0x00001224

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011

◆ I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET

#define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET   31

◆ I2SPCM2_BGR_REG

#define I2SPCM2_BGR_REG   0x0000122c

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT

#define I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT   0x2

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK   (0x00000001)

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK   0b0

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET   0

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS   0b1

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT

#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT   0b0

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK   (0x00010000)

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT

#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT   0b1

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET

#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET   16

◆ I2SPCM2_CLK_REG

#define I2SPCM2_CLK_REG   0x00001220

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM2_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET

#define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET   31

◆ I2SPCM3_BGR_REG

#define I2SPCM3_BGR_REG   0x0000123c

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT

#define I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT   0x3

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK   (0x00000001)

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK   0b0

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET   0

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS   0b1

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT

#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT   0b0

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK   (0x00010000)

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT

#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT   0b1

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET

#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET   16

◆ I2SPCM3_CLK_REG

#define I2SPCM3_CLK_REG   0x00001230

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM3_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET

#define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET   31

◆ I2SPCM4_BGR_REG

#define I2SPCM4_BGR_REG   0x0000124c

◆ I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT

#define I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT   0x4

◆ I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK   (0x00000001)

◆ I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK   0b0

◆ I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET   0

◆ I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS

#define I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS   0b1

◆ I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT

#define I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT   0b0

◆ I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK

#define I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK   (0x00010000)

◆ I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT

#define I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT   0b1

◆ I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET

#define I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET   16

◆ I2SPCM4_CLK_REG

#define I2SPCM4_CLK_REG   0x00001240

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ I2SPCM4_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM4_CLK_REG_FACTOR_M_OFFSET   0

◆ I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET

#define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET   31

◆ IOMMU0_BGR_REG

#define IOMMU0_BGR_REG   0x0000058c

◆ IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_CLEAR_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_CLEAR_MASK   (0x00000004)

◆ IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_MASK   0b0

◆ IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_OFFSET

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_OFFSET   2

◆ IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_PASS

#define IOMMU0_BGR_REG_IOMMU0_SYS_HCLK_GATING_PASS   0b1

◆ IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_CLEAR_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_CLEAR_MASK   (0x00000001)

◆ IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_MASK   0b0

◆ IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_OFFSET

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_OFFSET   0

◆ IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_PASS

#define IOMMU0_BGR_REG_IOMMU0_SYS_MCLK_GATING_PASS   0b1

◆ IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_CLEAR_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_CLEAR_MASK   (0x00000002)

◆ IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_MASK   0b0

◆ IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_OFFSET

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_OFFSET   1

◆ IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_PASS

#define IOMMU0_BGR_REG_IOMMU0_SYS_PCLK_GATING_PASS   0b1

◆ IOMMU0_BGR_REG_IOMMU0_SYS_RST_ASSERT

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_ASSERT   0b0

◆ IOMMU0_BGR_REG_IOMMU0_SYS_RST_CLEAR_MASK

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_CLEAR_MASK   (0x00010000)

◆ IOMMU0_BGR_REG_IOMMU0_SYS_RST_DE_ASSERT

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_DE_ASSERT   0b1

◆ IOMMU0_BGR_REG_IOMMU0_SYS_RST_OFFSET

#define IOMMU0_BGR_REG_IOMMU0_SYS_RST_OFFSET   16

◆ IOMMU1_BGR_REG

#define IOMMU1_BGR_REG   0x000005b4

◆ IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_CLEAR_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_CLEAR_MASK   (0x00000004)

◆ IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_MASK   0b0

◆ IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_OFFSET

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_OFFSET   2

◆ IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_PASS

#define IOMMU1_BGR_REG_IOMMU1_SYS_HCLK_GATING_PASS   0b1

◆ IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_CLEAR_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_CLEAR_MASK   (0x00000001)

◆ IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_MASK   0b0

◆ IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_OFFSET

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_OFFSET   0

◆ IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_PASS

#define IOMMU1_BGR_REG_IOMMU1_SYS_MCLK_GATING_PASS   0b1

◆ IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_CLEAR_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_CLEAR_MASK   (0x00000002)

◆ IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_MASK   0b0

◆ IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_OFFSET

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_OFFSET   1

◆ IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_PASS

#define IOMMU1_BGR_REG_IOMMU1_SYS_PCLK_GATING_PASS   0b1

◆ IOMMU1_BGR_REG_IOMMU1_SYS_RST_ASSERT

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_ASSERT   0b0

◆ IOMMU1_BGR_REG_IOMMU1_SYS_RST_CLEAR_MASK

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_CLEAR_MASK   (0x00010000)

◆ IOMMU1_BGR_REG_IOMMU1_SYS_RST_DE_ASSERT

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_DE_ASSERT   0b1

◆ IOMMU1_BGR_REG_IOMMU1_SYS_RST_OFFSET

#define IOMMU1_BGR_REG_IOMMU1_SYS_RST_OFFSET   16

◆ IRRX_BGR_REG

#define IRRX_BGR_REG   0x00001004

◆ IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK

#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK   (0x00000001)

◆ IRRX_BGR_REG_IRRX_GATING_MASK

#define IRRX_BGR_REG_IRRX_GATING_MASK   0b0

◆ IRRX_BGR_REG_IRRX_GATING_OFFSET

#define IRRX_BGR_REG_IRRX_GATING_OFFSET   0

◆ IRRX_BGR_REG_IRRX_GATING_PASS

#define IRRX_BGR_REG_IRRX_GATING_PASS   0b1

◆ IRRX_BGR_REG_IRRX_RST_ASSERT

#define IRRX_BGR_REG_IRRX_RST_ASSERT   0b0

◆ IRRX_BGR_REG_IRRX_RST_CLEAR_MASK

#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK   (0x00010000)

◆ IRRX_BGR_REG_IRRX_RST_DE_ASSERT

#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT   0b1

◆ IRRX_BGR_REG_IRRX_RST_OFFSET

#define IRRX_BGR_REG_IRRX_RST_OFFSET   16

◆ IRRX_CLK_REG

#define IRRX_CLK_REG   0x00001000

◆ IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ IRRX_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K   0b000

◆ IRRX_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ IRRX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b001

◆ IRRX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ IRRX_CLK_REG_FACTOR_M_OFFSET

#define IRRX_CLK_REG_FACTOR_M_OFFSET   0

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON   0b1

◆ IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET

#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET   31

◆ IRTX_BGR_REG

#define IRTX_BGR_REG   0x0000100c

◆ IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK   (0x00000001)

◆ IRTX_BGR_REG_IRTX_GATING_MASK

#define IRTX_BGR_REG_IRTX_GATING_MASK   0b0

◆ IRTX_BGR_REG_IRTX_GATING_OFFSET

#define IRTX_BGR_REG_IRTX_GATING_OFFSET   0

◆ IRTX_BGR_REG_IRTX_GATING_PASS

#define IRTX_BGR_REG_IRTX_GATING_PASS   0b1

◆ IRTX_BGR_REG_IRTX_RST_ASSERT

#define IRTX_BGR_REG_IRTX_RST_ASSERT   0b0

◆ IRTX_BGR_REG_IRTX_RST_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK   (0x00010000)

◆ IRTX_BGR_REG_IRTX_RST_DE_ASSERT

#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT   0b1

◆ IRTX_BGR_REG_IRTX_RST_OFFSET

#define IRTX_BGR_REG_IRTX_RST_OFFSET   16

◆ IRTX_CLK_REG

#define IRTX_CLK_REG   0x00001008

◆ IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ IRTX_CLK_REG_CLK_SRC_SEL_HOSC

#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ IRTX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b001

◆ IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ IRTX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ IRTX_CLK_REG_FACTOR_M_OFFSET

#define IRTX_CLK_REG_FACTOR_M_OFFSET   0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON   0b1

◆ IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET

#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET   31

◆ ISP_CLK_REG

#define ISP_CLK_REG   0x00001860

◆ ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ ISP_CLK_REG_CLK_SRC_SEL_OFFSET

#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b100

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b101

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b000

◆ ISP_CLK_REG_FACTOR_M_CLEAR_MASK

#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ ISP_CLK_REG_FACTOR_M_OFFSET

#define ISP_CLK_REG_FACTOR_M_OFFSET   0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK

#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0b0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0b1

◆ ISP_CLK_REG_ISP_CLK_GATING_OFFSET

#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31

◆ ITS0_BGR_REG

#define ITS0_BGR_REG   0x00000574

◆ ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_CLEAR_MASK

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_CLEAR_MASK   (0x00000002)

◆ ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_MASK

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_MASK   0b0

◆ ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_OFFSET

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_OFFSET   1

◆ ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_PASS

#define ITS0_BGR_REG_ITS_PCIE0_ACLK_GATING_PASS   0b1

◆ ITS0_BGR_REG_ITS_PCIE0_RST_ASSERT

#define ITS0_BGR_REG_ITS_PCIE0_RST_ASSERT   0b0

◆ ITS0_BGR_REG_ITS_PCIE0_RST_CLEAR_MASK

#define ITS0_BGR_REG_ITS_PCIE0_RST_CLEAR_MASK   (0x00010000)

◆ ITS0_BGR_REG_ITS_PCIE0_RST_DE_ASSERT

#define ITS0_BGR_REG_ITS_PCIE0_RST_DE_ASSERT   0b1

◆ ITS0_BGR_REG_ITS_PCIE0_RST_OFFSET

#define ITS0_BGR_REG_ITS_PCIE0_RST_OFFSET   16

◆ LEDC_BGR_REG

#define LEDC_BGR_REG   0x00001704

◆ LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK   (0x00000001)

◆ LEDC_BGR_REG_LEDC_GATING_MASK

#define LEDC_BGR_REG_LEDC_GATING_MASK   0b0

◆ LEDC_BGR_REG_LEDC_GATING_OFFSET

#define LEDC_BGR_REG_LEDC_GATING_OFFSET   0

◆ LEDC_BGR_REG_LEDC_GATING_PASS

#define LEDC_BGR_REG_LEDC_GATING_PASS   0b1

◆ LEDC_BGR_REG_LEDC_RST_ASSERT

#define LEDC_BGR_REG_LEDC_RST_ASSERT   0b0

◆ LEDC_BGR_REG_LEDC_RST_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK   (0x00010000)

◆ LEDC_BGR_REG_LEDC_RST_DE_ASSERT

#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT   0b1

◆ LEDC_BGR_REG_LEDC_RST_OFFSET

#define LEDC_BGR_REG_LEDC_RST_OFFSET   16

◆ LEDC_CLK_REG

#define LEDC_CLK_REG   0x00001700

◆ LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ LEDC_CLK_REG_CLK_SRC_SEL_HOSC

#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ LEDC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b001

◆ LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ LEDC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ LEDC_CLK_REG_FACTOR_M_OFFSET

#define LEDC_CLK_REG_FACTOR_M_OFFSET   0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0b1

◆ LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET

#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31

◆ LOSC_AUTO_SWT_32K_SEL_DISABLE

#define LOSC_AUTO_SWT_32K_SEL_DISABLE   (0U << 14)

◆ LOSC_AUTO_SWT_32K_SEL_EN

#define LOSC_AUTO_SWT_32K_SEL_EN   (1U << 14)

◆ LOSC_AUTO_SWT_32K_SEL_EN_MASK

#define LOSC_AUTO_SWT_32K_SEL_EN_MASK   (0x00004000)

◆ LOSC_CONTROL_KEY_FIFLD

#define LOSC_CONTROL_KEY_FIFLD   0x16aa0000

◆ LOSC_SRC_SEL_16M

#define LOSC_SRC_SEL_16M   (0U << 0)

◆ LOSC_SRC_SEL_32K

#define LOSC_SRC_SEL_32K   (1U << 0)

◆ LOSC_SRC_SEL_MASK

#define LOSC_SRC_SEL_MASK   (0x00000001)

◆ LPC_BGR_REG

#define LPC_BGR_REG   0x00001084

◆ LPC_BGR_REG_LPC_GATING_CLEAR_MASK

#define LPC_BGR_REG_LPC_GATING_CLEAR_MASK   (0x00000001)

◆ LPC_BGR_REG_LPC_GATING_MASK

#define LPC_BGR_REG_LPC_GATING_MASK   0b0

◆ LPC_BGR_REG_LPC_GATING_OFFSET

#define LPC_BGR_REG_LPC_GATING_OFFSET   0

◆ LPC_BGR_REG_LPC_GATING_PASS

#define LPC_BGR_REG_LPC_GATING_PASS   0b1

◆ LPC_BGR_REG_LPC_RST_ASSERT

#define LPC_BGR_REG_LPC_RST_ASSERT   0b0

◆ LPC_BGR_REG_LPC_RST_CLEAR_MASK

#define LPC_BGR_REG_LPC_RST_CLEAR_MASK   (0x00010000)

◆ LPC_BGR_REG_LPC_RST_DE_ASSERT

#define LPC_BGR_REG_LPC_RST_DE_ASSERT   0b1

◆ LPC_BGR_REG_LPC_RST_OFFSET

#define LPC_BGR_REG_LPC_RST_OFFSET   16

◆ LPC_CLK_REG

#define LPC_CLK_REG   0x00001080

◆ LPC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LPC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ LPC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LPC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ LPC_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define LPC_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011

◆ LPC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X   0b000

◆ LPC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X   0b001

◆ LPC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X

#define LPC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X   0b010

◆ LPC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LPC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ LPC_CLK_REG_FACTOR_M_OFFSET

#define LPC_CLK_REG_FACTOR_M_OFFSET   0

◆ LPC_CLK_REG_LPC_CLK_GATING_CLEAR_MASK

#define LPC_CLK_REG_LPC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_OFF

#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_ON

#define LPC_CLK_REG_LPC_CLK_GATING_CLOCK_IS_ON   0b1

◆ LPC_CLK_REG_LPC_CLK_GATING_OFFSET

#define LPC_CLK_REG_LPC_CLK_GATING_OFFSET   31

◆ LRADC_BGR_REG

#define LRADC_BGR_REG   0x00001024

◆ LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK   (0x00000001)

◆ LRADC_BGR_REG_LRADC_GATING_MASK

#define LRADC_BGR_REG_LRADC_GATING_MASK   0b0

◆ LRADC_BGR_REG_LRADC_GATING_OFFSET

#define LRADC_BGR_REG_LRADC_GATING_OFFSET   0

◆ LRADC_BGR_REG_LRADC_GATING_PASS

#define LRADC_BGR_REG_LRADC_GATING_PASS   0b1

◆ LRADC_BGR_REG_LRADC_RST_ASSERT

#define LRADC_BGR_REG_LRADC_RST_ASSERT   0b0

◆ LRADC_BGR_REG_LRADC_RST_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK   (0x00010000)

◆ LRADC_BGR_REG_LRADC_RST_DE_ASSERT

#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT   0b1

◆ LRADC_BGR_REG_LRADC_RST_OFFSET

#define LRADC_BGR_REG_LRADC_RST_OFFSET   16

◆ LVDS0_BGR_REG

#define LVDS0_BGR_REG   0x00001544

◆ LVDS0_BGR_REG_LVDS0_RST_ASSERT

#define LVDS0_BGR_REG_LVDS0_RST_ASSERT   0b0

◆ LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK

#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK   (0x00010000)

◆ LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT

#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT   0b1

◆ LVDS0_BGR_REG_LVDS0_RST_OFFSET

#define LVDS0_BGR_REG_LVDS0_RST_OFFSET   16

◆ LVDS1_BGR_REG

#define LVDS1_BGR_REG   0x0000154c

◆ LVDS1_BGR_REG_LVDS1_RST_ASSERT

#define LVDS1_BGR_REG_LVDS1_RST_ASSERT   0b0

◆ LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK

#define LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK   (0x00010000)

◆ LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT

#define LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT   0b1

◆ LVDS1_BGR_REG_LVDS1_RST_OFFSET

#define LVDS1_BGR_REG_LVDS1_RST_OFFSET   16

◆ MBUS_CLK_REG

#define MBUS_CLK_REG   0x00000588

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF   0b0

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON   0b1

◆ MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET   31

◆ MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK   (0x07000000)

◆ MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL

#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL   0b010

◆ MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL

#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL   0b101

◆ MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET   24

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M   0b100

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M   0b011

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M   0b001

◆ MBUS_CLK_REG_MBUS_CLK_SEL_SYS_CLK24M

#define MBUS_CLK_REG_MBUS_CLK_SEL_SYS_CLK24M   0b000

◆ MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK   (0x10000000)

◆ MBUS_CLK_REG_MBUS_DFS_EN_DISABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE   0b0

◆ MBUS_CLK_REG_MBUS_DFS_EN_ENABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE   0b1

◆ MBUS_CLK_REG_MBUS_DFS_EN_OFFSET

#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET   28

◆ MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK   (0x0000001f)

◆ MBUS_CLK_REG_MBUS_DIV1_OFFSET

#define MBUS_CLK_REG_MBUS_DIV1_OFFSET   0

◆ MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK   (0x08000000)

◆ MBUS_CLK_REG_MBUS_UPD_INVALID

#define MBUS_CLK_REG_MBUS_UPD_INVALID   0b0

◆ MBUS_CLK_REG_MBUS_UPD_OFFSET

#define MBUS_CLK_REG_MBUS_UPD_OFFSET   27

◆ MBUS_CLK_REG_MBUS_UPD_VALID

#define MBUS_CLK_REG_MBUS_UPD_VALID   0b1

◆ MBUS_GATE_EN_REG

#define MBUS_GATE_EN_REG   0x000005e4

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK   (0x00000004)

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET   2

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG

#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG   0b1

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK   (0x00000100)

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET   8

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK   (0x00000001)

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET   0

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK   (0x00000008)

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET   3

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK   (0x00000800)

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET   11

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK   (0x00001000)

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET   12

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK   (0x00000200)

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET   9

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_NAND_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_CLEAR_MASK   (0x00000020)

◆ MBUS_GATE_EN_REG_NAND_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_NAND_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_OFFSET   5

◆ MBUS_GATE_EN_REG_NAND_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_NAND_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_CLEAR_MASK   (0x00040000)

◆ MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_OFFSET   18

◆ MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_VE_DEC_MCLK_EN_PASS   0b1

◆ MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_CLEAR_MASK   (0x00000002)

◆ MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_MASK   0b0

◆ MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_OFFSET   1

◆ MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_VE_ENC0_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG

#define MBUS_MAT_CLK_GATING_REG   0x000005e0

◆ MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000800)

◆ MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET   11

◆ MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET   16

◆ MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000001)

◆ MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_IOMMU0_MBUS_GATE_SW_CFG_OFFSET   0

◆ MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00000002)

◆ MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_IOMMU1_MBUS_GATE_SW_CFG_OFFSET   1

◆ MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x20000000)

◆ MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET   29

◆ MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x80000000)

◆ MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET   31

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00040000)

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   18

◆ MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x10000000)

◆ MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET   28

◆ MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x40000000)

◆ MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_STORE_MBUS_GATE_SW_CFG_OFFSET   30

◆ MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00004000)

◆ MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET   14

◆ MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x00001000)

◆ MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET   12

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   (0x01000000)

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   24

◆ MEMC_REG_HCLK1_EN

#define MEMC_REG_HCLK1_EN   (1U << 8)

◆ MEMC_REG_HDR_CLK0_EN

#define MEMC_REG_HDR_CLK0_EN   (1U << 9)

◆ MEMC_REG_HDR_CLK1_EN

#define MEMC_REG_HDR_CLK1_EN   (1U << 10)

◆ MEMC_REG_PLLREF_CLK_EN

#define MEMC_REG_PLLREF_CLK_EN   (1U << 13)

◆ MSGBOX0_BGR_REG

#define MSGBOX0_BGR_REG   0x00000744

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   (0x00000001)

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK   0b0

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET   0

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS   0b1

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT

#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT   0b0

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK   (0x00010000)

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT

#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT   0b1

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET

#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET   16

◆ MSI_LITE0_BGR_REG

#define MSI_LITE0_BGR_REG   0x00000594

◆ MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_ASSERT

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_ASSERT   0b0

◆ MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_CLEAR_MASK

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_CLEAR_MASK   (0x00010000)

◆ MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_DE_ASSERT

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_DE_ASSERT   0b1

◆ MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_OFFSET

#define MSI_LITE0_BGR_REG_MSI_LITE0_AHB_RST_OFFSET   16

◆ MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK   (0x00000001)

◆ MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK   0b0

◆ MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET   0

◆ MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS

#define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS   0b1

◆ MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_ASSERT

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_ASSERT   0b0

◆ MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_CLEAR_MASK

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_CLEAR_MASK   (0x00020000)

◆ MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_DE_ASSERT

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_DE_ASSERT   0b1

◆ MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_OFFSET

#define MSI_LITE0_BGR_REG_MSI_LITE0_MBUS_RST_OFFSET   17

◆ MSI_LITE1_BGR_REG

#define MSI_LITE1_BGR_REG   0x0000059c

◆ MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_ASSERT

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_ASSERT   0b0

◆ MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_CLEAR_MASK

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_CLEAR_MASK   (0x00010000)

◆ MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_DE_ASSERT

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_DE_ASSERT   0b1

◆ MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_OFFSET

#define MSI_LITE1_BGR_REG_MSI_LITE1_AHB_RST_OFFSET   16

◆ MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK   (0x00000001)

◆ MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK   0b0

◆ MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET   0

◆ MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS

#define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS   0b1

◆ MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_ASSERT

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_ASSERT   0b0

◆ MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_CLEAR_MASK

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_CLEAR_MASK   (0x00020000)

◆ MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_DE_ASSERT

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_DE_ASSERT   0b1

◆ MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_OFFSET

#define MSI_LITE1_BGR_REG_MSI_LITE1_MBUS_RST_OFFSET   17

◆ MSI_LITE2_BGR_REG

#define MSI_LITE2_BGR_REG   0x000005a4

◆ MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_ASSERT

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_ASSERT   0b0

◆ MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_CLEAR_MASK

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_CLEAR_MASK   (0x00010000)

◆ MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_DE_ASSERT

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_DE_ASSERT   0b1

◆ MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_OFFSET

#define MSI_LITE2_BGR_REG_MSI_LITE2_AHB_RST_OFFSET   16

◆ MSI_LITE2_BGR_REG_MSI_LITE2_GATING_CLEAR_MASK

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_CLEAR_MASK   (0x00000001)

◆ MSI_LITE2_BGR_REG_MSI_LITE2_GATING_MASK

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_MASK   0b0

◆ MSI_LITE2_BGR_REG_MSI_LITE2_GATING_OFFSET

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_OFFSET   0

◆ MSI_LITE2_BGR_REG_MSI_LITE2_GATING_PASS

#define MSI_LITE2_BGR_REG_MSI_LITE2_GATING_PASS   0b1

◆ MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_ASSERT

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_ASSERT   0b0

◆ MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_CLEAR_MASK

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_CLEAR_MASK   (0x00020000)

◆ MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_DE_ASSERT

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_DE_ASSERT   0b1

◆ MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_OFFSET

#define MSI_LITE2_BGR_REG_MSI_LITE2_MBUS_RST_OFFSET   17

◆ NAND0_BGR_REG

#define NAND0_BGR_REG   0x00000c8c

◆ NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK

#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK   (0x00000001)

◆ NAND0_BGR_REG_NAND0_GATING_MASK

#define NAND0_BGR_REG_NAND0_GATING_MASK   0b0

◆ NAND0_BGR_REG_NAND0_GATING_OFFSET

#define NAND0_BGR_REG_NAND0_GATING_OFFSET   0

◆ NAND0_BGR_REG_NAND0_GATING_PASS

#define NAND0_BGR_REG_NAND0_GATING_PASS   0b1

◆ NAND0_BGR_REG_NAND0_RST_ASSERT

#define NAND0_BGR_REG_NAND0_RST_ASSERT   0b0

◆ NAND0_BGR_REG_NAND0_RST_CLEAR_MASK

#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK   (0x00010000)

◆ NAND0_BGR_REG_NAND0_RST_DE_ASSERT

#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT   0b1

◆ NAND0_BGR_REG_NAND0_RST_OFFSET

#define NAND0_BGR_REG_NAND0_RST_OFFSET   16

◆ NAND0_CLK0_CLK_REG

#define NAND0_CLK0_CLK_REG   0x00000c80

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET   0

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON   0b1

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET   31

◆ NAND0_CLK1_CLK_REG

#define NAND0_CLK1_CLK_REG   0x00000c84

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET   0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON   0b1

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET   31

◆ NPU_BGR_REG

#define NPU_BGR_REG   0x00000b04

◆ NPU_BGR_REG_NPU_AHB_RST_ASSERT

#define NPU_BGR_REG_NPU_AHB_RST_ASSERT   0b0

◆ NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK   (0x00040000)

◆ NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT   0b1

◆ NPU_BGR_REG_NPU_AHB_RST_OFFSET

#define NPU_BGR_REG_NPU_AHB_RST_OFFSET   18

◆ NPU_BGR_REG_NPU_AXI_RST_ASSERT

#define NPU_BGR_REG_NPU_AXI_RST_ASSERT   0b0

◆ NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK   (0x00020000)

◆ NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT   0b1

◆ NPU_BGR_REG_NPU_AXI_RST_OFFSET

#define NPU_BGR_REG_NPU_AXI_RST_OFFSET   17

◆ NPU_BGR_REG_NPU_CORE_RST_ASSERT

#define NPU_BGR_REG_NPU_CORE_RST_ASSERT   0b0

◆ NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK   (0x00010000)

◆ NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT   0b1

◆ NPU_BGR_REG_NPU_CORE_RST_OFFSET

#define NPU_BGR_REG_NPU_CORE_RST_OFFSET   16

◆ NPU_BGR_REG_NPU_GATING_CLEAR_MASK

#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK   (0x00000001)

◆ NPU_BGR_REG_NPU_GATING_MASK

#define NPU_BGR_REG_NPU_GATING_MASK   0b0

◆ NPU_BGR_REG_NPU_GATING_OFFSET

#define NPU_BGR_REG_NPU_GATING_OFFSET   0

◆ NPU_BGR_REG_NPU_GATING_PASS

#define NPU_BGR_REG_NPU_GATING_PASS   0b1

◆ NPU_BGR_REG_NPU_SRAM_RST_ASSERT

#define NPU_BGR_REG_NPU_SRAM_RST_ASSERT   0b0

◆ NPU_BGR_REG_NPU_SRAM_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_SRAM_RST_CLEAR_MASK   (0x00080000)

◆ NPU_BGR_REG_NPU_SRAM_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_SRAM_RST_DE_ASSERT   0b1

◆ NPU_BGR_REG_NPU_SRAM_RST_OFFSET

#define NPU_BGR_REG_NPU_SRAM_RST_OFFSET   19

◆ NPU_CLK_REG

#define NPU_CLK_REG   0x00000b00

◆ NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X

#define NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b110

◆ NPU_CLK_REG_CLK_SRC_SEL_NPUPLL

#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL   0b000

◆ NPU_CLK_REG_CLK_SRC_SEL_OFFSET

#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b011

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ NPU_CLK_REG_CLK_SRC_SEL_VE0PLL

#define NPU_CLK_REG_CLK_SRC_SEL_VE0PLL   0b100

◆ NPU_CLK_REG_CLK_SRC_SEL_VE1PLL

#define NPU_CLK_REG_CLK_SRC_SEL_VE1PLL   0b101

◆ NPU_CLK_REG_FACTOR_M_CLEAR_MASK

#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ NPU_CLK_REG_FACTOR_M_OFFSET

#define NPU_CLK_REG_FACTOR_M_OFFSET   0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK

#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0b1

◆ NPU_CLK_REG_NPU_CLK_GATING_OFFSET

#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31

◆ NPUPLL_GATE_EN_REG

#define NPUPLL_GATE_EN_REG   0x00001920

◆ NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET   0

◆ NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET   16

◆ NPUPLL_GATE_STAT_REG

#define NPUPLL_GATE_STAT_REG   0x000019a0

◆ NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE   0b0

◆ NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE   0b1

◆ NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET

#define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET   16

◆ NSI_BGR_REG

#define NSI_BGR_REG   0x00000584

◆ NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK

#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK   (0x00000001)

◆ NSI_BGR_REG_NSI_CFG_GATING_MASK

#define NSI_BGR_REG_NSI_CFG_GATING_MASK   0b0

◆ NSI_BGR_REG_NSI_CFG_GATING_OFFSET

#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET   0

◆ NSI_BGR_REG_NSI_CFG_GATING_PASS

#define NSI_BGR_REG_NSI_CFG_GATING_PASS   0b1

◆ NSI_BGR_REG_NSI_CFG_RST_ASSERT

#define NSI_BGR_REG_NSI_CFG_RST_ASSERT   0b0

◆ NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK

#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK   (0x00010000)

◆ NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT

#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT   0b1

◆ NSI_BGR_REG_NSI_CFG_RST_OFFSET

#define NSI_BGR_REG_NSI_CFG_RST_OFFSET   16

◆ NSI_CLK_REG

#define NSI_CLK_REG   0x00000580

◆ NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON   0b1

◆ NSI_CLK_REG_NSI_CLK_GATING_OFFSET

#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET   31

◆ NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK   (0x07000000)

◆ NSI_CLK_REG_NSI_CLK_SEL_DDRPLL

#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL   0b001

◆ NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X

#define NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X   0b101

◆ NSI_CLK_REG_NSI_CLK_SEL_OFFSET

#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET   24

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M   0b100

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M   0b011

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M   0b010

◆ NSI_CLK_REG_NSI_CLK_SEL_SYS_CLK24M

#define NSI_CLK_REG_NSI_CLK_SEL_SYS_CLK24M   0b000

◆ NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK

#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK   (0x10000000)

◆ NSI_CLK_REG_NSI_DFS_EN_DISABLE

#define NSI_CLK_REG_NSI_DFS_EN_DISABLE   0b0

◆ NSI_CLK_REG_NSI_DFS_EN_ENABLE

#define NSI_CLK_REG_NSI_DFS_EN_ENABLE   0b1

◆ NSI_CLK_REG_NSI_DFS_EN_OFFSET

#define NSI_CLK_REG_NSI_DFS_EN_OFFSET   28

◆ NSI_CLK_REG_NSI_DIV1_CLEAR_MASK

#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK   (0x0000001f)

◆ NSI_CLK_REG_NSI_DIV1_OFFSET

#define NSI_CLK_REG_NSI_DIV1_OFFSET   0

◆ NSI_CLK_REG_NSI_RST_ASSERT

#define NSI_CLK_REG_NSI_RST_ASSERT   0b0

◆ NSI_CLK_REG_NSI_RST_CLEAR_MASK

#define NSI_CLK_REG_NSI_RST_CLEAR_MASK   (0x40000000)

◆ NSI_CLK_REG_NSI_RST_DE_ASSERT

#define NSI_CLK_REG_NSI_RST_DE_ASSERT   0b1

◆ NSI_CLK_REG_NSI_RST_OFFSET

#define NSI_CLK_REG_NSI_RST_OFFSET   30

◆ NSI_CLK_REG_NSI_UPD_CLEAR_MASK

#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK   (0x08000000)

◆ NSI_CLK_REG_NSI_UPD_INVALID

#define NSI_CLK_REG_NSI_UPD_INVALID   0b0

◆ NSI_CLK_REG_NSI_UPD_OFFSET

#define NSI_CLK_REG_NSI_UPD_OFFSET   27

◆ NSI_CLK_REG_NSI_UPD_VALID

#define NSI_CLK_REG_NSI_UPD_VALID   0b1

◆ PCIE0_AUX_CLK_REG

#define PCIE0_AUX_CLK_REG   0x00001380

◆ PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x01000000)

◆ PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K   0b1

◆ PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PCIE0_AUX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b0

◆ PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET

#define PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET   0

◆ PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON   0b1

◆ PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET

#define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET   31

◆ PCIE0_AXI_SLV_CLK_REG

#define PCIE0_AXI_SLV_CLK_REG   0x00001384

◆ PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010

◆ PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define PCIE0_AXI_SLV_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b000

◆ PCIE0_AXI_SLV_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ PCIE0_AXI_SLV_CLK_REG_FACTOR_M_OFFSET

#define PCIE0_AXI_SLV_CLK_REG_FACTOR_M_OFFSET   0

◆ PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLEAR_MASK

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_OFF

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_ON

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_CLOCK_IS_ON   0b1

◆ PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_OFFSET

#define PCIE0_AXI_SLV_CLK_REG_PCIE0_AXI_SLV_CLK_GATING_OFFSET   31

◆ PCIE0_BGR_REG

#define PCIE0_BGR_REG   0x0000138c

◆ PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT   0b0

◆ PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK   (0x00010000)

◆ PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT   0b1

◆ PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET

#define PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET   16

◆ PCIE0_BGR_REG_PCIE0_RST_ASSERT

#define PCIE0_BGR_REG_PCIE0_RST_ASSERT   0b0

◆ PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK

#define PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK   (0x00020000)

◆ PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT

#define PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT   0b1

◆ PCIE0_BGR_REG_PCIE0_RST_OFFSET

#define PCIE0_BGR_REG_PCIE0_RST_OFFSET   17

◆ PERI0PLL_GATE_EN_REG

#define PERI0PLL_GATE_EN_REG   0x00001908

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   (0x00000008)

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   (0x00080000)

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   (0x00400000)

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000020)

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK   (0x80000000)

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET   31

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   (0x00200000)

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   (0x00100000)

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000004)

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   (0x00040000)

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000100)

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   (0x00000080)

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   (0x01000000)

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   (0x00800000)

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   (0x00000200)

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   (0x02000000)

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   (0x00000400)

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   (0x04000000)

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   (0x00000800)

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   (0x08000000)

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27

◆ PERI0PLL_GATE_STAT_REG

#define PERI0PLL_GATE_STAT_REG   0x00001988

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK   (0x00080000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET   19

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK   (0x00400000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET   22

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET   16

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK   (0x00200000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET   21

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK   (0x00100000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET   20

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK   (0x00040000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET   18

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET   17

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK   (0x01000000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET   24

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK   (0x00800000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET   23

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK   (0x02000000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET   25

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK   (0x04000000)

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET   26

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK   (0x08000000)

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE   0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE   0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET   27

◆ PERI1PLL_GATE_EN_REG

#define PERI1PLL_GATE_EN_REG   0x0000190c

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK   (0x00000008)

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET   3

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK   (0x00080000)

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET   19

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET   6

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK   (0x00400000)

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET   22

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET   0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET   16

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000020)

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET   4

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK   (0x80000000)

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET   31

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK   (0x00200000)

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET   21

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK   (0x00100000)

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET   20

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000004)

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET   1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK   (0x00040000)

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET   18

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET   17

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000100)

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK   (0x00000080)

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET   7

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK   (0x01000000)

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET   24

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK   (0x00800000)

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET   23

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK   (0x00000400)

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET   10

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK   (0x00000200)

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET   9

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK   (0x04000000)

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET   26

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK   (0x02000000)

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET   25

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK   (0x00000800)

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET   11

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK   (0x08000000)

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE   0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE   0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET   27

◆ PERI1PLL_GATE_STAT_REG

#define PERI1PLL_GATE_STAT_REG   0x0000198c

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK   (0x00080000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET   19

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK   (0x00400000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET   22

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET   16

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK   (0x00200000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET   21

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK   (0x00100000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET   20

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK   (0x00040000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET   18

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET   17

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK   (0x01000000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET   24

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK   (0x00800000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET   23

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK   (0x04000000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET   26

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK   (0x02000000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET   25

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK   (0x08000000)

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE   0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE   0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET   27

◆ PLL_AUDIO0_BIAS_REG

#define PLL_AUDIO0_BIAS_REG   0x00000270

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO0_CTRL_REG

#define PLL_AUDIO0_CTRL_REG   0x00000260

◆ PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x007f0000)

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   16

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO0_LOCK_CTRL_REG

#define PLL_AUDIO0_LOCK_CTRL_REG   0x00000264

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET   0

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET   4

◆ PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING

#define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING   0b1

◆ PLL_AUDIO0_PAT0_CTRL_REG

#define PLL_AUDIO0_PAT0_CTRL_REG   0x00000268

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO0_PAT1_CTRL_REG

#define PLL_AUDIO0_PAT1_CTRL_REG   0x0000026c

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_AUDIO1_BIAS_REG

#define PLL_AUDIO1_BIAS_REG   0x00000290

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO1_CTRL_REG

#define PLL_AUDIO1_CTRL_REG   0x00000280

◆ PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_AUDIO1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_P0_CLEAR_MASK   (0x00700000)

◆ PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_P0_OFFSET   20

◆ PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_P1_CLEAR_MASK   (0x00070000)

◆ PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_P1_OFFSET   16

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO1_LOCK_CTRL_REG

#define PLL_AUDIO1_LOCK_CTRL_REG   0x00000284

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_DISABLE

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_ENABLE

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_OFFSET

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_IRQEN_OFFSET   0

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_CLEAR_MASK

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_NO_EFFECT

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_OFFSET

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_OFFSET   4

◆ PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_PENDING

#define PLL_AUDIO1_LOCK_CTRL_REG_PLL_AUDIO1_UNLOCK_STAT_PENDING   0b1

◆ PLL_AUDIO1_PAT0_CTRL_REG

#define PLL_AUDIO1_PAT0_CTRL_REG   0x00000288

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO1_PAT1_CTRL_REG

#define PLL_AUDIO1_PAT1_CTRL_REG   0x0000028c

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_CFG0_REG

#define PLL_CFG0_REG   0x00001f20

◆ PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK

#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   (0xffffffff)

◆ PLL_CFG0_REG_PLL_CONFIG0_OFFSET

#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0

◆ PLL_CFG1_REG

#define PLL_CFG1_REG   0x00001f24

◆ PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK

#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   (0xffffffff)

◆ PLL_CFG1_REG_PLL_CONFIG1_OFFSET

#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0

◆ PLL_CFG2_REG

#define PLL_CFG2_REG   0x00001f28

◆ PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK

#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   (0xffffffff)

◆ PLL_CFG2_REG_PLL_CONFIG2_OFFSET

#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0

◆ PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_CPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_DDR_BIAS_REG

#define PLL_DDR_BIAS_REG   0x00000030

◆ PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_DDR_BIAS_REG_PLL_CP_OFFSET

#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_DDR_CTRL_REG

#define PLL_DDR_CTRL_REG   0x00000020

◆ PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_DDR_CTRL_REG_LOCK_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28

◆ PLL_DDR_CTRL_REG_LOCK_UNLOCKED

#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DDR_CTRL_REG_PLL_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_DDR_CTRL_REG_PLL_N_OFFSET

#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_DDR_LOCK_CTRL_REG

#define PLL_DDR_LOCK_CTRL_REG   0x00000024

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET   0

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET   4

◆ PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING

#define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING   0b1

◆ PLL_DDR_PAT0_CTRL_REG

#define PLL_DDR_PAT0_CTRL_REG   0x00000028

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG

#define PLL_DDR_PAT1_CTRL_REG   0x0000002c

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_DE_BIAS_REG

#define PLL_DE_BIAS_REG   0x000002f0

◆ PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_DE_BIAS_REG_PLL_CP_OFFSET

#define PLL_DE_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_DE_CTRL_REG

#define PLL_DE_CTRL_REG   0x000002e0

◆ PLL_DE_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_DE_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_DE_CTRL_REG_LOCK_OFFSET

#define PLL_DE_CTRL_REG_LOCK_OFFSET   28

◆ PLL_DE_CTRL_REG_LOCK_UNLOCKED

#define PLL_DE_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DE_CTRL_REG_PLL_EN_DISABLE

#define PLL_DE_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_DE_CTRL_REG_PLL_EN_ENABLE

#define PLL_DE_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_DE_CTRL_REG_PLL_EN_OFFSET

#define PLL_DE_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_DE_CTRL_REG_PLL_N_OFFSET

#define PLL_DE_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_DE_LOCK_CTRL_REG

#define PLL_DE_LOCK_CTRL_REG   0x000002e4

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET   0

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET   4

◆ PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING

#define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING   0b1

◆ PLL_DE_PAT0_CTRL_REG

#define PLL_DE_PAT0_CTRL_REG   0x000002e8

◆ PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_DE_PAT1_CTRL_REG

#define PLL_DE_PAT1_CTRL_REG   0x000002ec

◆ PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_GPU0_BIAS_REG

#define PLL_GPU0_BIAS_REG   0x000000f0

◆ PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_GPU0_BIAS_REG_PLL_CP_OFFSET

#define PLL_GPU0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_GPU0_CTRL_REG

#define PLL_GPU0_CTRL_REG   0x000000e0

◆ PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_GPU0_CTRL_REG_LOCK_OFFSET

#define PLL_GPU0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_GPU0_CTRL_REG_LOCK_UNLOCKED

#define PLL_GPU0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_GPU0_CTRL_REG_PLL_EN_DISABLE

#define PLL_GPU0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_GPU0_CTRL_REG_PLL_EN_ENABLE

#define PLL_GPU0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_GPU0_CTRL_REG_PLL_EN_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_GPU0_CTRL_REG_PLL_N_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_GPU0_LOCK_CTRL_REG

#define PLL_GPU0_LOCK_CTRL_REG   0x000000e4

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET   0

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET   4

◆ PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING

#define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING   0b1

◆ PLL_GPU0_PAT0_CTRL_REG

#define PLL_GPU0_PAT0_CTRL_REG   0x000000e8

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_GPU0_PAT1_CTRL_REG

#define PLL_GPU0_PAT1_CTRL_REG   0x000000ec

◆ PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_LOCK_DBG_CTRL_REG

#define PLL_LOCK_DBG_CTRL_REG   0x00001f2c

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   (0x80000000)

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0b0

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0b1

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL   0b0001011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL   0b0100000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   (0x07f00000)

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL   0b1000000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL   0b1000001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL   0b1000010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL   0b1000011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL   0b0000001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL   0b0001101

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL0

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL0   0b1100000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL1

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL1   0b1100001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL   0b0000100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_HDMIPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_HDMIPLL   0b1110000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL   0b0001100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL   0b0000010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL   0b0000011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL   0b0000000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL   0b0001001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL   0b0001010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL   0b0000101

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL   0b0000110

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL   0b0000111

◆ PLL_NPU_BIAS_REG

#define PLL_NPU_BIAS_REG   0x000002b0

◆ PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_NPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_NPU_CTRL_REG

#define PLL_NPU_CTRL_REG   0x000002a0

◆ PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_NPU_CTRL_REG_LOCK_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_NPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_NPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_NPU_CTRL_REG_PLL_N_OFFSET

#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_NPU_LOCK_CTRL_REG

#define PLL_NPU_LOCK_CTRL_REG   0x000002a4

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET   0

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET   4

◆ PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING

#define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING   0b1

◆ PLL_NPU_PAT0_CTRL_REG

#define PLL_NPU_PAT0_CTRL_REG   0x000002a8

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG

#define PLL_NPU_PAT1_CTRL_REG   0x000002ac

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_PERI0_BIAS_REG

#define PLL_PERI0_BIAS_REG   0x00000b0

◆ PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_PERI0_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI0_CTRL_REG

#define PLL_PERI0_CTRL_REG   0x000000a0

◆ PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_PERI0_CTRL_REG_LOCK_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI0_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI0_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_PERI0_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK   (0x0000001c)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET   2

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK   (0x02000000)

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE   0b0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE   0b1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET   25

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI0_LOCK_CTRL_REG

#define PLL_PERI0_LOCK_CTRL_REG   0x000000a4

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET   0

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET   4

◆ PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING

#define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING   0b1

◆ PLL_PERI0_PAT0_CTRL_REG

#define PLL_PERI0_PAT0_CTRL_REG   0x000000a8

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG

#define PLL_PERI0_PAT1_CTRL_REG   0x000000ac

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_PERI1_BIAS_REG

#define PLL_PERI1_BIAS_REG   0x000000d0

◆ PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_PERI1_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI1_CTRL_REG

#define PLL_PERI1_CTRL_REG   0x000000c0

◆ PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_PERI1_CTRL_REG_LOCK_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI1_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI1_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_PERI1_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK   (0x0000001c)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET   2

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK   (0x02000000)

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE   0b0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE   0b1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET   25

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI1_LOCK_CTRL_REG

#define PLL_PERI1_LOCK_CTRL_REG   0x000000c4

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET   0

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET   4

◆ PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING

#define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING   0b1

◆ PLL_PERI1_PAT0_CTRL_REG

#define PLL_PERI1_PAT0_CTRL_REG   0x000000c8

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG

#define PLL_PERI1_PAT1_CTRL_REG   0x000000cc

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_REF_BIAS_REG

#define PLL_REF_BIAS_REG   0x00000010

◆ PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_REF_BIAS_REG_PLL_CP_OFFSET

#define PLL_REF_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_REF_CTRL_REG

#define PLL_REF_CTRL_REG   0x00000000

◆ PLL_REF_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_REF_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_REF_CTRL_REG_LOCK_OFFSET

#define PLL_REF_CTRL_REG_LOCK_OFFSET   28

◆ PLL_REF_CTRL_REG_LOCK_UNLOCKED

#define PLL_REF_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_REF_CTRL_REG_PLL_EN_DISABLE

#define PLL_REF_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_REF_CTRL_REG_PLL_EN_ENABLE

#define PLL_REF_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_REF_CTRL_REG_PLL_EN_OFFSET

#define PLL_REF_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_REF_CTRL_REG_PLL_N_OFFSET

#define PLL_REF_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x007f0000)

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   16

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK   (0x01000000)

◆ PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE

#define PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE   0b0

◆ PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE

#define PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE   0b1

◆ PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET

#define PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET   24

◆ PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_REF_LOCK_CTRL_REG

#define PLL_REF_LOCK_CTRL_REG   0x00000004

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET   0

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET   4

◆ PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING

#define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING   0b1

◆ PLL_VE0_BIAS_REG

#define PLL_VE0_BIAS_REG   0x00000230

◆ PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_VE0_BIAS_REG_PLL_CP_OFFSET

#define PLL_VE0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VE0_CTRL_REG

#define PLL_VE0_CTRL_REG   0x00000220

◆ PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VE0_CTRL_REG_LOCK_OFFSET

#define PLL_VE0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VE0_CTRL_REG_LOCK_UNLOCKED

#define PLL_VE0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE0_CTRL_REG_PLL_EN_DISABLE

#define PLL_VE0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VE0_CTRL_REG_PLL_EN_ENABLE

#define PLL_VE0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VE0_CTRL_REG_PLL_EN_OFFSET

#define PLL_VE0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_VE0_CTRL_REG_PLL_N_OFFSET

#define PLL_VE0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VE0_LOCK_CTRL_REG

#define PLL_VE0_LOCK_CTRL_REG   0x00000224

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET   0

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET   4

◆ PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING

#define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING   0b1

◆ PLL_VE0_PAT0_CTRL_REG

#define PLL_VE0_PAT0_CTRL_REG   0x00000228

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VE0_PAT1_CTRL_REG

#define PLL_VE0_PAT1_CTRL_REG   0x0000022c

◆ PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_VE1_BIAS_REG

#define PLL_VE1_BIAS_REG   0x00000250

◆ PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_VE1_BIAS_REG_PLL_CP_OFFSET

#define PLL_VE1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VE1_CTRL_REG

#define PLL_VE1_CTRL_REG   0x00000240

◆ PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VE1_CTRL_REG_LOCK_OFFSET

#define PLL_VE1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VE1_CTRL_REG_LOCK_UNLOCKED

#define PLL_VE1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE1_CTRL_REG_PLL_EN_DISABLE

#define PLL_VE1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VE1_CTRL_REG_PLL_EN_ENABLE

#define PLL_VE1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VE1_CTRL_REG_PLL_EN_OFFSET

#define PLL_VE1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_VE1_CTRL_REG_PLL_N_OFFSET

#define PLL_VE1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET   20

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VE1_LOCK_CTRL_REG

#define PLL_VE1_LOCK_CTRL_REG   0x00000244

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET   0

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET   4

◆ PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING

#define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING   0b1

◆ PLL_VE1_PAT0_CTRL_REG

#define PLL_VE1_PAT0_CTRL_REG   0x00000248

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VE1_PAT1_CTRL_REG

#define PLL_VE1_PAT1_CTRL_REG   0x0000024c

◆ PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_VIDEO0_BIAS_REG

#define PLL_VIDEO0_BIAS_REG   0x00000130

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO0_CTRL_REG

#define PLL_VIDEO0_CTRL_REG   0x00000120

◆ PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO0_LOCK_CTRL_REG

#define PLL_VIDEO0_LOCK_CTRL_REG   0x00000124

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET   0

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET   4

◆ PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING

#define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING   0b1

◆ PLL_VIDEO0_PAT0_CTRL_REG

#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000128

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG

#define PLL_VIDEO0_PAT1_CTRL_REG   0x0000012c

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_VIDEO1_BIAS_REG

#define PLL_VIDEO1_BIAS_REG   0x00000150

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO1_CTRL_REG

#define PLL_VIDEO1_CTRL_REG   0x00000140

◆ PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO1_LOCK_CTRL_REG

#define PLL_VIDEO1_LOCK_CTRL_REG   0x00000144

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET   0

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET   4

◆ PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING

#define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING   0b1

◆ PLL_VIDEO1_PAT0_CTRL_REG

#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG

#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PLL_VIDEO2_BIAS_REG

#define PLL_VIDEO2_BIAS_REG   0x00000170

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   (0x001f0000)

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO2_CTRL_REG

#define PLL_VIDEO2_CTRL_REG   0x00000160

◆ PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   (0x10000000)

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   (0x20000000)

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET   24

◆ PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL

#define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK   (0x00000002)

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET   1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   (0x40000000)

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   (0x00000020)

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   (0x0000ff00)

◆ PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK   (0x00700000)

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET   20

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET   27

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK   (0x00070000)

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET   16

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE   0b0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE   0b1

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET   26

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   (0x000000c0)

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO2_LOCK_CTRL_REG

#define PLL_VIDEO2_LOCK_CTRL_REG   0x00000164

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK   (0x00000001)

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE   0b0

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE   0b1

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET   0

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK   (0x00000010)

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT   0b0

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET   4

◆ PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING

#define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING   0b1

◆ PLL_VIDEO2_PAT0_CTRL_REG

#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000168

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   (0x00060000)

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   (0x00080000)

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN   0b1

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET   19

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   (0x60000000)

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW   0b00

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b01

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT   0b10

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT   0b11

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   (0x1ff00000)

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG

#define PLL_VIDEO2_PAT1_CTRL_REG   0x0000016c

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   (0x01000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   (0x00100000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   (0x0001ffff)

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_16UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_16UA   0b001

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_24UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_24UA   0b010

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_32UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_32UA   0b011

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_40UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_40UA   0b100

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_48UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_48UA   0b101

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_56UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_56UA   0b110

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_64UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_64UA   0b111

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_8UA

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_8UA   0b000

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK   (0x70000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET   28

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK   (0x80000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE   0b0

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE   0b1

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET   31

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   (0x08000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET   27

◆ PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY   0b1

◆ PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK   (0x04000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY   0b0

◆ PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET   26

◆ PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK   (0x02000000)

◆ PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE   0b0

◆ PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE   0b1

◆ PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET   25

◆ PWM0_BGR_REG

#define PWM0_BGR_REG   0x00000784

◆ PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK

#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK   (0x00000001)

◆ PWM0_BGR_REG_PWM0_GATING_MASK

#define PWM0_BGR_REG_PWM0_GATING_MASK   0b0

◆ PWM0_BGR_REG_PWM0_GATING_OFFSET

#define PWM0_BGR_REG_PWM0_GATING_OFFSET   0

◆ PWM0_BGR_REG_PWM0_GATING_PASS

#define PWM0_BGR_REG_PWM0_GATING_PASS   0b1

◆ PWM0_BGR_REG_PWM0_RST_ASSERT

#define PWM0_BGR_REG_PWM0_RST_ASSERT   0b0

◆ PWM0_BGR_REG_PWM0_RST_CLEAR_MASK

#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK   (0x00010000)

◆ PWM0_BGR_REG_PWM0_RST_DE_ASSERT

#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT   0b1

◆ PWM0_BGR_REG_PWM0_RST_OFFSET

#define PWM0_BGR_REG_PWM0_RST_OFFSET   16

◆ PWM1_BGR_REG

#define PWM1_BGR_REG   0x0000078c

◆ PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK

#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK   (0x00000001)

◆ PWM1_BGR_REG_PWM1_GATING_MASK

#define PWM1_BGR_REG_PWM1_GATING_MASK   0b0

◆ PWM1_BGR_REG_PWM1_GATING_OFFSET

#define PWM1_BGR_REG_PWM1_GATING_OFFSET   0

◆ PWM1_BGR_REG_PWM1_GATING_PASS

#define PWM1_BGR_REG_PWM1_GATING_PASS   0b1

◆ PWM1_BGR_REG_PWM1_RST_ASSERT

#define PWM1_BGR_REG_PWM1_RST_ASSERT   0b0

◆ PWM1_BGR_REG_PWM1_RST_CLEAR_MASK

#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK   (0x00010000)

◆ PWM1_BGR_REG_PWM1_RST_DE_ASSERT

#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT   0b1

◆ PWM1_BGR_REG_PWM1_RST_OFFSET

#define PWM1_BGR_REG_PWM1_RST_OFFSET   16

◆ RESET_SHIFT

#define RESET_SHIFT   (16)

◆ RTC_LOSC_CTRL_REG

#define RTC_LOSC_CTRL_REG   (SUNXI_RTC_BASE)

◆ RTC_XO_CONTROL0_REG

#define RTC_XO_CONTROL0_REG   (SUNXI_RTC_BASE + XO_CONTROL0_REG)

◆ SERDES_BGR_REG

#define SERDES_BGR_REG   0x000013c4

◆ SERDES_BGR_REG_SERDES_RST_ASSERT

#define SERDES_BGR_REG_SERDES_RST_ASSERT   0b0

◆ SERDES_BGR_REG_SERDES_RST_CLEAR_MASK

#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK   (0x00010000)

◆ SERDES_BGR_REG_SERDES_RST_DE_ASSERT

#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT   0b1

◆ SERDES_BGR_REG_SERDES_RST_OFFSET

#define SERDES_BGR_REG_SERDES_RST_OFFSET   16

◆ SERDES_PHY_CFG_CLK_REG

#define SERDES_PHY_CFG_CLK_REG   0x000013c0

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b001

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET   0

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON   0b1

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET   31

◆ SGPIO_BGR_REG

#define SGPIO_BGR_REG   0x00001064

◆ SGPIO_BGR_REG_SGPIO_GATING_CLEAR_MASK

#define SGPIO_BGR_REG_SGPIO_GATING_CLEAR_MASK   (0x00000001)

◆ SGPIO_BGR_REG_SGPIO_GATING_MASK

#define SGPIO_BGR_REG_SGPIO_GATING_MASK   0b0

◆ SGPIO_BGR_REG_SGPIO_GATING_OFFSET

#define SGPIO_BGR_REG_SGPIO_GATING_OFFSET   0

◆ SGPIO_BGR_REG_SGPIO_GATING_PASS

#define SGPIO_BGR_REG_SGPIO_GATING_PASS   0b1

◆ SGPIO_BGR_REG_SGPIO_RST_ASSERT

#define SGPIO_BGR_REG_SGPIO_RST_ASSERT   0b0

◆ SGPIO_BGR_REG_SGPIO_RST_CLEAR_MASK

#define SGPIO_BGR_REG_SGPIO_RST_CLEAR_MASK   (0x00010000)

◆ SGPIO_BGR_REG_SGPIO_RST_DE_ASSERT

#define SGPIO_BGR_REG_SGPIO_RST_DE_ASSERT   0b1

◆ SGPIO_BGR_REG_SGPIO_RST_OFFSET

#define SGPIO_BGR_REG_SGPIO_RST_OFFSET   16

◆ SGPIO_CLK_REG

#define SGPIO_CLK_REG   0x00001060

◆ SGPIO_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SGPIO_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SGPIO_CLK_REG_CLK_SRC_SEL_CLK32K

#define SGPIO_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ SGPIO_CLK_REG_CLK_SRC_SEL_OFFSET

#define SGPIO_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SGPIO_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SGPIO_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SGPIO_CLK_REG_FACTOR_M_CLEAR_MASK

#define SGPIO_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SGPIO_CLK_REG_FACTOR_M_OFFSET

#define SGPIO_CLK_REG_FACTOR_M_OFFSET   0

◆ SGPIO_CLK_REG_SGPIO_CLK_GATING_CLEAR_MASK

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_OFF

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_ON

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_CLOCK_IS_ON   0b1

◆ SGPIO_CLK_REG_SGPIO_CLK_GATING_OFFSET

#define SGPIO_CLK_REG_SGPIO_CLK_GATING_OFFSET   31

◆ SMHC0_BGR_REG

#define SMHC0_BGR_REG   0x00000d0c

◆ SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK

#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK   (0x00000001)

◆ SMHC0_BGR_REG_SMHC0_GATING_MASK

#define SMHC0_BGR_REG_SMHC0_GATING_MASK   0b0

◆ SMHC0_BGR_REG_SMHC0_GATING_OFFSET

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET   0

◆ SMHC0_BGR_REG_SMHC0_GATING_PASS

#define SMHC0_BGR_REG_SMHC0_GATING_PASS   0b1

◆ SMHC0_BGR_REG_SMHC0_RST_ASSERT

#define SMHC0_BGR_REG_SMHC0_RST_ASSERT   0b0

◆ SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK

#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK   (0x00010000)

◆ SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT

#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT   0b1

◆ SMHC0_BGR_REG_SMHC0_RST_OFFSET

#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   16

◆ SMHC0_CLK_REG

#define SMHC0_CLK_REG   0x00000d00

◆ SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SMHC0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SMHC0_CLK_REG_FACTOR_M_OFFSET

#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SMHC0_CLK_REG_FACTOR_N_OFFSET

#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31

◆ SMHC1_BGR_REG

#define SMHC1_BGR_REG   0x00000d1c

◆ SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK

#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK   (0x00000001)

◆ SMHC1_BGR_REG_SMHC1_GATING_MASK

#define SMHC1_BGR_REG_SMHC1_GATING_MASK   0b0

◆ SMHC1_BGR_REG_SMHC1_GATING_OFFSET

#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET   0

◆ SMHC1_BGR_REG_SMHC1_GATING_PASS

#define SMHC1_BGR_REG_SMHC1_GATING_PASS   0b1

◆ SMHC1_BGR_REG_SMHC1_RST_ASSERT

#define SMHC1_BGR_REG_SMHC1_RST_ASSERT   0b0

◆ SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK

#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK   (0x00010000)

◆ SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT

#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT   0b1

◆ SMHC1_BGR_REG_SMHC1_RST_OFFSET

#define SMHC1_BGR_REG_SMHC1_RST_OFFSET   16

◆ SMHC1_CLK_REG

#define SMHC1_CLK_REG   0x00000d10

◆ SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ SMHC1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SMHC1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SMHC1_CLK_REG_FACTOR_M_OFFSET

#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SMHC1_CLK_REG_FACTOR_N_OFFSET

#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31

◆ SMHC2_BGR_REG

#define SMHC2_BGR_REG   0x00000d2c

◆ SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK

#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK   (0x00000001)

◆ SMHC2_BGR_REG_SMHC2_GATING_MASK

#define SMHC2_BGR_REG_SMHC2_GATING_MASK   0b0

◆ SMHC2_BGR_REG_SMHC2_GATING_OFFSET

#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET   0

◆ SMHC2_BGR_REG_SMHC2_GATING_PASS

#define SMHC2_BGR_REG_SMHC2_GATING_PASS   0b1

◆ SMHC2_BGR_REG_SMHC2_RST_ASSERT

#define SMHC2_BGR_REG_SMHC2_RST_ASSERT   0b0

◆ SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK

#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK   (0x00010000)

◆ SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT

#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT   0b1

◆ SMHC2_BGR_REG_SMHC2_RST_OFFSET

#define SMHC2_BGR_REG_SMHC2_RST_OFFSET   16

◆ SMHC2_CLK_REG

#define SMHC2_CLK_REG   0x00000d20

◆ SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011

◆ SMHC2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SMHC2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SMHC2_CLK_REG_FACTOR_M_OFFSET

#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SMHC2_CLK_REG_FACTOR_N_OFFSET

#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31

◆ SMHC3_BGR_REG

#define SMHC3_BGR_REG   0x00000d3c

◆ SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK

#define SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK   (0x00000001)

◆ SMHC3_BGR_REG_SMHC3_GATING_MASK

#define SMHC3_BGR_REG_SMHC3_GATING_MASK   0b0

◆ SMHC3_BGR_REG_SMHC3_GATING_OFFSET

#define SMHC3_BGR_REG_SMHC3_GATING_OFFSET   0

◆ SMHC3_BGR_REG_SMHC3_GATING_PASS

#define SMHC3_BGR_REG_SMHC3_GATING_PASS   0b1

◆ SMHC3_BGR_REG_SMHC3_RST_ASSERT

#define SMHC3_BGR_REG_SMHC3_RST_ASSERT   0b0

◆ SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK

#define SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK   (0x00010000)

◆ SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT

#define SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT   0b1

◆ SMHC3_BGR_REG_SMHC3_RST_OFFSET

#define SMHC3_BGR_REG_SMHC3_RST_OFFSET   16

◆ SMHC3_CLK_REG

#define SMHC3_CLK_REG   0x00000d30

◆ SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b010

◆ SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b001

◆ SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M   0b100

◆ SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M

#define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M   0b011

◆ SMHC3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SMHC3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SMHC3_CLK_REG_FACTOR_M_OFFSET

#define SMHC3_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SMHC3_CLK_REG_FACTOR_N_OFFSET

#define SMHC3_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET

#define SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET   31

◆ SPDIF_BGR_REG

#define SPDIF_BGR_REG   0x0000128c

◆ SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK

#define SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK   (0x00000001)

◆ SPDIF_BGR_REG_SPDIF_GATING_MASK

#define SPDIF_BGR_REG_SPDIF_GATING_MASK   0b0

◆ SPDIF_BGR_REG_SPDIF_GATING_OFFSET

#define SPDIF_BGR_REG_SPDIF_GATING_OFFSET   0

◆ SPDIF_BGR_REG_SPDIF_GATING_PASS

#define SPDIF_BGR_REG_SPDIF_GATING_PASS   0b1

◆ SPDIF_BGR_REG_SPDIF_RST_ASSERT

#define SPDIF_BGR_REG_SPDIF_RST_ASSERT   0b0

◆ SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK

#define SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK   (0x00010000)

◆ SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT

#define SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT   0b1

◆ SPDIF_BGR_REG_SPDIF_RST_OFFSET

#define SPDIF_BGR_REG_SPDIF_RST_OFFSET   16

◆ SPDIF_RX_CLK_REG

#define SPDIF_RX_CLK_REG   0x00001284

◆ SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b000

◆ SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b010

◆ SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPDIF_RX_CLK_REG_FACTOR_M_OFFSET

#define SPDIF_RX_CLK_REG_FACTOR_M_OFFSET   0

◆ SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET

#define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET   31

◆ SPDIF_TX_CLK_REG

#define SPDIF_TX_CLK_REG   0x00001280

◆ SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X   0b000

◆ SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV2   0b001

◆ SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL_DIV5   0b010

◆ SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPDIF_TX_CLK_REG_FACTOR_M_OFFSET

#define SPDIF_TX_CLK_REG_FACTOR_M_OFFSET   0

◆ SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET

#define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET   31

◆ SPI0_BGR_REG

#define SPI0_BGR_REG   0x00000f04

◆ SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK

#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK   (0x00000001)

◆ SPI0_BGR_REG_SPI0_GATING_MASK

#define SPI0_BGR_REG_SPI0_GATING_MASK   0b0

◆ SPI0_BGR_REG_SPI0_GATING_OFFSET

#define SPI0_BGR_REG_SPI0_GATING_OFFSET   0

◆ SPI0_BGR_REG_SPI0_GATING_PASS

#define SPI0_BGR_REG_SPI0_GATING_PASS   0b1

◆ SPI0_BGR_REG_SPI0_RST_ASSERT

#define SPI0_BGR_REG_SPI0_RST_ASSERT   0b0

◆ SPI0_BGR_REG_SPI0_RST_CLEAR_MASK

#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK   (0x00010000)

◆ SPI0_BGR_REG_SPI0_RST_DE_ASSERT

#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT   0b1

◆ SPI0_BGR_REG_SPI0_RST_OFFSET

#define SPI0_BGR_REG_SPI0_RST_OFFSET   16

◆ SPI0_CLK_REG

#define SPI0_CLK_REG   0x00000f00

◆ SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPI0_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110

◆ SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPI0_CLK_REG_FACTOR_M_OFFSET

#define SPI0_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPI0_CLK_REG_FACTOR_N_OFFSET

#define SPI0_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31

◆ SPI1_BGR_REG

#define SPI1_BGR_REG   0x00000f0c

◆ SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK

#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK   (0x00000001)

◆ SPI1_BGR_REG_SPI1_GATING_MASK

#define SPI1_BGR_REG_SPI1_GATING_MASK   0b0

◆ SPI1_BGR_REG_SPI1_GATING_OFFSET

#define SPI1_BGR_REG_SPI1_GATING_OFFSET   0

◆ SPI1_BGR_REG_SPI1_GATING_PASS

#define SPI1_BGR_REG_SPI1_GATING_PASS   0b1

◆ SPI1_BGR_REG_SPI1_RST_ASSERT

#define SPI1_BGR_REG_SPI1_RST_ASSERT   0b0

◆ SPI1_BGR_REG_SPI1_RST_CLEAR_MASK

#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK   (0x00010000)

◆ SPI1_BGR_REG_SPI1_RST_DE_ASSERT

#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT   0b1

◆ SPI1_BGR_REG_SPI1_RST_OFFSET

#define SPI1_BGR_REG_SPI1_RST_OFFSET   16

◆ SPI1_CLK_REG

#define SPI1_CLK_REG   0x00000f08

◆ SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPI1_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110

◆ SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPI1_CLK_REG_FACTOR_M_OFFSET

#define SPI1_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPI1_CLK_REG_FACTOR_N_OFFSET

#define SPI1_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31

◆ SPI2_BGR_REG

#define SPI2_BGR_REG   0x00000f14

◆ SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK

#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK   (0x00000001)

◆ SPI2_BGR_REG_SPI2_GATING_MASK

#define SPI2_BGR_REG_SPI2_GATING_MASK   0b0

◆ SPI2_BGR_REG_SPI2_GATING_OFFSET

#define SPI2_BGR_REG_SPI2_GATING_OFFSET   0

◆ SPI2_BGR_REG_SPI2_GATING_PASS

#define SPI2_BGR_REG_SPI2_GATING_PASS   0b1

◆ SPI2_BGR_REG_SPI2_RST_ASSERT

#define SPI2_BGR_REG_SPI2_RST_ASSERT   0b0

◆ SPI2_BGR_REG_SPI2_RST_CLEAR_MASK

#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK   (0x00010000)

◆ SPI2_BGR_REG_SPI2_RST_DE_ASSERT

#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT   0b1

◆ SPI2_BGR_REG_SPI2_RST_OFFSET

#define SPI2_BGR_REG_SPI2_RST_OFFSET   16

◆ SPI2_CLK_REG

#define SPI2_CLK_REG   0x00000f10

◆ SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPI2_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPI2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110

◆ SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPI2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPI2_CLK_REG_FACTOR_M_OFFSET

#define SPI2_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPI2_CLK_REG_FACTOR_N_OFFSET

#define SPI2_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31

◆ SPI3_BGR_REG

#define SPI3_BGR_REG   0x00000f24

◆ SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK

#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK   (0x00000001)

◆ SPI3_BGR_REG_SPI3_GATING_MASK

#define SPI3_BGR_REG_SPI3_GATING_MASK   0b0

◆ SPI3_BGR_REG_SPI3_GATING_OFFSET

#define SPI3_BGR_REG_SPI3_GATING_OFFSET   0

◆ SPI3_BGR_REG_SPI3_GATING_PASS

#define SPI3_BGR_REG_SPI3_GATING_PASS   0b1

◆ SPI3_BGR_REG_SPI3_RST_ASSERT

#define SPI3_BGR_REG_SPI3_RST_ASSERT   0b0

◆ SPI3_BGR_REG_SPI3_RST_CLEAR_MASK

#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK   (0x00010000)

◆ SPI3_BGR_REG_SPI3_RST_DE_ASSERT

#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT   0b1

◆ SPI3_BGR_REG_SPI3_RST_OFFSET

#define SPI3_BGR_REG_SPI3_RST_OFFSET   16

◆ SPI3_CLK_REG

#define SPI3_CLK_REG   0x00000f20

◆ SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPI3_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPI3_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110

◆ SPI3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPI3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPI3_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPI3_CLK_REG_FACTOR_M_OFFSET

#define SPI3_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI3_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPI3_CLK_REG_FACTOR_N_OFFSET

#define SPI3_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET

#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET   31

◆ SPI4_BGR_REG

#define SPI4_BGR_REG   0x00000f2c

◆ SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK

#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK   (0x00000001)

◆ SPI4_BGR_REG_SPI4_GATING_MASK

#define SPI4_BGR_REG_SPI4_GATING_MASK   0b0

◆ SPI4_BGR_REG_SPI4_GATING_OFFSET

#define SPI4_BGR_REG_SPI4_GATING_OFFSET   0

◆ SPI4_BGR_REG_SPI4_GATING_PASS

#define SPI4_BGR_REG_SPI4_GATING_PASS   0b1

◆ SPI4_BGR_REG_SPI4_RST_ASSERT

#define SPI4_BGR_REG_SPI4_RST_ASSERT   0b0

◆ SPI4_BGR_REG_SPI4_RST_CLEAR_MASK

#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK   (0x00010000)

◆ SPI4_BGR_REG_SPI4_RST_DE_ASSERT

#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT   0b1

◆ SPI4_BGR_REG_SPI4_RST_OFFSET

#define SPI4_BGR_REG_SPI4_RST_OFFSET   16

◆ SPI4_CLK_REG

#define SPI4_CLK_REG   0x00000f28

◆ SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPI4_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPI4_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b010

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b101

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M   0b100

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b011

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M   0b110

◆ SPI4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPI4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPI4_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPI4_CLK_REG_FACTOR_M_OFFSET

#define SPI4_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI4_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPI4_CLK_REG_FACTOR_N_OFFSET

#define SPI4_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET

#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET   31

◆ SPIF_BGR_REG

#define SPIF_BGR_REG   0x00000f1c

◆ SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK

#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK   (0x00000001)

◆ SPIF_BGR_REG_SPIF_GATING_MASK

#define SPIF_BGR_REG_SPIF_GATING_MASK   0b0

◆ SPIF_BGR_REG_SPIF_GATING_OFFSET

#define SPIF_BGR_REG_SPIF_GATING_OFFSET   0

◆ SPIF_BGR_REG_SPIF_GATING_PASS

#define SPIF_BGR_REG_SPIF_GATING_PASS   0b1

◆ SPIF_BGR_REG_SPIF_RST_ASSERT

#define SPIF_BGR_REG_SPIF_RST_ASSERT   0b0

◆ SPIF_BGR_REG_SPIF_RST_CLEAR_MASK

#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK   (0x00010000)

◆ SPIF_BGR_REG_SPIF_RST_DE_ASSERT

#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT   0b1

◆ SPIF_BGR_REG_SPIF_RST_OFFSET

#define SPIF_BGR_REG_SPIF_RST_OFFSET   16

◆ SPIF_CLK_REG

#define SPIF_CLK_REG   0x00000f18

◆ SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ SPIF_CLK_REG_CLK_SRC_SEL_HOSC

#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0b111

◆ SPIF_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M   0b101

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b010

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b001

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M   0b110

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M   0b100

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M   0b011

◆ SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ SPIF_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ SPIF_CLK_REG_FACTOR_M_OFFSET

#define SPIF_CLK_REG_FACTOR_M_OFFSET   0

◆ SPIF_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   (0x00001f00)

◆ SPIF_CLK_REG_FACTOR_N_OFFSET

#define SPIF_CLK_REG_FACTOR_N_OFFSET   8

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET

#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31

◆ SPINLOCK_BGR_REG

#define SPINLOCK_BGR_REG   0x00000724

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   (0x00000001)

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   (0x00010000)

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16

◆ SUNXI_MEMC_CLK_RST

#define SUNXI_MEMC_CLK_RST   (SUNXI_MEMC_COMMON_BASE + 0x10)

◆ SYSDAP_BGR_REG

#define SYSDAP_BGR_REG   0x000007ac

◆ SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK   (0x00000001)

◆ SYSDAP_BGR_REG_SYSDAP_GATING_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK   0b0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET   0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG

#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG   0b1

◆ SYSDAP_BGR_REG_SYSDAP_RST_ASSERT

#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT   0b0

◆ SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK   (0x00010000)

◆ SYSDAP_BGR_REG_SYSDAP_RST_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET   16

◆ SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG

#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG   0b1

◆ SYSDAP_REQ_CTRL_REG

#define SYSDAP_REQ_CTRL_REG   0x00001f10

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK   (0x00000001)

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET   0

◆ TCONTV0_BGR_REG

#define TCONTV0_BGR_REG   0x00001604

◆ TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK

#define TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK   (0x00000001)

◆ TCONTV0_BGR_REG_TCONTV0_GATING_MASK

#define TCONTV0_BGR_REG_TCONTV0_GATING_MASK   0b0

◆ TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET

#define TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET   0

◆ TCONTV0_BGR_REG_TCONTV0_GATING_PASS

#define TCONTV0_BGR_REG_TCONTV0_GATING_PASS   0b1

◆ TCONTV0_BGR_REG_TCONTV0_RST_ASSERT

#define TCONTV0_BGR_REG_TCONTV0_RST_ASSERT   0b0

◆ TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK

#define TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK   (0x00010000)

◆ TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT

#define TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT   0b1

◆ TCONTV0_BGR_REG_TCONTV0_RST_OFFSET

#define TCONTV0_BGR_REG_TCONTV0_RST_OFFSET   16

◆ TCONTV1_BGR_REG

#define TCONTV1_BGR_REG   0x0000160c

◆ TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK

#define TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK   (0x00000001)

◆ TCONTV1_BGR_REG_TCONTV1_GATING_MASK

#define TCONTV1_BGR_REG_TCONTV1_GATING_MASK   0b0

◆ TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET

#define TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET   0

◆ TCONTV1_BGR_REG_TCONTV1_GATING_PASS

#define TCONTV1_BGR_REG_TCONTV1_GATING_PASS   0b1

◆ TCONTV1_BGR_REG_TCONTV1_RST_ASSERT

#define TCONTV1_BGR_REG_TCONTV1_RST_ASSERT   0b0

◆ TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK

#define TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK   (0x00010000)

◆ TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT

#define TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT   0b1

◆ TCONTV1_BGR_REG_TCONTV1_RST_OFFSET

#define TCONTV1_BGR_REG_TCONTV1_RST_OFFSET   16

◆ THS0_BGR_REG

#define THS0_BGR_REG   0x00000fe4

◆ THS0_BGR_REG_THS0_GATING_CLEAR_MASK

#define THS0_BGR_REG_THS0_GATING_CLEAR_MASK   (0x00000001)

◆ THS0_BGR_REG_THS0_GATING_MASK

#define THS0_BGR_REG_THS0_GATING_MASK   0b0

◆ THS0_BGR_REG_THS0_GATING_OFFSET

#define THS0_BGR_REG_THS0_GATING_OFFSET   0

◆ THS0_BGR_REG_THS0_GATING_PASS

#define THS0_BGR_REG_THS0_GATING_PASS   0b1

◆ THS0_BGR_REG_THS0_RST_ASSERT

#define THS0_BGR_REG_THS0_RST_ASSERT   0b0

◆ THS0_BGR_REG_THS0_RST_CLEAR_MASK

#define THS0_BGR_REG_THS0_RST_CLEAR_MASK   (0x00010000)

◆ THS0_BGR_REG_THS0_RST_DE_ASSERT

#define THS0_BGR_REG_THS0_RST_DE_ASSERT   0b1

◆ THS0_BGR_REG_THS0_RST_OFFSET

#define THS0_BGR_REG_THS0_RST_OFFSET   16

◆ TIMER0_BGR_REG

#define TIMER0_BGR_REG   0x00000850

◆ TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK

#define TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK   (0x00000001)

◆ TIMER0_BGR_REG_TIMER0_GATING_MASK

#define TIMER0_BGR_REG_TIMER0_GATING_MASK   0b0

◆ TIMER0_BGR_REG_TIMER0_GATING_OFFSET

#define TIMER0_BGR_REG_TIMER0_GATING_OFFSET   0

◆ TIMER0_BGR_REG_TIMER0_GATING_PASS

#define TIMER0_BGR_REG_TIMER0_GATING_PASS   0b1

◆ TIMER0_BGR_REG_TIMER0_RST_ASSERT

#define TIMER0_BGR_REG_TIMER0_RST_ASSERT   0b0

◆ TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK

#define TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK   (0x00010000)

◆ TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT

#define TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT   0b1

◆ TIMER0_BGR_REG_TIMER0_RST_OFFSET

#define TIMER0_BGR_REG_TIMER0_RST_OFFSET   16

◆ TIMER0_CLK0_CLK_REG

#define TIMER0_CLK0_CLK_REG   0x00000800

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__1

#define TIMER0_CLK0_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__128

#define TIMER0_CLK0_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__16

#define TIMER0_CLK0_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__2

#define TIMER0_CLK0_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__32

#define TIMER0_CLK0_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__4

#define TIMER0_CLK0_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__64

#define TIMER0_CLK0_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK0_CLK_REG_FACTOR_P__8

#define TIMER0_CLK0_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET

#define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET   31

◆ TIMER0_CLK1_CLK_REG

#define TIMER0_CLK1_CLK_REG   0x00000804

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__1

#define TIMER0_CLK1_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__128

#define TIMER0_CLK1_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__16

#define TIMER0_CLK1_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__2

#define TIMER0_CLK1_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__32

#define TIMER0_CLK1_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__4

#define TIMER0_CLK1_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__64

#define TIMER0_CLK1_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK1_CLK_REG_FACTOR_P__8

#define TIMER0_CLK1_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET

#define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET   31

◆ TIMER0_CLK2_CLK_REG

#define TIMER0_CLK2_CLK_REG   0x00000808

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__1

#define TIMER0_CLK2_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__128

#define TIMER0_CLK2_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__16

#define TIMER0_CLK2_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__2

#define TIMER0_CLK2_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__32

#define TIMER0_CLK2_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__4

#define TIMER0_CLK2_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__64

#define TIMER0_CLK2_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK2_CLK_REG_FACTOR_P__8

#define TIMER0_CLK2_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET

#define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET   31

◆ TIMER0_CLK3_CLK_REG

#define TIMER0_CLK3_CLK_REG   0x0000080c

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__1

#define TIMER0_CLK3_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__128

#define TIMER0_CLK3_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__16

#define TIMER0_CLK3_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__2

#define TIMER0_CLK3_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__32

#define TIMER0_CLK3_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__4

#define TIMER0_CLK3_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__64

#define TIMER0_CLK3_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK3_CLK_REG_FACTOR_P__8

#define TIMER0_CLK3_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET

#define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET   31

◆ TIMER0_CLK4_CLK_REG

#define TIMER0_CLK4_CLK_REG   0x00000810

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__1

#define TIMER0_CLK4_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__128

#define TIMER0_CLK4_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__16

#define TIMER0_CLK4_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__2

#define TIMER0_CLK4_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__32

#define TIMER0_CLK4_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__4

#define TIMER0_CLK4_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__64

#define TIMER0_CLK4_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK4_CLK_REG_FACTOR_P__8

#define TIMER0_CLK4_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET

#define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET   31

◆ TIMER0_CLK5_CLK_REG

#define TIMER0_CLK5_CLK_REG   0x00000814

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__1

#define TIMER0_CLK5_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__128

#define TIMER0_CLK5_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__16

#define TIMER0_CLK5_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__2

#define TIMER0_CLK5_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__32

#define TIMER0_CLK5_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__4

#define TIMER0_CLK5_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__64

#define TIMER0_CLK5_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK5_CLK_REG_FACTOR_P__8

#define TIMER0_CLK5_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET

#define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET   31

◆ TIMER0_CLK6_CLK_REG

#define TIMER0_CLK6_CLK_REG   0x00000818

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__1

#define TIMER0_CLK6_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__128

#define TIMER0_CLK6_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__16

#define TIMER0_CLK6_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__2

#define TIMER0_CLK6_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__32

#define TIMER0_CLK6_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__4

#define TIMER0_CLK6_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__64

#define TIMER0_CLK6_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK6_CLK_REG_FACTOR_P__8

#define TIMER0_CLK6_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET

#define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET   31

◆ TIMER0_CLK7_CLK_REG

#define TIMER0_CLK7_CLK_REG   0x0000081c

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__1

#define TIMER0_CLK7_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__128

#define TIMER0_CLK7_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__16

#define TIMER0_CLK7_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__2

#define TIMER0_CLK7_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__32

#define TIMER0_CLK7_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__4

#define TIMER0_CLK7_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__64

#define TIMER0_CLK7_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK7_CLK_REG_FACTOR_P__8

#define TIMER0_CLK7_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET

#define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET   31

◆ TIMER0_CLK8_CLK_REG

#define TIMER0_CLK8_CLK_REG   0x00000820

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__1

#define TIMER0_CLK8_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__128

#define TIMER0_CLK8_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__16

#define TIMER0_CLK8_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__2

#define TIMER0_CLK8_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__32

#define TIMER0_CLK8_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__4

#define TIMER0_CLK8_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__64

#define TIMER0_CLK8_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK8_CLK_REG_FACTOR_P__8

#define TIMER0_CLK8_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET

#define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET   31

◆ TIMER0_CLK9_CLK_REG

#define TIMER0_CLK9_CLK_REG   0x00000824

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b001

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K   0b010

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC   0b100

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b011

◆ TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__1

#define TIMER0_CLK9_CLK_REG_FACTOR_P__1   0b000

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__128

#define TIMER0_CLK9_CLK_REG_FACTOR_P__128   0b111

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__16

#define TIMER0_CLK9_CLK_REG_FACTOR_P__16   0b100

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__2

#define TIMER0_CLK9_CLK_REG_FACTOR_P__2   0b001

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__32

#define TIMER0_CLK9_CLK_REG_FACTOR_P__32   0b101

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__4

#define TIMER0_CLK9_CLK_REG_FACTOR_P__4   0b010

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__64

#define TIMER0_CLK9_CLK_REG_FACTOR_P__64   0b110

◆ TIMER0_CLK9_CLK_REG_FACTOR_P__8

#define TIMER0_CLK9_CLK_REG_FACTOR_P__8   0b011

◆ TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK

#define TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK   (0x00000007)

◆ TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET

#define TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET   0

◆ TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE   0b0

◆ TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE   0b1

◆ TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET

#define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET   31

◆ TRACE_CLK_REG

#define TRACE_CLK_REG   0x00000540

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK32K

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ TRACE_CLK_REG_CLK_SRC_SEL_OFFSET

#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b011

◆ TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b100

◆ TRACE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define TRACE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ TRACE_CLK_REG_FACTOR_M_CLEAR_MASK

#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ TRACE_CLK_REG_FACTOR_M_OFFSET

#define TRACE_CLK_REG_FACTOR_M_OFFSET   0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON   0b1

◆ TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET

#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET   31

◆ TWI0_BGR_REG

#define TWI0_BGR_REG   0x00000e80

◆ TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK

#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK   (0x00000001)

◆ TWI0_BGR_REG_TWI0_GATING_MASK

#define TWI0_BGR_REG_TWI0_GATING_MASK   0b0

◆ TWI0_BGR_REG_TWI0_GATING_OFFSET

#define TWI0_BGR_REG_TWI0_GATING_OFFSET   0

◆ TWI0_BGR_REG_TWI0_GATING_PASS

#define TWI0_BGR_REG_TWI0_GATING_PASS   0b1

◆ TWI0_BGR_REG_TWI0_RST_ASSERT

#define TWI0_BGR_REG_TWI0_RST_ASSERT   0b0

◆ TWI0_BGR_REG_TWI0_RST_CLEAR_MASK

#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK   (0x00010000)

◆ TWI0_BGR_REG_TWI0_RST_DE_ASSERT

#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT   0b1

◆ TWI0_BGR_REG_TWI0_RST_OFFSET

#define TWI0_BGR_REG_TWI0_RST_OFFSET   16

◆ TWI10_BGR_REG

#define TWI10_BGR_REG   0x00000ea8

◆ TWI10_BGR_REG_TWI10_GATING_CLEAR_MASK

#define TWI10_BGR_REG_TWI10_GATING_CLEAR_MASK   (0x00000001)

◆ TWI10_BGR_REG_TWI10_GATING_MASK

#define TWI10_BGR_REG_TWI10_GATING_MASK   0b0

◆ TWI10_BGR_REG_TWI10_GATING_OFFSET

#define TWI10_BGR_REG_TWI10_GATING_OFFSET   0

◆ TWI10_BGR_REG_TWI10_GATING_PASS

#define TWI10_BGR_REG_TWI10_GATING_PASS   0b1

◆ TWI10_BGR_REG_TWI10_RST_ASSERT

#define TWI10_BGR_REG_TWI10_RST_ASSERT   0b0

◆ TWI10_BGR_REG_TWI10_RST_CLEAR_MASK

#define TWI10_BGR_REG_TWI10_RST_CLEAR_MASK   (0x00010000)

◆ TWI10_BGR_REG_TWI10_RST_DE_ASSERT

#define TWI10_BGR_REG_TWI10_RST_DE_ASSERT   0b1

◆ TWI10_BGR_REG_TWI10_RST_OFFSET

#define TWI10_BGR_REG_TWI10_RST_OFFSET   16

◆ TWI11_BGR_REG

#define TWI11_BGR_REG   0x00000eac

◆ TWI11_BGR_REG_TWI11_GATING_CLEAR_MASK

#define TWI11_BGR_REG_TWI11_GATING_CLEAR_MASK   (0x00000001)

◆ TWI11_BGR_REG_TWI11_GATING_MASK

#define TWI11_BGR_REG_TWI11_GATING_MASK   0b0

◆ TWI11_BGR_REG_TWI11_GATING_OFFSET

#define TWI11_BGR_REG_TWI11_GATING_OFFSET   0

◆ TWI11_BGR_REG_TWI11_GATING_PASS

#define TWI11_BGR_REG_TWI11_GATING_PASS   0b1

◆ TWI11_BGR_REG_TWI11_RST_ASSERT

#define TWI11_BGR_REG_TWI11_RST_ASSERT   0b0

◆ TWI11_BGR_REG_TWI11_RST_CLEAR_MASK

#define TWI11_BGR_REG_TWI11_RST_CLEAR_MASK   (0x00010000)

◆ TWI11_BGR_REG_TWI11_RST_DE_ASSERT

#define TWI11_BGR_REG_TWI11_RST_DE_ASSERT   0b1

◆ TWI11_BGR_REG_TWI11_RST_OFFSET

#define TWI11_BGR_REG_TWI11_RST_OFFSET   16

◆ TWI12_BGR_REG

#define TWI12_BGR_REG   0x00000eb0

◆ TWI12_BGR_REG_TWI12_GATING_CLEAR_MASK

#define TWI12_BGR_REG_TWI12_GATING_CLEAR_MASK   (0x00000001)

◆ TWI12_BGR_REG_TWI12_GATING_MASK

#define TWI12_BGR_REG_TWI12_GATING_MASK   0b0

◆ TWI12_BGR_REG_TWI12_GATING_OFFSET

#define TWI12_BGR_REG_TWI12_GATING_OFFSET   0

◆ TWI12_BGR_REG_TWI12_GATING_PASS

#define TWI12_BGR_REG_TWI12_GATING_PASS   0b1

◆ TWI12_BGR_REG_TWI12_RST_ASSERT

#define TWI12_BGR_REG_TWI12_RST_ASSERT   0b0

◆ TWI12_BGR_REG_TWI12_RST_CLEAR_MASK

#define TWI12_BGR_REG_TWI12_RST_CLEAR_MASK   (0x00010000)

◆ TWI12_BGR_REG_TWI12_RST_DE_ASSERT

#define TWI12_BGR_REG_TWI12_RST_DE_ASSERT   0b1

◆ TWI12_BGR_REG_TWI12_RST_OFFSET

#define TWI12_BGR_REG_TWI12_RST_OFFSET   16

◆ TWI1_BGR_REG

#define TWI1_BGR_REG   0x00000e84

◆ TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK

#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK   (0x00000001)

◆ TWI1_BGR_REG_TWI1_GATING_MASK

#define TWI1_BGR_REG_TWI1_GATING_MASK   0b0

◆ TWI1_BGR_REG_TWI1_GATING_OFFSET

#define TWI1_BGR_REG_TWI1_GATING_OFFSET   0

◆ TWI1_BGR_REG_TWI1_GATING_PASS

#define TWI1_BGR_REG_TWI1_GATING_PASS   0b1

◆ TWI1_BGR_REG_TWI1_RST_ASSERT

#define TWI1_BGR_REG_TWI1_RST_ASSERT   0b0

◆ TWI1_BGR_REG_TWI1_RST_CLEAR_MASK

#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK   (0x00010000)

◆ TWI1_BGR_REG_TWI1_RST_DE_ASSERT

#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT   0b1

◆ TWI1_BGR_REG_TWI1_RST_OFFSET

#define TWI1_BGR_REG_TWI1_RST_OFFSET   16

◆ TWI2_BGR_REG

#define TWI2_BGR_REG   0x00000e88

◆ TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK

#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK   (0x00000001)

◆ TWI2_BGR_REG_TWI2_GATING_MASK

#define TWI2_BGR_REG_TWI2_GATING_MASK   0b0

◆ TWI2_BGR_REG_TWI2_GATING_OFFSET

#define TWI2_BGR_REG_TWI2_GATING_OFFSET   0

◆ TWI2_BGR_REG_TWI2_GATING_PASS

#define TWI2_BGR_REG_TWI2_GATING_PASS   0b1

◆ TWI2_BGR_REG_TWI2_RST_ASSERT

#define TWI2_BGR_REG_TWI2_RST_ASSERT   0b0

◆ TWI2_BGR_REG_TWI2_RST_CLEAR_MASK

#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK   (0x00010000)

◆ TWI2_BGR_REG_TWI2_RST_DE_ASSERT

#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT   0b1

◆ TWI2_BGR_REG_TWI2_RST_OFFSET

#define TWI2_BGR_REG_TWI2_RST_OFFSET   16

◆ TWI3_BGR_REG

#define TWI3_BGR_REG   0x00000e8c

◆ TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK

#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK   (0x00000001)

◆ TWI3_BGR_REG_TWI3_GATING_MASK

#define TWI3_BGR_REG_TWI3_GATING_MASK   0b0

◆ TWI3_BGR_REG_TWI3_GATING_OFFSET

#define TWI3_BGR_REG_TWI3_GATING_OFFSET   0

◆ TWI3_BGR_REG_TWI3_GATING_PASS

#define TWI3_BGR_REG_TWI3_GATING_PASS   0b1

◆ TWI3_BGR_REG_TWI3_RST_ASSERT

#define TWI3_BGR_REG_TWI3_RST_ASSERT   0b0

◆ TWI3_BGR_REG_TWI3_RST_CLEAR_MASK

#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK   (0x00010000)

◆ TWI3_BGR_REG_TWI3_RST_DE_ASSERT

#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT   0b1

◆ TWI3_BGR_REG_TWI3_RST_OFFSET

#define TWI3_BGR_REG_TWI3_RST_OFFSET   16

◆ TWI4_BGR_REG

#define TWI4_BGR_REG   0x00000e90

◆ TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK

#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK   (0x00000001)

◆ TWI4_BGR_REG_TWI4_GATING_MASK

#define TWI4_BGR_REG_TWI4_GATING_MASK   0b0

◆ TWI4_BGR_REG_TWI4_GATING_OFFSET

#define TWI4_BGR_REG_TWI4_GATING_OFFSET   0

◆ TWI4_BGR_REG_TWI4_GATING_PASS

#define TWI4_BGR_REG_TWI4_GATING_PASS   0b1

◆ TWI4_BGR_REG_TWI4_RST_ASSERT

#define TWI4_BGR_REG_TWI4_RST_ASSERT   0b0

◆ TWI4_BGR_REG_TWI4_RST_CLEAR_MASK

#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK   (0x00010000)

◆ TWI4_BGR_REG_TWI4_RST_DE_ASSERT

#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT   0b1

◆ TWI4_BGR_REG_TWI4_RST_OFFSET

#define TWI4_BGR_REG_TWI4_RST_OFFSET   16

◆ TWI5_BGR_REG

#define TWI5_BGR_REG   0x00000e94

◆ TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK

#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK   (0x00000001)

◆ TWI5_BGR_REG_TWI5_GATING_MASK

#define TWI5_BGR_REG_TWI5_GATING_MASK   0b0

◆ TWI5_BGR_REG_TWI5_GATING_OFFSET

#define TWI5_BGR_REG_TWI5_GATING_OFFSET   0

◆ TWI5_BGR_REG_TWI5_GATING_PASS

#define TWI5_BGR_REG_TWI5_GATING_PASS   0b1

◆ TWI5_BGR_REG_TWI5_RST_ASSERT

#define TWI5_BGR_REG_TWI5_RST_ASSERT   0b0

◆ TWI5_BGR_REG_TWI5_RST_CLEAR_MASK

#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK   (0x00010000)

◆ TWI5_BGR_REG_TWI5_RST_DE_ASSERT

#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT   0b1

◆ TWI5_BGR_REG_TWI5_RST_OFFSET

#define TWI5_BGR_REG_TWI5_RST_OFFSET   16

◆ TWI6_BGR_REG

#define TWI6_BGR_REG   0x00000e98

◆ TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK

#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK   (0x00000001)

◆ TWI6_BGR_REG_TWI6_GATING_MASK

#define TWI6_BGR_REG_TWI6_GATING_MASK   0b0

◆ TWI6_BGR_REG_TWI6_GATING_OFFSET

#define TWI6_BGR_REG_TWI6_GATING_OFFSET   0

◆ TWI6_BGR_REG_TWI6_GATING_PASS

#define TWI6_BGR_REG_TWI6_GATING_PASS   0b1

◆ TWI6_BGR_REG_TWI6_RST_ASSERT

#define TWI6_BGR_REG_TWI6_RST_ASSERT   0b0

◆ TWI6_BGR_REG_TWI6_RST_CLEAR_MASK

#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK   (0x00010000)

◆ TWI6_BGR_REG_TWI6_RST_DE_ASSERT

#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT   0b1

◆ TWI6_BGR_REG_TWI6_RST_OFFSET

#define TWI6_BGR_REG_TWI6_RST_OFFSET   16

◆ TWI7_BGR_REG

#define TWI7_BGR_REG   0x00000e9c

◆ TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK

#define TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK   (0x00000001)

◆ TWI7_BGR_REG_TWI7_GATING_MASK

#define TWI7_BGR_REG_TWI7_GATING_MASK   0b0

◆ TWI7_BGR_REG_TWI7_GATING_OFFSET

#define TWI7_BGR_REG_TWI7_GATING_OFFSET   0

◆ TWI7_BGR_REG_TWI7_GATING_PASS

#define TWI7_BGR_REG_TWI7_GATING_PASS   0b1

◆ TWI7_BGR_REG_TWI7_RST_ASSERT

#define TWI7_BGR_REG_TWI7_RST_ASSERT   0b0

◆ TWI7_BGR_REG_TWI7_RST_CLEAR_MASK

#define TWI7_BGR_REG_TWI7_RST_CLEAR_MASK   (0x00010000)

◆ TWI7_BGR_REG_TWI7_RST_DE_ASSERT

#define TWI7_BGR_REG_TWI7_RST_DE_ASSERT   0b1

◆ TWI7_BGR_REG_TWI7_RST_OFFSET

#define TWI7_BGR_REG_TWI7_RST_OFFSET   16

◆ TWI8_BGR_REG

#define TWI8_BGR_REG   0x00000ea0

◆ TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK

#define TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK   (0x00000001)

◆ TWI8_BGR_REG_TWI8_GATING_MASK

#define TWI8_BGR_REG_TWI8_GATING_MASK   0b0

◆ TWI8_BGR_REG_TWI8_GATING_OFFSET

#define TWI8_BGR_REG_TWI8_GATING_OFFSET   0

◆ TWI8_BGR_REG_TWI8_GATING_PASS

#define TWI8_BGR_REG_TWI8_GATING_PASS   0b1

◆ TWI8_BGR_REG_TWI8_RST_ASSERT

#define TWI8_BGR_REG_TWI8_RST_ASSERT   0b0

◆ TWI8_BGR_REG_TWI8_RST_CLEAR_MASK

#define TWI8_BGR_REG_TWI8_RST_CLEAR_MASK   (0x00010000)

◆ TWI8_BGR_REG_TWI8_RST_DE_ASSERT

#define TWI8_BGR_REG_TWI8_RST_DE_ASSERT   0b1

◆ TWI8_BGR_REG_TWI8_RST_OFFSET

#define TWI8_BGR_REG_TWI8_RST_OFFSET   16

◆ TWI9_BGR_REG

#define TWI9_BGR_REG   0x00000ea4

◆ TWI9_BGR_REG_TWI9_GATING_CLEAR_MASK

#define TWI9_BGR_REG_TWI9_GATING_CLEAR_MASK   (0x00000001)

◆ TWI9_BGR_REG_TWI9_GATING_MASK

#define TWI9_BGR_REG_TWI9_GATING_MASK   0b0

◆ TWI9_BGR_REG_TWI9_GATING_OFFSET

#define TWI9_BGR_REG_TWI9_GATING_OFFSET   0

◆ TWI9_BGR_REG_TWI9_GATING_PASS

#define TWI9_BGR_REG_TWI9_GATING_PASS   0b1

◆ TWI9_BGR_REG_TWI9_RST_ASSERT

#define TWI9_BGR_REG_TWI9_RST_ASSERT   0b0

◆ TWI9_BGR_REG_TWI9_RST_CLEAR_MASK

#define TWI9_BGR_REG_TWI9_RST_CLEAR_MASK   (0x00010000)

◆ TWI9_BGR_REG_TWI9_RST_DE_ASSERT

#define TWI9_BGR_REG_TWI9_RST_DE_ASSERT   0b1

◆ TWI9_BGR_REG_TWI9_RST_OFFSET

#define TWI9_BGR_REG_TWI9_RST_OFFSET   16

◆ UART0_BGR_REG

#define UART0_BGR_REG   0x00000e00

◆ UART0_BGR_REG_UART0_GATING_CLEAR_MASK

#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK   (0x00000001)

◆ UART0_BGR_REG_UART0_GATING_MASK

#define UART0_BGR_REG_UART0_GATING_MASK   0b0

◆ UART0_BGR_REG_UART0_GATING_OFFSET

#define UART0_BGR_REG_UART0_GATING_OFFSET   0

◆ UART0_BGR_REG_UART0_GATING_PASS

#define UART0_BGR_REG_UART0_GATING_PASS   0b1

◆ UART0_BGR_REG_UART0_RST_ASSERT

#define UART0_BGR_REG_UART0_RST_ASSERT   0b0

◆ UART0_BGR_REG_UART0_RST_CLEAR_MASK

#define UART0_BGR_REG_UART0_RST_CLEAR_MASK   (0x00010000)

◆ UART0_BGR_REG_UART0_RST_DE_ASSERT

#define UART0_BGR_REG_UART0_RST_DE_ASSERT   0b1

◆ UART0_BGR_REG_UART0_RST_OFFSET

#define UART0_BGR_REG_UART0_RST_OFFSET   16

◆ UART1_BGR_REG

#define UART1_BGR_REG   0x00000e04

◆ UART1_BGR_REG_UART1_GATING_CLEAR_MASK

#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK   (0x00000001)

◆ UART1_BGR_REG_UART1_GATING_MASK

#define UART1_BGR_REG_UART1_GATING_MASK   0b0

◆ UART1_BGR_REG_UART1_GATING_OFFSET

#define UART1_BGR_REG_UART1_GATING_OFFSET   0

◆ UART1_BGR_REG_UART1_GATING_PASS

#define UART1_BGR_REG_UART1_GATING_PASS   0b1

◆ UART1_BGR_REG_UART1_RST_ASSERT

#define UART1_BGR_REG_UART1_RST_ASSERT   0b0

◆ UART1_BGR_REG_UART1_RST_CLEAR_MASK

#define UART1_BGR_REG_UART1_RST_CLEAR_MASK   (0x00010000)

◆ UART1_BGR_REG_UART1_RST_DE_ASSERT

#define UART1_BGR_REG_UART1_RST_DE_ASSERT   0b1

◆ UART1_BGR_REG_UART1_RST_OFFSET

#define UART1_BGR_REG_UART1_RST_OFFSET   16

◆ UART2_BGR_REG

#define UART2_BGR_REG   0x00000e08

◆ UART2_BGR_REG_UART2_GATING_CLEAR_MASK

#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK   (0x00000001)

◆ UART2_BGR_REG_UART2_GATING_MASK

#define UART2_BGR_REG_UART2_GATING_MASK   0b0

◆ UART2_BGR_REG_UART2_GATING_OFFSET

#define UART2_BGR_REG_UART2_GATING_OFFSET   0

◆ UART2_BGR_REG_UART2_GATING_PASS

#define UART2_BGR_REG_UART2_GATING_PASS   0b1

◆ UART2_BGR_REG_UART2_RST_ASSERT

#define UART2_BGR_REG_UART2_RST_ASSERT   0b0

◆ UART2_BGR_REG_UART2_RST_CLEAR_MASK

#define UART2_BGR_REG_UART2_RST_CLEAR_MASK   (0x00010000)

◆ UART2_BGR_REG_UART2_RST_DE_ASSERT

#define UART2_BGR_REG_UART2_RST_DE_ASSERT   0b1

◆ UART2_BGR_REG_UART2_RST_OFFSET

#define UART2_BGR_REG_UART2_RST_OFFSET   16

◆ UART3_BGR_REG

#define UART3_BGR_REG   0x00000e0c

◆ UART3_BGR_REG_UART3_GATING_CLEAR_MASK

#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK   (0x00000001)

◆ UART3_BGR_REG_UART3_GATING_MASK

#define UART3_BGR_REG_UART3_GATING_MASK   0b0

◆ UART3_BGR_REG_UART3_GATING_OFFSET

#define UART3_BGR_REG_UART3_GATING_OFFSET   0

◆ UART3_BGR_REG_UART3_GATING_PASS

#define UART3_BGR_REG_UART3_GATING_PASS   0b1

◆ UART3_BGR_REG_UART3_RST_ASSERT

#define UART3_BGR_REG_UART3_RST_ASSERT   0b0

◆ UART3_BGR_REG_UART3_RST_CLEAR_MASK

#define UART3_BGR_REG_UART3_RST_CLEAR_MASK   (0x00010000)

◆ UART3_BGR_REG_UART3_RST_DE_ASSERT

#define UART3_BGR_REG_UART3_RST_DE_ASSERT   0b1

◆ UART3_BGR_REG_UART3_RST_OFFSET

#define UART3_BGR_REG_UART3_RST_OFFSET   16

◆ UART4_BGR_REG

#define UART4_BGR_REG   0x00000e10

◆ UART4_BGR_REG_UART4_GATING_CLEAR_MASK

#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK   (0x00000001)

◆ UART4_BGR_REG_UART4_GATING_MASK

#define UART4_BGR_REG_UART4_GATING_MASK   0b0

◆ UART4_BGR_REG_UART4_GATING_OFFSET

#define UART4_BGR_REG_UART4_GATING_OFFSET   0

◆ UART4_BGR_REG_UART4_GATING_PASS

#define UART4_BGR_REG_UART4_GATING_PASS   0b1

◆ UART4_BGR_REG_UART4_RST_ASSERT

#define UART4_BGR_REG_UART4_RST_ASSERT   0b0

◆ UART4_BGR_REG_UART4_RST_CLEAR_MASK

#define UART4_BGR_REG_UART4_RST_CLEAR_MASK   (0x00010000)

◆ UART4_BGR_REG_UART4_RST_DE_ASSERT

#define UART4_BGR_REG_UART4_RST_DE_ASSERT   0b1

◆ UART4_BGR_REG_UART4_RST_OFFSET

#define UART4_BGR_REG_UART4_RST_OFFSET   16

◆ UART5_BGR_REG

#define UART5_BGR_REG   0x00000e14

◆ UART5_BGR_REG_UART5_GATING_CLEAR_MASK

#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK   (0x00000001)

◆ UART5_BGR_REG_UART5_GATING_MASK

#define UART5_BGR_REG_UART5_GATING_MASK   0b0

◆ UART5_BGR_REG_UART5_GATING_OFFSET

#define UART5_BGR_REG_UART5_GATING_OFFSET   0

◆ UART5_BGR_REG_UART5_GATING_PASS

#define UART5_BGR_REG_UART5_GATING_PASS   0b1

◆ UART5_BGR_REG_UART5_RST_ASSERT

#define UART5_BGR_REG_UART5_RST_ASSERT   0b0

◆ UART5_BGR_REG_UART5_RST_CLEAR_MASK

#define UART5_BGR_REG_UART5_RST_CLEAR_MASK   (0x00010000)

◆ UART5_BGR_REG_UART5_RST_DE_ASSERT

#define UART5_BGR_REG_UART5_RST_DE_ASSERT   0b1

◆ UART5_BGR_REG_UART5_RST_OFFSET

#define UART5_BGR_REG_UART5_RST_OFFSET   16

◆ UART6_BGR_REG

#define UART6_BGR_REG   0x00000e18

◆ UART6_BGR_REG_UART6_GATING_CLEAR_MASK

#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK   (0x00000001)

◆ UART6_BGR_REG_UART6_GATING_MASK

#define UART6_BGR_REG_UART6_GATING_MASK   0b0

◆ UART6_BGR_REG_UART6_GATING_OFFSET

#define UART6_BGR_REG_UART6_GATING_OFFSET   0

◆ UART6_BGR_REG_UART6_GATING_PASS

#define UART6_BGR_REG_UART6_GATING_PASS   0b1

◆ UART6_BGR_REG_UART6_RST_ASSERT

#define UART6_BGR_REG_UART6_RST_ASSERT   0b0

◆ UART6_BGR_REG_UART6_RST_CLEAR_MASK

#define UART6_BGR_REG_UART6_RST_CLEAR_MASK   (0x00010000)

◆ UART6_BGR_REG_UART6_RST_DE_ASSERT

#define UART6_BGR_REG_UART6_RST_DE_ASSERT   0b1

◆ UART6_BGR_REG_UART6_RST_OFFSET

#define UART6_BGR_REG_UART6_RST_OFFSET   16

◆ UFS_AXI_CLK_REG

#define UFS_AXI_CLK_REG   0x00000d80

◆ UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M   0b001

◆ UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b000

◆ UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK

#define UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ UFS_AXI_CLK_REG_FACTOR_M_OFFSET

#define UFS_AXI_CLK_REG_FACTOR_M_OFFSET   0

◆ UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON   0b1

◆ UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET

#define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET   31

◆ UFS_BGR_REG

#define UFS_BGR_REG   0x00000d8c

◆ UFS_BGR_REG_UFS_AXI_RST_ASSERT

#define UFS_BGR_REG_UFS_AXI_RST_ASSERT   0b0

◆ UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK

#define UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK   (0x00020000)

◆ UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT

#define UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT   0b1

◆ UFS_BGR_REG_UFS_AXI_RST_OFFSET

#define UFS_BGR_REG_UFS_AXI_RST_OFFSET   17

◆ UFS_BGR_REG_UFS_CORE_RST_ASSERT

#define UFS_BGR_REG_UFS_CORE_RST_ASSERT   0b0

◆ UFS_BGR_REG_UFS_CORE_RST_CLEAR_MASK

#define UFS_BGR_REG_UFS_CORE_RST_CLEAR_MASK   (0x00080000)

◆ UFS_BGR_REG_UFS_CORE_RST_DE_ASSERT

#define UFS_BGR_REG_UFS_CORE_RST_DE_ASSERT   0b1

◆ UFS_BGR_REG_UFS_CORE_RST_OFFSET

#define UFS_BGR_REG_UFS_CORE_RST_OFFSET   19

◆ UFS_BGR_REG_UFS_GATING_CLEAR_MASK

#define UFS_BGR_REG_UFS_GATING_CLEAR_MASK   (0x00000001)

◆ UFS_BGR_REG_UFS_GATING_MASK

#define UFS_BGR_REG_UFS_GATING_MASK   0b0

◆ UFS_BGR_REG_UFS_GATING_OFFSET

#define UFS_BGR_REG_UFS_GATING_OFFSET   0

◆ UFS_BGR_REG_UFS_GATING_PASS

#define UFS_BGR_REG_UFS_GATING_PASS   0b1

◆ UFS_BGR_REG_UFS_PHY_RST_ASSERT

#define UFS_BGR_REG_UFS_PHY_RST_ASSERT   0b0

◆ UFS_BGR_REG_UFS_PHY_RST_CLEAR_MASK

#define UFS_BGR_REG_UFS_PHY_RST_CLEAR_MASK   (0x00040000)

◆ UFS_BGR_REG_UFS_PHY_RST_DE_ASSERT

#define UFS_BGR_REG_UFS_PHY_RST_DE_ASSERT   0b1

◆ UFS_BGR_REG_UFS_PHY_RST_OFFSET

#define UFS_BGR_REG_UFS_PHY_RST_OFFSET   18

◆ UFS_BGR_REG_UFS_RST_ASSERT

#define UFS_BGR_REG_UFS_RST_ASSERT   0b0

◆ UFS_BGR_REG_UFS_RST_CLEAR_MASK

#define UFS_BGR_REG_UFS_RST_CLEAR_MASK   (0x00010000)

◆ UFS_BGR_REG_UFS_RST_DE_ASSERT

#define UFS_BGR_REG_UFS_RST_DE_ASSERT   0b1

◆ UFS_BGR_REG_UFS_RST_OFFSET

#define UFS_BGR_REG_UFS_RST_OFFSET   16

◆ UFS_CFG_CLK_REG

#define UFS_CFG_CLK_REG   0x00000d84

◆ UFS_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ UFS_CFG_CLK_REG_CLK_SRC_SEL_HOSC

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ UFS_CFG_CLK_REG_CLK_SRC_SEL_OFFSET

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ UFS_CFG_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define UFS_CFG_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b000

◆ UFS_CFG_CLK_REG_FACTOR_M_CLEAR_MASK

#define UFS_CFG_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ UFS_CFG_CLK_REG_FACTOR_M_OFFSET

#define UFS_CFG_CLK_REG_FACTOR_M_OFFSET   0

◆ UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLEAR_MASK

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_OFF

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_OFF   0b0

◆ UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_ON

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_CLOCK_IS_ON   0b1

◆ UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_OFFSET

#define UFS_CFG_CLK_REG_UFS_CFG_CLK_GATING_OFFSET   31

◆ UFS_REF_CLK_EN_REG

#define UFS_REF_CLK_EN_REG   0x00000d90

◆ UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_CLEAR_MASK

#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_CLEAR_MASK   (0x00000001)

◆ UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_OFFSET

#define UFS_REF_CLK_EN_REG_UFS_REF_CLK_EN_OFFSET   0

◆ USB0_BGR_REG

#define USB0_BGR_REG   0x00001304

◆ USB0_BGR_REG_USB0_DEVICE_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB0_DEVICE_GATING_CLEAR_MASK   (0x00000100)

◆ USB0_BGR_REG_USB0_DEVICE_GATING_MASK

#define USB0_BGR_REG_USB0_DEVICE_GATING_MASK   0b0

◆ USB0_BGR_REG_USB0_DEVICE_GATING_OFFSET

#define USB0_BGR_REG_USB0_DEVICE_GATING_OFFSET   8

◆ USB0_BGR_REG_USB0_DEVICE_GATING_PASS

#define USB0_BGR_REG_USB0_DEVICE_GATING_PASS   0b1

◆ USB0_BGR_REG_USB0_DEVICE_RST_ASSERT

#define USB0_BGR_REG_USB0_DEVICE_RST_ASSERT   0b0

◆ USB0_BGR_REG_USB0_DEVICE_RST_CLEAR_MASK

#define USB0_BGR_REG_USB0_DEVICE_RST_CLEAR_MASK   (0x01000000)

◆ USB0_BGR_REG_USB0_DEVICE_RST_DE_ASSERT

#define USB0_BGR_REG_USB0_DEVICE_RST_DE_ASSERT   0b1

◆ USB0_BGR_REG_USB0_DEVICE_RST_OFFSET

#define USB0_BGR_REG_USB0_DEVICE_RST_OFFSET   24

◆ USB0_BGR_REG_USB0_EHCI_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB0_EHCI_GATING_CLEAR_MASK   (0x00000010)

◆ USB0_BGR_REG_USB0_EHCI_GATING_MASK

#define USB0_BGR_REG_USB0_EHCI_GATING_MASK   0b0

◆ USB0_BGR_REG_USB0_EHCI_GATING_OFFSET

#define USB0_BGR_REG_USB0_EHCI_GATING_OFFSET   4

◆ USB0_BGR_REG_USB0_EHCI_GATING_PASS

#define USB0_BGR_REG_USB0_EHCI_GATING_PASS   0b1

◆ USB0_BGR_REG_USB0_EHCI_RST_ASSERT

#define USB0_BGR_REG_USB0_EHCI_RST_ASSERT   0b0

◆ USB0_BGR_REG_USB0_EHCI_RST_CLEAR_MASK

#define USB0_BGR_REG_USB0_EHCI_RST_CLEAR_MASK   (0x00100000)

◆ USB0_BGR_REG_USB0_EHCI_RST_DE_ASSERT

#define USB0_BGR_REG_USB0_EHCI_RST_DE_ASSERT   0b1

◆ USB0_BGR_REG_USB0_EHCI_RST_OFFSET

#define USB0_BGR_REG_USB0_EHCI_RST_OFFSET   20

◆ USB0_BGR_REG_USB0_OHCI_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB0_OHCI_GATING_CLEAR_MASK   (0x00000001)

◆ USB0_BGR_REG_USB0_OHCI_GATING_MASK

#define USB0_BGR_REG_USB0_OHCI_GATING_MASK   0b0

◆ USB0_BGR_REG_USB0_OHCI_GATING_OFFSET

#define USB0_BGR_REG_USB0_OHCI_GATING_OFFSET   0

◆ USB0_BGR_REG_USB0_OHCI_GATING_PASS

#define USB0_BGR_REG_USB0_OHCI_GATING_PASS   0b1

◆ USB0_BGR_REG_USB0_OHCI_RST_ASSERT

#define USB0_BGR_REG_USB0_OHCI_RST_ASSERT   0b0

◆ USB0_BGR_REG_USB0_OHCI_RST_CLEAR_MASK

#define USB0_BGR_REG_USB0_OHCI_RST_CLEAR_MASK   (0x00010000)

◆ USB0_BGR_REG_USB0_OHCI_RST_DE_ASSERT

#define USB0_BGR_REG_USB0_OHCI_RST_DE_ASSERT   0b1

◆ USB0_BGR_REG_USB0_OHCI_RST_OFFSET

#define USB0_BGR_REG_USB0_OHCI_RST_OFFSET   16

◆ USB0_CLK_REG

#define USB0_CLK_REG   0x00001300

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b000

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M   0b001

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   (0x03000000)

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC   0b011

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K   0b010

◆ USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24

◆ USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   (0x80000000)

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1

◆ USB0_CLK_REG_USB0_CLKEN_OFFSET

#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31

◆ USB0_CLK_REG_USB0_PHY_RSTN_ASSERT

#define USB0_CLK_REG_USB0_PHY_RSTN_ASSERT   0b0

◆ USB0_CLK_REG_USB0_PHY_RSTN_CLEAR_MASK

#define USB0_CLK_REG_USB0_PHY_RSTN_CLEAR_MASK   (0x40000000)

◆ USB0_CLK_REG_USB0_PHY_RSTN_DE_ASSERT

#define USB0_CLK_REG_USB0_PHY_RSTN_DE_ASSERT   0b1

◆ USB0_CLK_REG_USB0_PHY_RSTN_OFFSET

#define USB0_CLK_REG_USB0_PHY_RSTN_OFFSET   30

◆ USB0_USB1_REF_CLK_REG

#define USB0_USB1_REF_CLK_REG   0x00001340

◆ USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_HOSC

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB0_USB1_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLEAR_MASK

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_OFF

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_ON

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_OFFSET

#define USB0_USB1_REF_CLK_REG_USB0_USB1_REF_CLK_GATING_OFFSET   31

◆ USB1_BGR_REG

#define USB1_BGR_REG   0x0000130c

◆ USB1_BGR_REG_USB1_EHCI_GATING_CLEAR_MASK

#define USB1_BGR_REG_USB1_EHCI_GATING_CLEAR_MASK   (0x00000010)

◆ USB1_BGR_REG_USB1_EHCI_GATING_MASK

#define USB1_BGR_REG_USB1_EHCI_GATING_MASK   0b0

◆ USB1_BGR_REG_USB1_EHCI_GATING_OFFSET

#define USB1_BGR_REG_USB1_EHCI_GATING_OFFSET   4

◆ USB1_BGR_REG_USB1_EHCI_GATING_PASS

#define USB1_BGR_REG_USB1_EHCI_GATING_PASS   0b1

◆ USB1_BGR_REG_USB1_EHCI_RST_ASSERT

#define USB1_BGR_REG_USB1_EHCI_RST_ASSERT   0b0

◆ USB1_BGR_REG_USB1_EHCI_RST_CLEAR_MASK

#define USB1_BGR_REG_USB1_EHCI_RST_CLEAR_MASK   (0x00100000)

◆ USB1_BGR_REG_USB1_EHCI_RST_DE_ASSERT

#define USB1_BGR_REG_USB1_EHCI_RST_DE_ASSERT   0b1

◆ USB1_BGR_REG_USB1_EHCI_RST_OFFSET

#define USB1_BGR_REG_USB1_EHCI_RST_OFFSET   20

◆ USB1_BGR_REG_USB1_OHCI_GATING_CLEAR_MASK

#define USB1_BGR_REG_USB1_OHCI_GATING_CLEAR_MASK   (0x00000001)

◆ USB1_BGR_REG_USB1_OHCI_GATING_MASK

#define USB1_BGR_REG_USB1_OHCI_GATING_MASK   0b0

◆ USB1_BGR_REG_USB1_OHCI_GATING_OFFSET

#define USB1_BGR_REG_USB1_OHCI_GATING_OFFSET   0

◆ USB1_BGR_REG_USB1_OHCI_GATING_PASS

#define USB1_BGR_REG_USB1_OHCI_GATING_PASS   0b1

◆ USB1_BGR_REG_USB1_OHCI_RST_ASSERT

#define USB1_BGR_REG_USB1_OHCI_RST_ASSERT   0b0

◆ USB1_BGR_REG_USB1_OHCI_RST_CLEAR_MASK

#define USB1_BGR_REG_USB1_OHCI_RST_CLEAR_MASK   (0x00010000)

◆ USB1_BGR_REG_USB1_OHCI_RST_DE_ASSERT

#define USB1_BGR_REG_USB1_OHCI_RST_DE_ASSERT   0b1

◆ USB1_BGR_REG_USB1_OHCI_RST_OFFSET

#define USB1_BGR_REG_USB1_OHCI_RST_OFFSET   16

◆ USB1_CLK_REG

#define USB1_CLK_REG   0x00001308

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b000

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M   0b001

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   (0x03000000)

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC   0b011

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K   0b010

◆ USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET

#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24

◆ USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   (0x80000000)

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0b0

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0b1

◆ USB1_CLK_REG_USB1_CLKEN_OFFSET

#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31

◆ USB1_CLK_REG_USB1_PHY_RSTN_ASSERT

#define USB1_CLK_REG_USB1_PHY_RSTN_ASSERT   0b0

◆ USB1_CLK_REG_USB1_PHY_RSTN_CLEAR_MASK

#define USB1_CLK_REG_USB1_PHY_RSTN_CLEAR_MASK   (0x40000000)

◆ USB1_CLK_REG_USB1_PHY_RSTN_DE_ASSERT

#define USB1_CLK_REG_USB1_PHY_RSTN_DE_ASSERT   0b1

◆ USB1_CLK_REG_USB1_PHY_RSTN_OFFSET

#define USB1_CLK_REG_USB1_PHY_RSTN_OFFSET   30

◆ USB2_BGR_REG

#define USB2_BGR_REG   0x0000135c

◆ USB2_BGR_REG_USB2_RST_ASSERT

#define USB2_BGR_REG_USB2_RST_ASSERT   0b0

◆ USB2_BGR_REG_USB2_RST_CLEAR_MASK

#define USB2_BGR_REG_USB2_RST_CLEAR_MASK   (0x00010000)

◆ USB2_BGR_REG_USB2_RST_DE_ASSERT

#define USB2_BGR_REG_USB2_RST_DE_ASSERT   0b1

◆ USB2_BGR_REG_USB2_RST_OFFSET

#define USB2_BGR_REG_USB2_RST_OFFSET   16

◆ USB2_MF_CLK_REG

#define USB2_MF_CLK_REG   0x00001354

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB2_MF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ USB2_MF_CLK_REG_FACTOR_M_OFFSET

#define USB2_MF_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET   31

◆ USB2_SUSPEND_CLK_REG

#define USB2_SUSPEND_CLK_REG   0x00001350

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x01000000)

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K   0b0

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b1

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET

#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31

◆ USB2_U2_PIPE_CLK_REG

#define USB2_U2_PIPE_CLK_REG   0x00001364

◆ USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b001

◆ USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB2_U2_PIPE_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ USB2_U2_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_U2_PIPE_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ USB2_U2_PIPE_CLK_REG_FACTOR_M_OFFSET

#define USB2_U2_PIPE_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLEAR_MASK

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_OFF

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_ON

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_OFFSET

#define USB2_U2_PIPE_CLK_REG_USB2_U2_PIPE_CLK_GATING_OFFSET   31

◆ USB2_U2_REF_CLK_REG

#define USB2_U2_REF_CLK_REG   0x00001348

◆ USB2_U2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ USB2_U2_REF_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_HOSC   0b001

◆ USB2_U2_REF_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_U2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB2_U2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLEAR_MASK

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_OFF

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_ON

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_OFFSET

#define USB2_U2_REF_CLK_REG_USB2_U2_REF_CLK_GATING_OFFSET   31

◆ USB2_U3_UTMI_CLK_REG

#define USB2_U3_UTMI_CLK_REG   0x00001360

◆ USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_HOSC   0b010

◆ USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b001

◆ USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M

#define USB2_U3_UTMI_CLK_REG_CLK_SRC_SEL_SYS_CLK24M   0b000

◆ USB2_U3_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_U3_UTMI_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ USB2_U3_UTMI_CLK_REG_FACTOR_M_OFFSET

#define USB2_U3_UTMI_CLK_REG_FACTOR_M_OFFSET   0

◆ USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLEAR_MASK

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_OFF

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_ON

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_CLOCK_IS_ON   0b1

◆ USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_OFFSET

#define USB2_U3_UTMI_CLK_REG_USB2_U3_UTMI_CLK_GATING_OFFSET   31

◆ USBEHCI0_GATIING_BIT

#define USBEHCI0_GATIING_BIT   4

◆ USBEHCI0_RST_BIT

#define USBEHCI0_RST_BIT   20

◆ USBEHCI1_GATIING_BIT

#define USBEHCI1_GATIING_BIT   4

◆ USBEHCI1_RST_BIT

#define USBEHCI1_RST_BIT   20

◆ USBPHY0_RST_BIT

#define USBPHY0_RST_BIT   30

◆ USBPHY0_SCLK_GATING_BIT

#define USBPHY0_SCLK_GATING_BIT   31

◆ USBPHY1_RST_BIT

#define USBPHY1_RST_BIT   30

◆ USBPHY1_SCLK_GATING_BIT

#define USBPHY1_SCLK_GATING_BIT   31

◆ VE_BGR_REG

#define VE_BGR_REG   0x00000a8c

◆ VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK

#define VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK   (0x00000004)

◆ VE_BGR_REG_VE_DEC_GATING_MASK

#define VE_BGR_REG_VE_DEC_GATING_MASK   0b0

◆ VE_BGR_REG_VE_DEC_GATING_OFFSET

#define VE_BGR_REG_VE_DEC_GATING_OFFSET   2

◆ VE_BGR_REG_VE_DEC_GATING_PASS

#define VE_BGR_REG_VE_DEC_GATING_PASS   0b1

◆ VE_BGR_REG_VE_DEC_RST_ASSERT

#define VE_BGR_REG_VE_DEC_RST_ASSERT   0b0

◆ VE_BGR_REG_VE_DEC_RST_CLEAR_MASK

#define VE_BGR_REG_VE_DEC_RST_CLEAR_MASK   (0x00040000)

◆ VE_BGR_REG_VE_DEC_RST_DE_ASSERT

#define VE_BGR_REG_VE_DEC_RST_DE_ASSERT   0b1

◆ VE_BGR_REG_VE_DEC_RST_OFFSET

#define VE_BGR_REG_VE_DEC_RST_OFFSET   18

◆ VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK

#define VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK   (0x00000001)

◆ VE_BGR_REG_VE_ENC0_GATING_MASK

#define VE_BGR_REG_VE_ENC0_GATING_MASK   0b0

◆ VE_BGR_REG_VE_ENC0_GATING_OFFSET

#define VE_BGR_REG_VE_ENC0_GATING_OFFSET   0

◆ VE_BGR_REG_VE_ENC0_GATING_PASS

#define VE_BGR_REG_VE_ENC0_GATING_PASS   0b1

◆ VE_BGR_REG_VE_ENC0_RST_ASSERT

#define VE_BGR_REG_VE_ENC0_RST_ASSERT   0b0

◆ VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK

#define VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK   (0x00010000)

◆ VE_BGR_REG_VE_ENC0_RST_DE_ASSERT

#define VE_BGR_REG_VE_ENC0_RST_DE_ASSERT   0b1

◆ VE_BGR_REG_VE_ENC0_RST_OFFSET

#define VE_BGR_REG_VE_ENC0_RST_OFFSET   16

◆ VE_DEC_CLK_REG

#define VE_DEC_CLK_REG   0x00000a88

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X

#define VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b101

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL

#define VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL   0b110

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b100

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b010

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL

#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL   0b001

◆ VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL

#define VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL   0b000

◆ VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ VE_DEC_CLK_REG_FACTOR_M_OFFSET

#define VE_DEC_CLK_REG_FACTOR_M_OFFSET   0

◆ VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON   0b1

◆ VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET

#define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET   31

◆ VE_ENC0_CLK_REG

#define VE_ENC0_CLK_REG   0x00000a80

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X   0b101

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL   0b110

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b100

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M   0b011

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M   0b010

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL   0b000

◆ VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL

#define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL   0b001

◆ VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ VE_ENC0_CLK_REG_FACTOR_M_OFFSET

#define VE_ENC0_CLK_REG_FACTOR_M_OFFSET   0

◆ VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON   0b1

◆ VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET

#define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET   31

◆ VEPLL_GATE_EN_REG

#define VEPLL_GATE_EN_REG   0x00001918

◆ VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO   0b0

◆ VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET

#define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET   0

◆ VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE   0b0

◆ VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE   0b1

◆ VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET

#define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET   16

◆ VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO   0b0

◆ VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET

#define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET   1

◆ VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE   0b0

◆ VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE   0b1

◆ VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET

#define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET   17

◆ VEPLL_GATE_STAT_REG

#define VEPLL_GATE_STAT_REG   0x00001998

◆ VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE   0b0

◆ VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE   0b1

◆ VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET

#define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET   16

◆ VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE   0b0

◆ VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE   0b1

◆ VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET

#define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET   17

◆ VIDEO_IN_BGR_REG

#define VIDEO_IN_BGR_REG   0x00001884

◆ VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT   0b0

◆ VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK   (0x00010000)

◆ VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT   0b1

◆ VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET

#define VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET   16

◆ VIDEO_OUT0_BGR_REG

#define VIDEO_OUT0_BGR_REG   0x000016e4

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT   0b0

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK   (0x00010000)

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT   0b1

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET   16

◆ VIDEO_OUT1_BGR_REG

#define VIDEO_OUT1_BGR_REG   0x000016ec

◆ VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT   0b0

◆ VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK   (0x00010000)

◆ VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT   0b1

◆ VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET

#define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET   16

◆ VIDEOPLL_GATE_EN_REG

#define VIDEOPLL_GATE_EN_REG   0x00001910

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000010)

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET   4

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00100000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET   20

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000001)

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET   0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00010000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET   16

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000020)

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET   5

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00200000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET   21

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000002)

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET   1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00020000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET   17

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK   (0x00000040)

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET   6

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK   (0x00400000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET   22

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK   (0x00000004)

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET   2

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK   (0x00040000)

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET   18

◆ VIDEOPLL_GATE_STAT_REG

#define VIDEOPLL_GATE_STAT_REG   0x00001990

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK   (0x00100000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET   20

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK   (0x00010000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET   16

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK   (0x00200000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET   21

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK   (0x00020000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET   17

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK   (0x00400000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET   22

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK   (0x00040000)

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET   18

◆ VO0_TCONLCD0_BGR_REG

#define VO0_TCONLCD0_BGR_REG   0x00001504

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK   (0x00000001)

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK   0b0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET   0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS   0b1

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT   0b0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK   (0x00010000)

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT   0b1

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET   16

◆ VO0_TCONLCD0_CLK_REG

#define VO0_TCONLCD0_CLK_REG   0x00001500

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0b1

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET   31

◆ VO0_TCONLCD1_BGR_REG

#define VO0_TCONLCD1_BGR_REG   0x0000150c

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK   (0x00000001)

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK   0b0

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET   0

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS   0b1

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT   0b0

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK   (0x00010000)

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT   0b1

◆ VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET

#define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET   16

◆ VO0_TCONLCD1_CLK_REG

#define VO0_TCONLCD1_CLK_REG   0x00001508

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET   0

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON   0b1

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET   31

◆ VO0_TCONLCD2_BGR_REG

#define VO0_TCONLCD2_BGR_REG   0x00001514

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK   (0x00000001)

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK   0b0

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET   0

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS   0b1

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT   0b0

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK   (0x00010000)

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT   0b1

◆ VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET

#define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET   16

◆ VO0_TCONLCD2_CLK_REG

#define VO0_TCONLCD2_CLK_REG   0x00001510

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   (0x07000000)

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0b011

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0b000

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0b001

◆ VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0b010

◆ VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK   (0x0000001f)

◆ VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET   0

◆ VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK   (0x80000000)

◆ VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON   0b1

◆ VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET

#define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET   31

◆ XO_CONTROL0_REG

#define XO_CONTROL0_REG   0x0160
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