sys-clk.c File Reference

#include <io.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <timer.h>
#include <log.h>
#include <sys-clk.h>

Include dependency graph for sys-clk.c:

Macros
#define	CPU_UPDATE_OFFSET   (26)
#define	CPU_LOCK_OFFSET   (28)
#define	CPU_LOCK_ENABLE_OFFSET   (29)

Functions
static void	enable_pll (uint32_t reg_addr, uint32_t n_factor)
	Enables the PLL (Phase-Locked Loop) with a given factor.
static void	set_pll_cpux_axi (void)
	Configures the CPU and DSU PLLs, and sets the CPU-to-AXI divider.
static void	set_apb (void)
	Configures the APB clock source and divider.
static void	set_pll_nsi (void)
	Configures the NSI (Non-Shared Interface) clock source and gating.
static void	set_pll_mbus (void)
	Configures the MBUS (Memory Bus) clock source and gating.
void	sunxi_clk_init (void)
	Initializes the clocks for the Sunxi platform.
void	sunxi_clk_dump ()
	Dump all clock-related register values.

Macro Definition Documentation

CPU_LOCK_ENABLE_OFFSET

#define CPU_LOCK_ENABLE_OFFSET   (29)

CPU_LOCK_OFFSET

#define CPU_LOCK_OFFSET   (28)

CPU_UPDATE_OFFSET

#define CPU_UPDATE_OFFSET   (26)

Function Documentation

enable_pll()

static void enable_pll ( uint32_t  reg_addr, uint32_t  n_factor  )

static

Enables the PLL (Phase-Locked Loop) with a given factor.

This function configures and enables the PLL by setting specific bits in the provided register address. The PLL configuration parameters such as n_factor, lock enable, and update offset are adjusted to match the desired PLL configuration. After configuring, the function waits for the PLL to lock and then performs a final check to ensure the lock is complete.

Parameters

reg_addr	The register address to configure the PLL.
n_factor	The PLL multiplier factor (used to set the PLL's frequency). Typically, this value will be used in the calculation: PLL Frequency = 24M * n / p / (m0 * m1). A specific n_factor value adjusts the PLL's output.

Note

The function waits for the PLL to lock and ensures proper updates and lock status before completing the operation. Additionally, delays and register bit manipulations ensure the PLL is stable and functioning.

set_apb()

static void set_apb ( void  )

static

Configures the APB clock source and divider.

This function configures the APB1 clock source and sets its divider to a default value by modifying the appropriate control registers. It ensures the APB clock is sourced from the High-Speed Oscillator (HOSC) and sets the APB clock factor to its default value.

Note

This function performs two key actions: setting the APB clock source and resetting the APB clock divider factor.

set_pll_cpux_axi()

static void set_pll_cpux_axi ( void  )

static

Configures the CPU and DSU PLLs, and sets the CPU-to-AXI divider.

This function configures the PLLs for the CPU and DSU by calling the enable_pll function with predefined PLL multiplier factors. It also adjusts the CPU-to-AXI clock divider by modifying the corresponding register to control the clock speed and synchronization.

Note

The function performs PLL configuration for both the CPU (CCU_REG_PLL_C0_CPUX) and DSU (CCU_REG_PLL_C0_DSU) and sets the CPU-to-AXI clock divider factor.

set_pll_mbus()

static void set_pll_mbus ( void  )

static

Configures the MBUS (Memory Bus) clock source and gating.

This function first disables the MBUS clock gating, updates the MBUS clock divider, then sets the MBUS clock source to DDR PLL, and finally enables the MBUS clock. It waits for the updates to complete to ensure proper clock configuration.

Note

The function performs two main stages:

1. Disabling clock gating and updating the MBUS divider.
2. Setting the MBUS clock source to DDR PLL and enabling the MBUS clock.

set_pll_nsi()

static void set_pll_nsi ( void  )

static

Configures the NSI (Non-Shared Interface) clock source and gating.

This function first disables the NSI clock gating, updates the NSI clock divider, then sets the NSI clock source to DDR PLL, and finally enables the NSI clock. It also waits for the updates to complete, ensuring that the clock configurations are applied correctly.

Note

The function performs two main stages:

1. Disabling clock gating and updating the NSI divider.
2. Setting the NSI clock source to DDR PLL and enabling the NSI clock.

sunxi_clk_dump()

void sunxi_clk_dump

(

void

)

Dump all clock-related register values.

This function prints out all clock-related register values for debugging and observation.

sunxi_clk_init()

void sunxi_clk_init

(

void

)

Initializes the clocks for the Sunxi platform.

Initialize the global clocks.

This function configures various clock sources for the CPU, AXI, APB, NSI, and MBUS based on the Sunxi platform's requirements. The function also prints debug messages to track the initialization process.

It performs the following tasks:

• Configures the CPU and AXI clock using the set_pll_cpux_axi() function.
• Configures the APB clock using the set_apb() function.
• Configures the NSI clock using the set_pll_nsi() function.
• Configures the MBUS clock using the set_pll_mbus() function.

Note

This function should be called during the system initialization process to ensure the correct operation of the platform's clock system.

Warning

Ensure that all the clock configuration functions are correctly implemented and tested to avoid system instability.