This graph shows which files directly or indirectly include this file:

Macros
#define	SUNXI_BROM_BASE 0x00000000

#define	SUNXI_SRAM_C_BASE 0x00020000

#define	SUNXI_VE_BASE 0x01C0E000

#define	SUNXI_GPIO_BASE 0x02000000

#define	SUNXI_RGPIO_BASE 0x02000540

#define	SUNXI_PWM_BASE 0x02000C00

#define	SUNXI_CCU_BASE 0x02001000

#define	SUNXI_GPADC_BASE 0x02009000

#define	SUNXI_THS_BASE 0x02009400

#define	SUNXI_ADDA_BASE 0x02030000

#define	SUNXI_DMIC_BASE 0x02031000

#define	SUNXI_I2S0_BASE 0x02032000

#define	SUNXI_I2S1_BASE 0x02033000

#define	SUNXI_TIMER_BASE 0x02050000

#define	SUNXI_UART0_BASE 0x02500000

#define	SUNXI_UART1_BASE 0x02500400

#define	SUNXI_UART2_BASE 0x02500800

#define	SUNXI_UART3_BASE 0x02500C00

#define	SUNXI_TWI0_BASE 0x02502000

#define	SUNXI_TWI1_BASE 0x02502400

#define	SUNXI_TWI2_BASE 0x02502800

#define	SUNXI_TWI3_BASE 0x02502C00

#define	SUNXI_SYSCTRL_BASE 0x03000000

#define	SUNXI_DMA0_SGDMA__BASE 0x03002000

#define	SUNXI_SPINLOCK_BASE 0x03005000

#define	SUNXI_HSTIMER_BASE 0x03008000

#define	SUNXI_DCU_BASE 0x03010000

#define	SUNXI_CPU_GIC_BASE 0x03020000

#define	SUNXI_CE_BASE 0x03040000

#define	SUNXI_CE_KEY_SRAM_BASE 0x03041000

#define	SUNXI_DMA1_NDMA__BASE 0x03042000

#define	SUNXI_SQPI_PSRAMC_BASE 0x03043000

#define	SUNXI_NPU_BASE 0x03050000

#define	SUNXI_MSI_MEMC_BASE 0x03102000

#define	SUNXI_SMHC0_BASE 0x04020000

#define	SUNXI_SMHC1_BASE 0x04021000

#define	SUNXI_SPI0_BASE 0x04025000

#define	SUNXI_SPI1_BASE 0x04026000

#define	SUNXI_USB0_BASE 0x04100000

#define	SUNXI_EMAC_BASE 0x04500000

#define	SUNXI_SPI_FLASH_BASE 0x04F00000

#define	SUNXI_DE_BASE 0x05000000

#define	SUNXI_G2D_BASE 0x05410000

#define	SUNXI_DSI0_BASE 0x05450000

#define	SUNXI_DISPLAY_TOP_BASE 0x05460000

#define	SUNXI_TCON_LCD0_BASE 0x05461000

#define	SUNXI_CSI_BASE 0x05800000

#define	SUNXI_ISP_BASE 0x05900000

#define	SUNXI_R_CPUCFG_BASE 0x07000400

#define	SUNXI_R_PPU_BASE 0x07001000

#define	SUNXI_R_SPC_BASE 0x07002000

#define	SUNXI_R_PRCM_BASE 0x07010000

#define	SUNXI_R_TWD_BASE 0x07020800

#define	SUNXI_RTC_BASE 0x07090000

#define	SUNXI_SID_BASE 0x07091000

#define	SUNXI_CPUX_PMC_BASE 0x08000000

#define	SUNXI_CPUX_CFG_BASE 0x08008000

#define	SUNXI_CPUX_WDG_BASE 0x08009000

#define	SUNXI_CPUX_TS_BASE 0x0800A000

#define	SUNXI_CPUX_MSGBOX_BASE 0x0800B000

#define	SUNXI_SPI_FLASH_XIP_BASE 0x10000000

#define	SUNXI_SQPI_PSRAM_XIP_BASE 0x12000000

#define	SUNXI_RISCV_CLINT_BASE 0x30000000

#define	SUNXI_RISCV_CLIC_BASE 0x30800000

#define	SUNXI_RESERVE_BASE 0x30805000

#define	SUNXI_RISCV_SYSMAP_BASE 0x3FFFF000

#define	SUNXI_CPUX_PLIC_BASE 0x30000000

#define	SUNXI_CPUX_CLINT_BASE 0x34000000

#define	SUNXI_DRAM_SPACE_BASE 0x40000000

#define	SUNXI_PIO_BASE (SUNXI_GPIO_BASE)

#define	SUNXI_RPIO_BASE (SUNXI_RGPIO_BASE)

#define	SUNXI_SS_BASE (SUNXI_CE_BASE)

#define	SUNXI_SYSCRL_BASE (SUNXI_SYSCTRL_BASE)

#define	SUNXI_RTWI_BASE (SUNXI_TWI0_BASE)

#define	SUNXI_RTWI_BRG_REG (SUNXI_CCU_BASE + 0x091c)

#define	SUNXI_RST_BIT (16)

#define	SUNXI_GATING_BIT (0)

#define	SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)

#define	SUNXI_RTC_PMC_BYPASS_STATUS (SUNXI_RTC_BASE + 0x238)

#define	SUNXI_RTC_IOMODE_CTL (SUNXI_RTC_BASE + 0x240)

#define	SUNXI_CPUS_CFG_BASE (0x07000400U)

#define	SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE)

#define	SUNXI_SPIF_BASE (SUNXI_SPI_FLASH_BASE)

#define	SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0)

#define	SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4)

#define	SYSRTC_BOOTFLAG_REG 0x02A0

#define	BOOT_SYS_UPDATE 0x2

#define	SUNXI_BOOTFLAG_WRITE_KEY 0x429B0000

#define	SUNXI_WDOG_KEY_FILED 0x16AA0000

#define	SUNXI_WDOG_MODE_REG 0x18

#define	VCC33_DET_CTRL_REG (0x1f4)

#define	VCCIO_THRESHOLD_MASK (0xff)

#define	VCCIO_THRESHOLD_VOLTAGE_2_5 (0 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_6 (1 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_7 (2 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_8 (3 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_9 (4 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_3_0 (5 << 4)

#define	FORCE_DETECTER_OUTPUT (1 << 7)

#define	VCCIO_DET_BYPASS_EN (1 << 0)

#define	SUNXI_PLAT_TCIP_BASE_ADDR (SUNXI_RISCV_CLINT_BASE)

#define	SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)

Macro Definition Documentation

◆ BOOT_SYS_UPDATE

#define BOOT_SYS_UPDATE 0x2

◆ FORCE_DETECTER_OUTPUT

#define FORCE_DETECTER_OUTPUT (1 << 7)

◆ SRAM_CONTRL_REG0

#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0)

◆ SRAM_CONTRL_REG1

#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4)

◆ SUNXI_ADDA_BASE

#define SUNXI_ADDA_BASE 0x02030000

◆ SUNXI_BOOTFLAG_WRITE_KEY

#define SUNXI_BOOTFLAG_WRITE_KEY 0x429B0000

◆ SUNXI_BROM_BASE

#define SUNXI_BROM_BASE 0x00000000

◆ SUNXI_CCU_BASE

#define SUNXI_CCU_BASE 0x02001000

◆ SUNXI_CE_BASE

#define SUNXI_CE_BASE 0x03040000

◆ SUNXI_CE_KEY_SRAM_BASE

#define SUNXI_CE_KEY_SRAM_BASE 0x03041000

◆ SUNXI_CPU_GIC_BASE

#define SUNXI_CPU_GIC_BASE 0x03020000

◆ SUNXI_CPUS_CFG_BASE

#define SUNXI_CPUS_CFG_BASE (0x07000400U)

◆ SUNXI_CPUX_CFG_BASE

#define SUNXI_CPUX_CFG_BASE 0x08008000

◆ SUNXI_CPUX_CLINT_BASE

#define SUNXI_CPUX_CLINT_BASE 0x34000000

◆ SUNXI_CPUX_MSGBOX_BASE

#define SUNXI_CPUX_MSGBOX_BASE 0x0800B000

◆ SUNXI_CPUX_PLIC_BASE

#define SUNXI_CPUX_PLIC_BASE 0x30000000

◆ SUNXI_CPUX_PMC_BASE

#define SUNXI_CPUX_PMC_BASE 0x08000000

◆ SUNXI_CPUX_TS_BASE

#define SUNXI_CPUX_TS_BASE 0x0800A000

◆ SUNXI_CPUX_WDG_BASE

#define SUNXI_CPUX_WDG_BASE 0x08009000

◆ SUNXI_CSI_BASE

#define SUNXI_CSI_BASE 0x05800000

◆ SUNXI_DCU_BASE

#define SUNXI_DCU_BASE 0x03010000

◆ SUNXI_DE_BASE

#define SUNXI_DE_BASE 0x05000000

◆ SUNXI_DISPLAY_TOP_BASE

#define SUNXI_DISPLAY_TOP_BASE 0x05460000

◆ SUNXI_DMA0_SGDMA__BASE

#define SUNXI_DMA0_SGDMA__BASE 0x03002000

◆ SUNXI_DMA1_NDMA__BASE

#define SUNXI_DMA1_NDMA__BASE 0x03042000

◆ SUNXI_DMIC_BASE

#define SUNXI_DMIC_BASE 0x02031000

◆ SUNXI_DRAM_SPACE_BASE

#define SUNXI_DRAM_SPACE_BASE 0x40000000

◆ SUNXI_DSI0_BASE

#define SUNXI_DSI0_BASE 0x05450000

◆ SUNXI_EMAC_BASE

#define SUNXI_EMAC_BASE 0x04500000

◆ SUNXI_G2D_BASE

#define SUNXI_G2D_BASE 0x05410000

◆ SUNXI_GATING_BIT

#define SUNXI_GATING_BIT (0)

◆ SUNXI_GPADC_BASE

#define SUNXI_GPADC_BASE 0x02009000

◆ SUNXI_GPIO_BASE

#define SUNXI_GPIO_BASE 0x02000000

◆ SUNXI_HSTIMER_BASE

#define SUNXI_HSTIMER_BASE 0x03008000

◆ SUNXI_I2S0_BASE

#define SUNXI_I2S0_BASE 0x02032000

◆ SUNXI_I2S1_BASE

#define SUNXI_I2S1_BASE 0x02033000

◆ SUNXI_ISP_BASE

#define SUNXI_ISP_BASE 0x05900000

◆ SUNXI_MSI_MEMC_BASE

#define SUNXI_MSI_MEMC_BASE 0x03102000

◆ SUNXI_NPU_BASE

#define SUNXI_NPU_BASE 0x03050000

◆ SUNXI_PIO_BASE

#define SUNXI_PIO_BASE (SUNXI_GPIO_BASE)

◆ SUNXI_PLAT_TCIP_BASE_ADDR

#define SUNXI_PLAT_TCIP_BASE_ADDR (SUNXI_RISCV_CLINT_BASE)

◆ SUNXI_PWM_BASE

#define SUNXI_PWM_BASE 0x02000C00

◆ SUNXI_R_CPUCFG_BASE

#define SUNXI_R_CPUCFG_BASE 0x07000400

◆ SUNXI_R_PPU_BASE

#define SUNXI_R_PPU_BASE 0x07001000

◆ SUNXI_R_PRCM_BASE

#define SUNXI_R_PRCM_BASE 0x07010000

◆ SUNXI_R_SPC_BASE

#define SUNXI_R_SPC_BASE 0x07002000

◆ SUNXI_R_TWD_BASE

#define SUNXI_R_TWD_BASE 0x07020800

◆ SUNXI_RCPUCFG_BASE

#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE)

◆ SUNXI_RESERVE_BASE

#define SUNXI_RESERVE_BASE 0x30805000

◆ SUNXI_RGPIO_BASE

#define SUNXI_RGPIO_BASE 0x02000540

◆ SUNXI_RISCV_CLIC_BASE

#define SUNXI_RISCV_CLIC_BASE 0x30800000

◆ SUNXI_RISCV_CLINT_BASE

#define SUNXI_RISCV_CLINT_BASE 0x30000000

◆ SUNXI_RISCV_SYSMAP_BASE

#define SUNXI_RISCV_SYSMAP_BASE 0x3FFFF000

◆ SUNXI_RPIO_BASE

#define SUNXI_RPIO_BASE (SUNXI_RGPIO_BASE)

◆ SUNXI_RST_BIT

#define SUNXI_RST_BIT (16)

◆ SUNXI_RTC_BASE

#define SUNXI_RTC_BASE 0x07090000

◆ SUNXI_RTC_DATA_BASE

#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)

◆ SUNXI_RTC_IOMODE_CTL

#define SUNXI_RTC_IOMODE_CTL (SUNXI_RTC_BASE + 0x240)

◆ SUNXI_RTC_PMC_BYPASS_STATUS

#define SUNXI_RTC_PMC_BYPASS_STATUS (SUNXI_RTC_BASE + 0x238)

◆ SUNXI_RTWI_BASE

#define SUNXI_RTWI_BASE (SUNXI_TWI0_BASE)

◆ SUNXI_RTWI_BRG_REG

#define SUNXI_RTWI_BRG_REG (SUNXI_CCU_BASE + 0x091c)

◆ SUNXI_SID_BASE

#define SUNXI_SID_BASE 0x07091000

◆ SUNXI_SID_SRAM_BASE

#define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)

◆ SUNXI_SMHC0_BASE

#define SUNXI_SMHC0_BASE 0x04020000

◆ SUNXI_SMHC1_BASE

#define SUNXI_SMHC1_BASE 0x04021000

◆ SUNXI_SPI0_BASE

#define SUNXI_SPI0_BASE 0x04025000

◆ SUNXI_SPI1_BASE

#define SUNXI_SPI1_BASE 0x04026000

◆ SUNXI_SPI_FLASH_BASE

#define SUNXI_SPI_FLASH_BASE 0x04F00000

◆ SUNXI_SPI_FLASH_XIP_BASE

#define SUNXI_SPI_FLASH_XIP_BASE 0x10000000

◆ SUNXI_SPIF_BASE

#define SUNXI_SPIF_BASE (SUNXI_SPI_FLASH_BASE)

◆ SUNXI_SPINLOCK_BASE

#define SUNXI_SPINLOCK_BASE 0x03005000

◆ SUNXI_SQPI_PSRAM_XIP_BASE

#define SUNXI_SQPI_PSRAM_XIP_BASE 0x12000000

◆ SUNXI_SQPI_PSRAMC_BASE

#define SUNXI_SQPI_PSRAMC_BASE 0x03043000

◆ SUNXI_SRAM_C_BASE

#define SUNXI_SRAM_C_BASE 0x00020000

◆ SUNXI_SS_BASE

#define SUNXI_SS_BASE (SUNXI_CE_BASE)

◆ SUNXI_SYSCRL_BASE

#define SUNXI_SYSCRL_BASE (SUNXI_SYSCTRL_BASE)

◆ SUNXI_SYSCTRL_BASE

#define SUNXI_SYSCTRL_BASE 0x03000000

◆ SUNXI_TCON_LCD0_BASE

#define SUNXI_TCON_LCD0_BASE 0x05461000

◆ SUNXI_THS_BASE

#define SUNXI_THS_BASE 0x02009400

◆ SUNXI_TIMER_BASE

#define SUNXI_TIMER_BASE 0x02050000

◆ SUNXI_TWI0_BASE

#define SUNXI_TWI0_BASE 0x02502000

◆ SUNXI_TWI1_BASE

#define SUNXI_TWI1_BASE 0x02502400

◆ SUNXI_TWI2_BASE

#define SUNXI_TWI2_BASE 0x02502800

◆ SUNXI_TWI3_BASE

#define SUNXI_TWI3_BASE 0x02502C00

◆ SUNXI_UART0_BASE

#define SUNXI_UART0_BASE 0x02500000

◆ SUNXI_UART1_BASE

#define SUNXI_UART1_BASE 0x02500400

◆ SUNXI_UART2_BASE

#define SUNXI_UART2_BASE 0x02500800

◆ SUNXI_UART3_BASE

#define SUNXI_UART3_BASE 0x02500C00

◆ SUNXI_USB0_BASE

#define SUNXI_USB0_BASE 0x04100000

◆ SUNXI_VE_BASE

#define SUNXI_VE_BASE 0x01C0E000

◆ SUNXI_WDOG_KEY_FILED

#define SUNXI_WDOG_KEY_FILED 0x16AA0000

◆ SUNXI_WDOG_MODE_REG

#define SUNXI_WDOG_MODE_REG 0x18

◆ SYSRTC_BOOTFLAG_REG

#define SYSRTC_BOOTFLAG_REG 0x02A0

◆ VCC33_DET_CTRL_REG

#define VCC33_DET_CTRL_REG (0x1f4)

◆ VCCIO_DET_BYPASS_EN

#define VCCIO_DET_BYPASS_EN (1 << 0)

◆ VCCIO_THRESHOLD_MASK

#define VCCIO_THRESHOLD_MASK (0xff)

◆ VCCIO_THRESHOLD_VOLTAGE_2_5

#define VCCIO_THRESHOLD_VOLTAGE_2_5 (0 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_6

#define VCCIO_THRESHOLD_VOLTAGE_2_6 (1 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_7

#define VCCIO_THRESHOLD_VOLTAGE_2_7 (2 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_8

#define VCCIO_THRESHOLD_VOLTAGE_2_8 (3 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_9

#define VCCIO_THRESHOLD_VOLTAGE_2_9 (4 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_3_0

#define VCCIO_THRESHOLD_VOLTAGE_3_0 (5 << 4)

Macros