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/* SPDX-License-Identifier: GPL-2.0+ */


#ifndef __CACHE_H__

#define __CACHE_H__


#include <stdint.h>

#include "barrier.h"

#include "csr.h"


void cache_init(void);


void dcache_enable(void);


void icache_enable(void);


void flush_dcache_range(uint64_t start, uint64_t end);


void invalidate_dcache_range(uint64_t start, uint64_t end);


void flush_dcache_all();


void invalidate_dcache_all();


#endif /* __CACHE_H__ */

invalidate_dcache_all
static void invalidate_dcache_all()
Invalidate the entire data cache.
Definition cache.h:218

flush_dcache_range
static void flush_dcache_range(uint64_t start, uint64_t end)
Flush a range of addresses from the data cache.
Definition cache.h:173

invalidate_dcache_range
static void invalidate_dcache_range(uint64_t start, uint64_t end)
Invalidate a range of addresses in the data cache.
Definition cache.h:193

flush_dcache_all
static void flush_dcache_all()
Flush (clean) the entire data cache.
Definition cache.h:213

uint64_t
u64_t uint64_t
Definition stdint.h:16

csr.h

barrier.h
Memory barrier definitions for RISC-V architecture.

cache_init
void cache_init(void)
Initialize the cache configuration.
Definition cache.c:190

dcache_enable
void dcache_enable(void)
Enable the data cache.
Definition cache.c:201

icache_enable
void icache_enable(void)
Enable the instruction cache.
Definition cache.c:211

stdint.h