reg-ccu.h

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2013-2025
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * 
 * original from bsp uboot defines
 */
 
#ifndef __SUN55IW6_REG_CCU_H__
#define __SUN55IW6_REG_CCU_H__
 
#include <reg-ncat.h>
 
#define PLL_DDR_CTRL_REG 0x00000020//PLL_DDR Control Register
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_DDR_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_DDR_PAT0_CTRL_REG 0x00000028//PLL_DDR Pattern0 Control Register
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_DDR_PAT1_CTRL_REG 0x0000002c//PLL_DDR Pattern1 Control Register
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_DDR_BIAS_REG 0x00000030//PLL_DDR Bias Register
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_PERI0_CTRL_REG 0x000000a0//PLL_PERI0 Control Register
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8//PLL_PERI0 Pattern0 Control Register
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac//PLL_PERI0 Pattern1 Control Register
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI0_BIAS_REG 0x000000b0//PLL_PERI0 Bias Register
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_PERI1_CTRL_REG 0x000000c0//PLL_PERI1 Control Register
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8//PLL_PERI1 Pattern0 Control Register
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc//PLL_PERI1 Pattern1 Control Register
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_PERI1_BIAS_REG 0x000000d0//PLL_PERI1 Bias Register
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VIDEO0_CTRL_REG 0x00000120//PLL_VIDEO0 Control Register
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128//PLL_VIDEO0 Pattern0 Control Register
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c//PLL_VIDEO0 Pattern1 Control Register
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO0_BIAS_REG 0x00000130//PLL_VIDEO0 Bias Register
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VIDEO1_CTRL_REG 0x00000140//PLL_VIDEO1 Control Register
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET 16
#define PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148//PLL_VIDEO1 Pattern0 Control Register
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c//PLL_VIDEO1 Pattern1 Control Register
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VIDEO1_BIAS_REG 0x00000150//PLL_VIDEO1 Bias Register
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_VE_CTRL_REG 0x00000220//PLL_VE Control Register
#define PLL_VE_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VE_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VE_CTRL_REG_LOCK_OFFSET 28
#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VE_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VE_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_VE_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_VE_PAT0_CTRL_REG 0x00000228//PLL_VE Pattern0 Control Register
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_VE_PAT1_CTRL_REG 0x0000022c//PLL_VE Pattern1 Control Register
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_VE_BIAS_REG 0x00000230//PLL_VE Bias Register
#define PLL_VE_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_AUDIO0_CTRL_REG 0x00000260//PLL_AUDIO0 Control Register
#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET 16
#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000
#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268//PLL_AUDIO0 Pattern0 Control Register
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c//PLL_AUDIO0 Pattern1 Control Register
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO0_BIAS_REG 0x00000270//PLL_AUDIO0 Bias Register
#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_AUDIO1_CTRL_REG 0x00000280//PLL_AUDIO1 Control Register
#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_P_OFFSET 16
#define PLL_AUDIO1_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000
#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001
 
#define PLL_AUDIO1_PAT0_CTRL_REG 0x00000288//PLL_AUDIO1 Pattern0 Control Register
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO1_PAT1_CTRL_REG 0x0000028c//PLL_AUDIO1 Pattern1 Control Register
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_AUDIO1_BIAS_REG 0x00000290//PLL_AUDIO1 Bias Register
#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define PLL_NPU_CTRL_REG 0x000002a0//PLL_NPU Control Register
#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_NPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_NPU_CTRL_REG_PLL_P0_OFFSET 20
#define PLL_NPU_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000
#define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
 
#define PLL_NPU_PAT0_CTRL_REG 0x000002a8//PLL_NPU Pattern0 Control Register
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1
#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff
 
#define PLL_NPU_PAT1_CTRL_REG 0x000002ac//PLL_NPU Pattern1 Control Register
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff
 
#define PLL_NPU_BIAS_REG 0x000002b0//PLL_NPU Bias Register
#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000
 
#define AHB_CLK_REG 0x00000500//AHB Clock Register
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0b01
#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define AHB_CLK_REG_FACTOR_M_OFFSET 0
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB0_CLK_REG 0x00000510//APB0 Clock Register
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB0_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0b01
#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB0_CLK_REG_FACTOR_M_OFFSET 0
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB1_CLK_REG 0x00000518//APB1 Clock Register
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB1_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0b01
#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11
#define APB1_CLK_REG_FACTOR_M_OFFSET 0
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define APB_UART_CLK_REG 0x00000538//APB_UART Clock Register
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define APB_UART_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K 0b001
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100
#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define TRACE_CLK_REG 0x00000540//TRACE Clock Register
#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK 0x80000000
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0b0
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0b1
#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define TRACE_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0b01
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11
#define TRACE_CLK_REG_FACTOR_M_OFFSET 0
#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GIC_CLK_REG 0x00000560//GIC Clock Register
#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31
#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK 0x80000000
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0b0
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0b1
#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GIC_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0b001
#define GIC_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101
#define GIC_CLK_REG_FACTOR_M_OFFSET 0
#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define ITS0_BGR_REG 0x00000574//ITS0 Bus Gating Reset Register
#define ITS0_BGR_REG_ITS0_RST_OFFSET 16
#define ITS0_BGR_REG_ITS0_RST_CLEAR_MASK 0x00010000
#define ITS0_BGR_REG_ITS0_RST_ASSERT 0b0
#define ITS0_BGR_REG_ITS0_RST_DE_ASSERT 0b1
#define ITS0_BGR_REG_ITS0_ACLK_GATING_OFFSET 1
#define ITS0_BGR_REG_ITS0_ACLK_GATING_CLEAR_MASK 0x00000002
#define ITS0_BGR_REG_ITS0_ACLK_GATING_MASK 0b0
#define ITS0_BGR_REG_ITS0_ACLK_GATING_PASS 0b1
#define ITS0_BGR_REG_ITS0_HCLK_GATING_OFFSET 0
#define ITS0_BGR_REG_ITS0_HCLK_GATING_CLEAR_MASK 0x00000001
#define ITS0_BGR_REG_ITS0_HCLK_GATING_MASK 0b0
#define ITS0_BGR_REG_ITS0_HCLK_GATING_PASS 0b1
 
#define NSI_CLK_REG 0x00000580//NSI Clock Register
#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31
#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK 0x80000000
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0
#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1
#define NSI_CLK_REG_NSI_RST_OFFSET 30
#define NSI_CLK_REG_NSI_RST_CLEAR_MASK 0x40000000
#define NSI_CLK_REG_NSI_RST_ASSERT 0b0
#define NSI_CLK_REG_NSI_RST_DE_ASSERT 0b1
#define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28
#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK 0x10000000
#define NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0
#define NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1
#define NSI_CLK_REG_NSI_UPD_OFFSET 27
#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK 0x08000000
#define NSI_CLK_REG_NSI_UPD_INVALID 0b0
#define NSI_CLK_REG_NSI_UPD_VALID 0b1
#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24
#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK 0x07000000
#define NSI_CLK_REG_NSI_CLK_SEL_HOSC 0b000
#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL 0b001
#define NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL4X 0b010
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS 0b011
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b100
#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M 0b101
#define NSI_CLK_REG_NSI_DIV1_OFFSET 0
#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK 0x0000001f
 
#define NSI_BGR_REG 0x00000584//NSI Bus Gating Reset Register
#define NSI_BGR_REG_NSI_CFG_RST_OFFSET 16
#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK 0x00010000
#define NSI_BGR_REG_NSI_CFG_RST_ASSERT 0b0
#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT 0b1
#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0
#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK 0x00000001
#define NSI_BGR_REG_NSI_CFG_GATING_MASK 0b0
#define NSI_BGR_REG_NSI_CFG_GATING_PASS 0b1
 
#define MBUS_CLK_REG 0x00000588//MBUS Clock Register
#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK 0x80000000
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0
#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1
#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28
#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK 0x10000000
#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0
#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1
#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27
#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK 0x08000000
#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0
#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1
#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24
#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK 0x07000000
#define MBUS_CLK_REG_MBUS_CLK_SEL_HOSC 0b000
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS 0b001
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b010
#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b011
#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL 0b100
#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL 0b101
#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0
#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK 0x0000001f
 
#define IOMMU_BGR_REG 0x0000058c//IOMMU Bus Gating Reset Register
#define IOMMU_BGR_REG_IOMMU_GATING_OFFSET 0
#define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK 0x00000001
#define IOMMU_BGR_REG_IOMMU_GATING_MASK 0b0
#define IOMMU_BGR_REG_IOMMU_GATING_PASS 0b1
 
#define AHB_GATE_EN_REG 0x000005c0//AHB Gate Enable Register
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000
#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0
#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET 22
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET 19
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET 18
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET 17
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET 16
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 15
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00008000
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 14
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00004000
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 13
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00002000
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_OFFSET 12
#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00001000
#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_OFFSET 11
#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000800
#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000040
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000020
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET 4
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000010
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0b1
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET 1
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE 0b0
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE 0b1
 
#define MBUS_GATE_EN_REG 0x000005e0//MBUS Gate Enable Register
#define MBUS_GATE_EN_REG_CAN_MCLK_EN_OFFSET 17
#define MBUS_GATE_EN_REG_CAN_MCLK_EN_CLEAR_MASK 0x00020000
#define MBUS_GATE_EN_REG_CAN_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_CAN_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET 12
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK 0x00001000
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET 11
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK 0x00000800
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET 9
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK 0x00000200
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET 8
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK 0x00000100
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_OFFSET 5
#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_CLEAR_MASK 0x00000020
#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET 3
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK 0x00000008
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET 2
#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK 0x00000004
#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG 0b1
#define MBUS_GATE_EN_REG_VE_MCLK_EN_OFFSET 1
#define MBUS_GATE_EN_REG_VE_MCLK_EN_CLEAR_MASK 0x00000002
#define MBUS_GATE_EN_REG_VE_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_VE_MCLK_EN_PASS 0b1
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET 0
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK 0x00000001
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK 0b0
#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS 0b1
 
#define MBUS_MAT_CLK_GATING_REG 0x000005e4//MBUS Master Clock Gating Register
#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_OFFSET 27
#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_OFFSET 26
#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x04000000
#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 24
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK 0x01000000
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_OFFSET 23
#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 22
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_OFFSET 21
#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00200000
#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 20
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_OFFSET 19
#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET 18
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE 0b1
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET 17
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE 0b0
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE 0b1
 
#define DMA0_BGR_REG 0x00000704//DMA0 Bus Gating Reset Register
#define DMA0_BGR_REG_DMA0_RST_OFFSET 16
#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK 0x00010000
#define DMA0_BGR_REG_DMA0_RST_ASSERT 0b0
#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT 0b1
#define DMA0_BGR_REG_DMA0_GATING_OFFSET 0
#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK 0x00000001
#define DMA0_BGR_REG_DMA0_GATING_MASK 0b0
#define DMA0_BGR_REG_DMA0_GATING_PASS 0b1
 
#define DMA1_BGR_REG 0x0000070c//DMA1 Bus Gating Reset Register
#define DMA1_BGR_REG_DMA1_RST_OFFSET 16
#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK 0x00010000
#define DMA1_BGR_REG_DMA1_RST_ASSERT 0b0
#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT 0b1
#define DMA1_BGR_REG_DMA1_GATING_OFFSET 0
#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK 0x00000001
#define DMA1_BGR_REG_DMA1_GATING_MASK 0b0
#define DMA1_BGR_REG_DMA1_GATING_PASS 0b1
 
#define SPINLOCK_BGR_REG 0x00000724//SPINLOCK Bus Gating Reset Register
#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16
#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK 0x00010000
#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0b0
#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0b1
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK 0x00000001
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0b0
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0b1
 
#define MSGBOX0_BGR_REG 0x00000744//MSGBOX0 Bus Gating Reset Register
#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16
#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK 0x00010000
#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT 0b0
#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT 0b1
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK 0x00000001
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK 0b0
#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS 0b1
 
#define MSGBOX_CORE0_BGR_REG 0x0000074c//MSGBOX_CORE0 Bus Gating Reset Register
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_OFFSET 16
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_CLEAR_MASK 0x00010000
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_ASSERT 0b0
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_DE_ASSERT 0b1
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_OFFSET 0
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_MASK 0b0
#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_PASS 0b1
 
#define MSGBOX_CORE1_BGR_REG 0x00000754//MSGBOX_CORE1 Bus Gating Reset Register
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_OFFSET 16
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_CLEAR_MASK 0x00010000
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_ASSERT 0b0
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_DE_ASSERT 0b1
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_OFFSET 0
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_MASK 0b0
#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_PASS 0b1
 
#define MSGBOX_CORE2_BGR_REG 0x0000075c//MSGBOX_CORE2 Bus Gating Reset Register
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_OFFSET 16
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_CLEAR_MASK 0x00010000
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_ASSERT 0b0
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_DE_ASSERT 0b1
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_OFFSET 0
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_MASK 0b0
#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_PASS 0b1
 
#define MSGBOX_CORE3_BGR_REG 0x00000764//MSGBOX_CORE3 Bus Gating Reset Register
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_OFFSET 16
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_CLEAR_MASK 0x00010000
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_ASSERT 0b0
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_DE_ASSERT 0b1
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_OFFSET 0
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_MASK 0b0
#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_PASS 0b1
 
#define MSGBOX_RV_BGR_REG 0x0000076c//MSGBOX_RV Bus Gating Reset Register
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_OFFSET 16
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_CLEAR_MASK 0x00010000
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_ASSERT 0b0
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_DE_ASSERT 0b1
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_OFFSET 0
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_MASK 0b0
#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_PASS 0b1
 
#define PWM0_BGR_REG 0x00000784//PWM0 Bus Gating Reset Register
#define PWM0_BGR_REG_PWM0_RST_OFFSET 16
#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK 0x00010000
#define PWM0_BGR_REG_PWM0_RST_ASSERT 0b0
#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT 0b1
#define PWM0_BGR_REG_PWM0_GATING_OFFSET 0
#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK 0x00000001
#define PWM0_BGR_REG_PWM0_GATING_MASK 0b0
#define PWM0_BGR_REG_PWM0_GATING_PASS 0b1
 
#define PWM1_BGR_REG 0x0000078c//PWM1 Bus Gating Reset Register
#define PWM1_BGR_REG_PWM1_RST_OFFSET 16
#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK 0x00010000
#define PWM1_BGR_REG_PWM1_RST_ASSERT 0b0
#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT 0b1
#define PWM1_BGR_REG_PWM1_GATING_OFFSET 0
#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK 0x00000001
#define PWM1_BGR_REG_PWM1_GATING_MASK 0b0
#define PWM1_BGR_REG_PWM1_GATING_PASS 0b1
 
#define PWM2_BGR_REG 0x00000794//PWM2 Bus Gating Reset Register
#define PWM2_BGR_REG_PWM2_RST_OFFSET 16
#define PWM2_BGR_REG_PWM2_RST_CLEAR_MASK 0x00010000
#define PWM2_BGR_REG_PWM2_RST_ASSERT 0b0
#define PWM2_BGR_REG_PWM2_RST_DE_ASSERT 0b1
#define PWM2_BGR_REG_PWM2_GATING_OFFSET 0
#define PWM2_BGR_REG_PWM2_GATING_CLEAR_MASK 0x00000001
#define PWM2_BGR_REG_PWM2_GATING_MASK 0b0
#define PWM2_BGR_REG_PWM2_GATING_PASS 0b1
 
#define DBGSYS_BGR_REG 0x000007a4//DBGSYS Bus Gating Reset Register
#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16
#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK 0x00010000
#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0b0
#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0b1
#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0
#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK 0x00000001
#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0b0
#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0b1
 
#define SYSDAP_BGR_REG 0x000007ac//SYSDAP Bus Gating Reset Register
#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16
#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK 0x00010000
#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0b0
#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG 0b1
#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0
#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK 0x00000001
#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0b0
#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG 0b1
 
#define TIMER0_CLK_REG 0x00000800//TIMER0 Clock Register
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET 31
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE 0b0
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE 0b1
#define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER1_CLK_REG 0x00000804//TIMER1 Clock Register
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET 31
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE 0b0
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE 0b1
#define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER1_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER1_CLK_REG_FACTOR_M__1 0b000
#define TIMER1_CLK_REG_FACTOR_M__2 0b001
#define TIMER1_CLK_REG_FACTOR_M__4 0b010
#define TIMER1_CLK_REG_FACTOR_M__8 0b011
#define TIMER1_CLK_REG_FACTOR_M__16 0b100
#define TIMER1_CLK_REG_FACTOR_M__32 0b101
#define TIMER1_CLK_REG_FACTOR_M__64 0b110
#define TIMER1_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER2_CLK_REG 0x00000808//TIMER2 Clock Register
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET 31
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE 0b0
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE 0b1
#define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER2_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER2_CLK_REG_FACTOR_M__1 0b000
#define TIMER2_CLK_REG_FACTOR_M__2 0b001
#define TIMER2_CLK_REG_FACTOR_M__4 0b010
#define TIMER2_CLK_REG_FACTOR_M__8 0b011
#define TIMER2_CLK_REG_FACTOR_M__16 0b100
#define TIMER2_CLK_REG_FACTOR_M__32 0b101
#define TIMER2_CLK_REG_FACTOR_M__64 0b110
#define TIMER2_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER3_CLK_REG 0x0000080c//TIMER3 Clock Register
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET 31
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE 0b0
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE 0b1
#define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER3_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER3_CLK_REG_FACTOR_M__1 0b000
#define TIMER3_CLK_REG_FACTOR_M__2 0b001
#define TIMER3_CLK_REG_FACTOR_M__4 0b010
#define TIMER3_CLK_REG_FACTOR_M__8 0b011
#define TIMER3_CLK_REG_FACTOR_M__16 0b100
#define TIMER3_CLK_REG_FACTOR_M__32 0b101
#define TIMER3_CLK_REG_FACTOR_M__64 0b110
#define TIMER3_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER4_CLK_REG 0x00000810//TIMER4 Clock Register
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET 31
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE 0b0
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE 0b1
#define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER4_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER4_CLK_REG_FACTOR_M__1 0b000
#define TIMER4_CLK_REG_FACTOR_M__2 0b001
#define TIMER4_CLK_REG_FACTOR_M__4 0b010
#define TIMER4_CLK_REG_FACTOR_M__8 0b011
#define TIMER4_CLK_REG_FACTOR_M__16 0b100
#define TIMER4_CLK_REG_FACTOR_M__32 0b101
#define TIMER4_CLK_REG_FACTOR_M__64 0b110
#define TIMER4_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER5_CLK_REG 0x00000814//TIMER5 Clock Register
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET 31
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE 0b0
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE 0b1
#define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER5_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER5_CLK_REG_FACTOR_M__1 0b000
#define TIMER5_CLK_REG_FACTOR_M__2 0b001
#define TIMER5_CLK_REG_FACTOR_M__4 0b010
#define TIMER5_CLK_REG_FACTOR_M__8 0b011
#define TIMER5_CLK_REG_FACTOR_M__16 0b100
#define TIMER5_CLK_REG_FACTOR_M__32 0b101
#define TIMER5_CLK_REG_FACTOR_M__64 0b110
#define TIMER5_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER6_CLK_REG 0x00000818//TIMER6 Clock Register
#define TIMER6_CLK_REG_TIMER6_CLK_GATING_OFFSET 31
#define TIMER6_CLK_REG_TIMER6_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER6_CLK_REG_TIMER6_CLK_GATING_DISABLE 0b0
#define TIMER6_CLK_REG_TIMER6_CLK_GATING_ENABLE 0b1
#define TIMER6_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER6_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER6_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER6_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER6_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER6_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER6_CLK_REG_FACTOR_M__1 0b000
#define TIMER6_CLK_REG_FACTOR_M__2 0b001
#define TIMER6_CLK_REG_FACTOR_M__4 0b010
#define TIMER6_CLK_REG_FACTOR_M__8 0b011
#define TIMER6_CLK_REG_FACTOR_M__16 0b100
#define TIMER6_CLK_REG_FACTOR_M__32 0b101
#define TIMER6_CLK_REG_FACTOR_M__64 0b110
#define TIMER6_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER7_CLK_REG 0x0000081c//TIMER7 Clock Register
#define TIMER7_CLK_REG_TIMER7_CLK_GATING_OFFSET 31
#define TIMER7_CLK_REG_TIMER7_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER7_CLK_REG_TIMER7_CLK_GATING_DISABLE 0b0
#define TIMER7_CLK_REG_TIMER7_CLK_GATING_ENABLE 0b1
#define TIMER7_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER7_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER7_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER7_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER7_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER7_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER7_CLK_REG_FACTOR_M__1 0b000
#define TIMER7_CLK_REG_FACTOR_M__2 0b001
#define TIMER7_CLK_REG_FACTOR_M__4 0b010
#define TIMER7_CLK_REG_FACTOR_M__8 0b011
#define TIMER7_CLK_REG_FACTOR_M__16 0b100
#define TIMER7_CLK_REG_FACTOR_M__32 0b101
#define TIMER7_CLK_REG_FACTOR_M__64 0b110
#define TIMER7_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER_BGR_REG 0x00000850//TIMER Bus Gating Reset Register
#define TIMER_BGR_REG_TIMER_RST_OFFSET 16
#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK 0x00010000
#define TIMER_BGR_REG_TIMER_RST_ASSERT 0b0
#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT 0b1
#define TIMER_BGR_REG_TIMER_GATING_OFFSET 0
#define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK 0x00000001
#define TIMER_BGR_REG_TIMER_GATING_MASK 0b0
#define TIMER_BGR_REG_TIMER_GATING_PASS 0b1
 
#define TIMER0_RV_CLK_REG 0x00000860//RISC-V TIMER0 Clock Register
#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_OFFSET 31
#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_DISABLE 0b0
#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_ENABLE 0b1
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER0_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER0_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER0_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER0_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER0_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER0_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER0_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER0_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER1_RV_CLK_REG 0x00000864//RISC-V TIMER1 Clock Register
#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_OFFSET 31
#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_DISABLE 0b0
#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_ENABLE 0b1
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER1_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER1_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER1_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER1_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER1_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER1_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER1_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER1_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER1_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER1_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER2_RV_CLK_REG 0x00000868//RISC-V TIMER2 Clock Register
#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_OFFSET 31
#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_DISABLE 0b0
#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_ENABLE 0b1
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER2_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER2_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER2_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER2_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER2_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER2_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER2_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER2_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER2_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER2_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER3_RV_CLK_REG 0x0000086c//RISC-V TIMER3 Clock Register
#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_OFFSET 31
#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_DISABLE 0b0
#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_ENABLE 0b1
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define TIMER3_RV_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER3_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER3_RV_CLK_REG_FACTOR_M__1 0b000
#define TIMER3_RV_CLK_REG_FACTOR_M__2 0b001
#define TIMER3_RV_CLK_REG_FACTOR_M__4 0b010
#define TIMER3_RV_CLK_REG_FACTOR_M__8 0b011
#define TIMER3_RV_CLK_REG_FACTOR_M__16 0b100
#define TIMER3_RV_CLK_REG_FACTOR_M__32 0b101
#define TIMER3_RV_CLK_REG_FACTOR_M__64 0b110
#define TIMER3_RV_CLK_REG_FACTOR_M__128 0b111
 
#define TIMER_RV_BGR_REG 0x00000870//RISC-V TIMER Bus Gating Reset Register
#define TIMER_RV_BGR_REG_TIMER_RV_RST_OFFSET 16
#define TIMER_RV_BGR_REG_TIMER_RV_RST_CLEAR_MASK 0x00010000
#define TIMER_RV_BGR_REG_TIMER_RV_RST_ASSERT 0b0
#define TIMER_RV_BGR_REG_TIMER_RV_RST_DE_ASSERT 0b1
#define TIMER_RV_BGR_REG_TIMER_RV_GATING_OFFSET 0
#define TIMER_RV_BGR_REG_TIMER_RV_GATING_CLEAR_MASK 0x00000001
#define TIMER_RV_BGR_REG_TIMER_RV_GATING_MASK 0b0
#define TIMER_RV_BGR_REG_TIMER_RV_GATING_PASS 0b1
 
#define DE0_CLK_REG 0x00000a00//DE0 Clock Register
#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31
#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK 0x80000000
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0
#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1
#define DE0_CLK_REG_FACTOR_M_OFFSET 0
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DE0_BGR_REG 0x00000a04//DE0 Bus Gating Reset Register
#define DE0_BGR_REG_DE0_RST_OFFSET 16
#define DE0_BGR_REG_DE0_RST_CLEAR_MASK 0x00010000
#define DE0_BGR_REG_DE0_RST_ASSERT 0b0
#define DE0_BGR_REG_DE0_RST_DE_ASSERT 0b1
#define DE0_BGR_REG_DE0_GATING_OFFSET 0
#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK 0x00000001
#define DE0_BGR_REG_DE0_GATING_MASK 0b0
#define DE0_BGR_REG_DE0_GATING_PASS 0b1
 
#define G2D_CLK_REG 0x00000a40//G2D Clock Register
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1
#define G2D_CLK_REG_FACTOR_M_OFFSET 0
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define G2D_BGR_REG 0x00000a44//G2D Bus Gating Reset Register
#define G2D_BGR_REG_G2D_RST_OFFSET 16
#define G2D_BGR_REG_G2D_RST_CLEAR_MASK 0x00010000
#define G2D_BGR_REG_G2D_RST_ASSERT 0b0
#define G2D_BGR_REG_G2D_RST_DE_ASSERT 0b1
#define G2D_BGR_REG_G2D_GATING_OFFSET 0
#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK 0x00000001
#define G2D_BGR_REG_G2D_GATING_MASK 0b0
#define G2D_BGR_REG_G2D_GATING_PASS 0b1
 
#define DE_SYS_BGR_REG 0x00000a74//DE_SYS Bus Gating Reset Register
#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16
#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK 0x00010000
#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT 0b0
#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT 0b1
 
#define VE_CLK_REG 0x00000a80//VE Clock Register
#define VE_CLK_REG_VE_CLK_GATING_OFFSET 31
#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK 0x80000000
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF 0b0
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON 0b1
#define VE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VE_CLK_REG_CLK_SRC_SEL_VEPLL 0b000
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011
#define VE_CLK_REG_FACTOR_M_OFFSET 0
#define VE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define VE_BGR_REG 0x00000a8c//VE Bus Gating Reset Register
#define VE_BGR_REG_VE_RST_OFFSET 16
#define VE_BGR_REG_VE_RST_CLEAR_MASK 0x00010000
#define VE_BGR_REG_VE_RST_ASSERT 0b0
#define VE_BGR_REG_VE_RST_DE_ASSERT 0b1
#define VE_BGR_REG_VE_GATING_OFFSET 0
#define VE_BGR_REG_VE_GATING_CLEAR_MASK 0x00000001
#define VE_BGR_REG_VE_GATING_MASK 0b0
#define VE_BGR_REG_VE_GATING_PASS 0b1
 
#define CE_CLK_REG 0x00000ac0//CE Clock Register
#define CE_CLK_REG_CE_CLK_GATING_OFFSET 31
#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK 0x80000000
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0b0
#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG 0b1
#define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CE_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define CE_CLK_REG_FACTOR_M_OFFSET 0
#define CE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CE_BGR_REG 0x00000ac4//CE Bus Gating Reset Register
#define CE_BGR_REG_CE_SYS_RST_OFFSET 17
#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK 0x00020000
#define CE_BGR_REG_CE_SYS_RST_ASSERT 0b0
#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG 0b1
#define CE_BGR_REG_CE_RST_OFFSET 16
#define CE_BGR_REG_CE_RST_CLEAR_MASK 0x00010000
#define CE_BGR_REG_CE_RST_ASSERT 0b0
#define CE_BGR_REG_CE_RST_SECURE_DEBUG 0b1
#define CE_BGR_REG_CE_SYS_GATING_OFFSET 1
#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK 0x00000002
#define CE_BGR_REG_CE_SYS_GATING_MASK 0b0
#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG 0b1
#define CE_BGR_REG_CE_GATING_OFFSET 0
#define CE_BGR_REG_CE_GATING_CLEAR_MASK 0x00000001
#define CE_BGR_REG_CE_GATING_MASK 0b0
#define CE_BGR_REG_CE_GATING_SECURE_DEBUG 0b1
 
#define NPU_CLK_REG 0x00000b00//NPU Clock Register
#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31
#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK 0x80000000
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0b0
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0b1
#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL 0b000
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011
#define NPU_CLK_REG_FACTOR_M_OFFSET 0
#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define NPU_BGR_REG 0x00000b04//NPU Bus Gating Reset Register
#define NPU_BGR_REG_NPU_GLB_RST_OFFSET 19
#define NPU_BGR_REG_NPU_GLB_RST_CLEAR_MASK 0x00080000
#define NPU_BGR_REG_NPU_GLB_RST_ASSERT 0b0
#define NPU_BGR_REG_NPU_GLB_RST_DE_ASSERT 0b1
#define NPU_BGR_REG_NPU_AHB_RST_OFFSET 18
#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK 0x00040000
#define NPU_BGR_REG_NPU_AHB_RST_ASSERT 0b0
#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT 0b1
#define NPU_BGR_REG_NPU_AXI_RST_OFFSET 17
#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK 0x00020000
#define NPU_BGR_REG_NPU_AXI_RST_ASSERT 0b0
#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT 0b1
#define NPU_BGR_REG_NPU_CORE_RST_OFFSET 16
#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK 0x00010000
#define NPU_BGR_REG_NPU_CORE_RST_ASSERT 0b0
#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT 0b1
#define NPU_BGR_REG_NPU_TZMA_GATING_OFFSET 1
#define NPU_BGR_REG_NPU_TZMA_GATING_CLEAR_MASK 0x00000002
#define NPU_BGR_REG_NPU_TZMA_GATING_MASK 0b0
#define NPU_BGR_REG_NPU_TZMA_GATING_PASS 0b1
#define NPU_BGR_REG_NPU_GATING_OFFSET 0
#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK 0x00000001
#define NPU_BGR_REG_NPU_GATING_MASK 0b0
#define NPU_BGR_REG_NPU_GATING_PASS 0b1
 
#define RV_CORE_CLK_REG 0x00000b80//RISCV_CORE Clock Register
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_OFFSET 31
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLEAR_MASK 0x80000000
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_OFF 0b0
#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_ON 0b1
#define RV_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define RV_CORE_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100
#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101
#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_OFFSET 8
#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK 0x00000300
#define RV_CORE_CLK_REG_FACTOR_M_OFFSET 0
#define RV_CORE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define RV_TS_CLK_REG 0x00000b88//RISCV_TS Clock Register
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_OFFSET 31
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLEAR_MASK 0x80000000
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_OFF 0b0
#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_ON 0b1
#define RV_TS_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define RV_TS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define RV_TS_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define RV_TS_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001
#define RV_TS_CLK_REG_CLK_SRC_SEL_CLK32K 0b010
 
#define RV_SYS_BGR_REG 0x00000b94//RISCV_SYS Bus Gating Reset Register
#define RV_SYS_BGR_REG_RV_SYS_RST_OFFSET 17
#define RV_SYS_BGR_REG_RV_SYS_RST_CLEAR_MASK 0x00020000
#define RV_SYS_BGR_REG_RV_SYS_RST_ASSERT 0b0
#define RV_SYS_BGR_REG_RV_SYS_RST_DE_ASSERT 0b1
#define RV_SYS_BGR_REG_RV_CORE_RST_OFFSET 16
#define RV_SYS_BGR_REG_RV_CORE_RST_CLEAR_MASK 0x00010000
#define RV_SYS_BGR_REG_RV_CORE_RST_ASSERT 0b0
#define RV_SYS_BGR_REG_RV_CORE_RST_DE_ASSERT 0b1
 
#define RV_CFG_BGR_REG 0x00000b9c//RISCV_CFG Bus Gating Reset Register
#define RV_CFG_BGR_REG_RV_CFG_RST_OFFSET 16
#define RV_CFG_BGR_REG_RV_CFG_RST_CLEAR_MASK 0x00010000
#define RV_CFG_BGR_REG_RV_CFG_RST_ASSERT 0b0
#define RV_CFG_BGR_REG_RV_CFG_RST_DE_ASSERT 0b1
#define RV_CFG_BGR_REG_RV_CFG_GATING_OFFSET 0
#define RV_CFG_BGR_REG_RV_CFG_GATING_CLEAR_MASK 0x00000001
#define RV_CFG_BGR_REG_RV_CFG_GATING_MASK 0b0
#define RV_CFG_BGR_REG_RV_CFG_GATING_PASS 0b1
 
#define DRAM_CLK_REG 0x00000c00//DRAM Clock Register
#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK 0x80000000
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0b0
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0b1
#define DRAM_CLK_REG_DRAM_UPD_OFFSET 27
#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK 0x08000000
#define DRAM_CLK_REG_DRAM_UPD_INVALID 0b0
#define DRAM_CLK_REG_DRAM_UPD_VALID 0b1
#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK 0x07000000
#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0b000
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_800M 0b001
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M 0b010
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M 0b011
#define DRAM_CLK_REG_DRAM_CLK_SEL_NPUPLL 0b100
#define DRAM_CLK_REG_DRAM_CLK_SEL_HOSC 0b101
#define DRAM_CLK_REG_DRAM_DIV1_OFFSET 0
#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK 0x0000001f
 
#define DRAM_BGR_REG 0x00000c0c//DRAM Bus Gating Reset Register
#define DRAM_BGR_REG_DRAM_RST_OFFSET 16
#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK 0x00010000
#define DRAM_BGR_REG_DRAM_RST_ASSERT 0b0
#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT 0b1
#define DRAM_BGR_REG_DRAM_GATING_OFFSET 0
#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK 0x00000001
#define DRAM_BGR_REG_DRAM_GATING_MASK 0b0
#define DRAM_BGR_REG_DRAM_GATING_PASS 0b1
 
#define NAND0_CLK2X_CLK_REG 0x00000c80//NAND0 CLK2X Clock Register
#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_OFFSET 31
#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLEAR_MASK 0x80000000
#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_OFF 0b0
#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_ON 0b1
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define NAND0_CLK2X_CLK_REG_FACTOR_M_OFFSET 0
#define NAND0_CLK2X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define NAND0_CLK1_CLK_REG 0x00000c84//NAND0 CLK1 Clock Register
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK 0x80000000
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0b0
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0b1
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0
#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define NAND0_BGR_REG 0x00000c8c//NAND0 Bus Gating Reset Register
#define NAND0_BGR_REG_NAND0_RST_OFFSET 16
#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK 0x00010000
#define NAND0_BGR_REG_NAND0_RST_ASSERT 0b0
#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT 0b1
#define NAND0_BGR_REG_NAND0_GATING_OFFSET 0
#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK 0x00000001
#define NAND0_BGR_REG_NAND0_GATING_MASK 0b0
#define NAND0_BGR_REG_NAND0_GATING_PASS 0b1
 
#define SMHC0_CLK_REG 0x00000d00//SMHC0 Clock Register
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC0_BGR_REG 0x00000d0c//SMHC0 Bus Gating Reset Register
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET 16
#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK 0x00010000
#define SMHC0_BGR_REG_SMHC0_RST_ASSERT 0b0
#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT 0b1
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0
#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK 0x00000001
#define SMHC0_BGR_REG_SMHC0_GATING_MASK 0b0
#define SMHC0_BGR_REG_SMHC0_GATING_PASS 0b1
 
#define SMHC1_CLK_REG 0x00000d10//SMHC1 Clock Register
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100
#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC1_BGR_REG 0x00000d1c//SMHC1 Bus Gating Reset Register
#define SMHC1_BGR_REG_SMHC1_RST_OFFSET 16
#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK 0x00010000
#define SMHC1_BGR_REG_SMHC1_RST_ASSERT 0b0
#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT 0b1
#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0
#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK 0x00000001
#define SMHC1_BGR_REG_SMHC1_GATING_MASK 0b0
#define SMHC1_BGR_REG_SMHC1_GATING_PASS 0b1
 
#define SMHC2_CLK_REG 0x00000d20//SMHC2 Clock Register
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100
#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SMHC2_BGR_REG 0x00000d2c//SMHC2 Bus Gating Reset Register
#define SMHC2_BGR_REG_SMHC2_RST_OFFSET 16
#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK 0x00010000
#define SMHC2_BGR_REG_SMHC2_RST_ASSERT 0b0
#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT 0b1
#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0
#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK 0x00000001
#define SMHC2_BGR_REG_SMHC2_GATING_MASK 0b0
#define SMHC2_BGR_REG_SMHC2_GATING_PASS 0b1
 
#define UART0_BGR_REG 0x00000e00//UART0 Bus Gating Reset Register
#define UART0_BGR_REG_UART0_RST_OFFSET 16
#define UART0_BGR_REG_UART0_RST_CLEAR_MASK 0x00010000
#define UART0_BGR_REG_UART0_RST_ASSERT 0b0
#define UART0_BGR_REG_UART0_RST_DE_ASSERT 0b1
#define UART0_BGR_REG_UART0_GATING_OFFSET 0
#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK 0x00000001
#define UART0_BGR_REG_UART0_GATING_MASK 0b0
#define UART0_BGR_REG_UART0_GATING_PASS 0b1
 
#define UART1_BGR_REG 0x00000e04//UART1 Bus Gating Reset Register
#define UART1_BGR_REG_UART1_RST_OFFSET 16
#define UART1_BGR_REG_UART1_RST_CLEAR_MASK 0x00010000
#define UART1_BGR_REG_UART1_RST_ASSERT 0b0
#define UART1_BGR_REG_UART1_RST_DE_ASSERT 0b1
#define UART1_BGR_REG_UART1_GATING_OFFSET 0
#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK 0x00000001
#define UART1_BGR_REG_UART1_GATING_MASK 0b0
#define UART1_BGR_REG_UART1_GATING_PASS 0b1
 
#define UART2_BGR_REG 0x00000e08//UART2 Bus Gating Reset Register
#define UART2_BGR_REG_UART2_RST_OFFSET 16
#define UART2_BGR_REG_UART2_RST_CLEAR_MASK 0x00010000
#define UART2_BGR_REG_UART2_RST_ASSERT 0b0
#define UART2_BGR_REG_UART2_RST_DE_ASSERT 0b1
#define UART2_BGR_REG_UART2_GATING_OFFSET 0
#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK 0x00000001
#define UART2_BGR_REG_UART2_GATING_MASK 0b0
#define UART2_BGR_REG_UART2_GATING_PASS 0b1
 
#define UART3_BGR_REG 0x00000e0c//UART3 Bus Gating Reset Register
#define UART3_BGR_REG_UART3_RST_OFFSET 16
#define UART3_BGR_REG_UART3_RST_CLEAR_MASK 0x00010000
#define UART3_BGR_REG_UART3_RST_ASSERT 0b0
#define UART3_BGR_REG_UART3_RST_DE_ASSERT 0b1
#define UART3_BGR_REG_UART3_GATING_OFFSET 0
#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK 0x00000001
#define UART3_BGR_REG_UART3_GATING_MASK 0b0
#define UART3_BGR_REG_UART3_GATING_PASS 0b1
 
#define UART4_BGR_REG 0x00000e10//UART4 Bus Gating Reset Register
#define UART4_BGR_REG_UART4_RST_OFFSET 16
#define UART4_BGR_REG_UART4_RST_CLEAR_MASK 0x00010000
#define UART4_BGR_REG_UART4_RST_ASSERT 0b0
#define UART4_BGR_REG_UART4_RST_DE_ASSERT 0b1
#define UART4_BGR_REG_UART4_GATING_OFFSET 0
#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK 0x00000001
#define UART4_BGR_REG_UART4_GATING_MASK 0b0
#define UART4_BGR_REG_UART4_GATING_PASS 0b1
 
#define UART5_BGR_REG 0x00000e14//UART5 Bus Gating Reset Register
#define UART5_BGR_REG_UART5_RST_OFFSET 16
#define UART5_BGR_REG_UART5_RST_CLEAR_MASK 0x00010000
#define UART5_BGR_REG_UART5_RST_ASSERT 0b0
#define UART5_BGR_REG_UART5_RST_DE_ASSERT 0b1
#define UART5_BGR_REG_UART5_GATING_OFFSET 0
#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK 0x00000001
#define UART5_BGR_REG_UART5_GATING_MASK 0b0
#define UART5_BGR_REG_UART5_GATING_PASS 0b1
 
#define UART6_BGR_REG 0x00000e18//UART6 Bus Gating Reset Register
#define UART6_BGR_REG_UART6_RST_OFFSET 16
#define UART6_BGR_REG_UART6_RST_CLEAR_MASK 0x00010000
#define UART6_BGR_REG_UART6_RST_ASSERT 0b0
#define UART6_BGR_REG_UART6_RST_DE_ASSERT 0b1
#define UART6_BGR_REG_UART6_GATING_OFFSET 0
#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK 0x00000001
#define UART6_BGR_REG_UART6_GATING_MASK 0b0
#define UART6_BGR_REG_UART6_GATING_PASS 0b1
 
#define UART7_BGR_REG 0x00000e20//UART7 Bus Gating Reset Register
#define UART7_BGR_REG_UART7_RST_OFFSET 16
#define UART7_BGR_REG_UART7_RST_CLEAR_MASK 0x00010000
#define UART7_BGR_REG_UART7_RST_ASSERT 0b0
#define UART7_BGR_REG_UART7_RST_DE_ASSERT 0b1
#define UART7_BGR_REG_UART7_GATING_OFFSET 0
#define UART7_BGR_REG_UART7_GATING_CLEAR_MASK 0x00000001
#define UART7_BGR_REG_UART7_GATING_MASK 0b0
#define UART7_BGR_REG_UART7_GATING_PASS 0b1
 
#define UART8_BGR_REG 0x00000e24//UART8 Bus Gating Reset Register
#define UART8_BGR_REG_UART8_RST_OFFSET 16
#define UART8_BGR_REG_UART8_RST_CLEAR_MASK 0x00010000
#define UART8_BGR_REG_UART8_RST_ASSERT 0b0
#define UART8_BGR_REG_UART8_RST_DE_ASSERT 0b1
#define UART8_BGR_REG_UART8_GATING_OFFSET 0
#define UART8_BGR_REG_UART8_GATING_CLEAR_MASK 0x00000001
#define UART8_BGR_REG_UART8_GATING_MASK 0b0
#define UART8_BGR_REG_UART8_GATING_PASS 0b1
 
#define UART9_BGR_REG 0x00000e28//UART9 Bus Gating Reset Register
#define UART9_BGR_REG_UART9_RST_OFFSET 16
#define UART9_BGR_REG_UART9_RST_CLEAR_MASK 0x00010000
#define UART9_BGR_REG_UART9_RST_ASSERT 0b0
#define UART9_BGR_REG_UART9_RST_DE_ASSERT 0b1
#define UART9_BGR_REG_UART9_GATING_OFFSET 0
#define UART9_BGR_REG_UART9_GATING_CLEAR_MASK 0x00000001
#define UART9_BGR_REG_UART9_GATING_MASK 0b0
#define UART9_BGR_REG_UART9_GATING_PASS 0b1
 
#define UART10_BGR_REG 0x00000e2c//UART10 Bus Gating Reset Register
#define UART10_BGR_REG_UART10_RST_OFFSET 16
#define UART10_BGR_REG_UART10_RST_CLEAR_MASK 0x00010000
#define UART10_BGR_REG_UART10_RST_ASSERT 0b0
#define UART10_BGR_REG_UART10_RST_DE_ASSERT 0b1
#define UART10_BGR_REG_UART10_GATING_OFFSET 0
#define UART10_BGR_REG_UART10_GATING_CLEAR_MASK 0x00000001
#define UART10_BGR_REG_UART10_GATING_MASK 0b0
#define UART10_BGR_REG_UART10_GATING_PASS 0b1
 
#define UART11_BGR_REG 0x00000e30//UART11 Bus Gating Reset Register
#define UART11_BGR_REG_UART11_RST_OFFSET 16
#define UART11_BGR_REG_UART11_RST_CLEAR_MASK 0x00010000
#define UART11_BGR_REG_UART11_RST_ASSERT 0b0
#define UART11_BGR_REG_UART11_RST_DE_ASSERT 0b1
#define UART11_BGR_REG_UART11_GATING_OFFSET 0
#define UART11_BGR_REG_UART11_GATING_CLEAR_MASK 0x00000001
#define UART11_BGR_REG_UART11_GATING_MASK 0b0
#define UART11_BGR_REG_UART11_GATING_PASS 0b1
 
#define UART12_BGR_REG 0x00000e34//UART12 Bus Gating Reset Register
#define UART12_BGR_REG_UART12_RST_OFFSET 16
#define UART12_BGR_REG_UART12_RST_CLEAR_MASK 0x00010000
#define UART12_BGR_REG_UART12_RST_ASSERT 0b0
#define UART12_BGR_REG_UART12_RST_DE_ASSERT 0b1
#define UART12_BGR_REG_UART12_GATING_OFFSET 0
#define UART12_BGR_REG_UART12_GATING_CLEAR_MASK 0x00000001
#define UART12_BGR_REG_UART12_GATING_MASK 0b0
#define UART12_BGR_REG_UART12_GATING_PASS 0b1
 
#define UART13_BGR_REG 0x00000e38//UART13 Bus Gating Reset Register
#define UART13_BGR_REG_UART13_RST_OFFSET 16
#define UART13_BGR_REG_UART13_RST_CLEAR_MASK 0x00010000
#define UART13_BGR_REG_UART13_RST_ASSERT 0b0
#define UART13_BGR_REG_UART13_RST_DE_ASSERT 0b1
#define UART13_BGR_REG_UART13_GATING_OFFSET 0
#define UART13_BGR_REG_UART13_GATING_CLEAR_MASK 0x00000001
#define UART13_BGR_REG_UART13_GATING_MASK 0b0
#define UART13_BGR_REG_UART13_GATING_PASS 0b1
 
#define UART14_BGR_REG 0x00000e3c//UART14 Bus Gating Reset Register
#define UART14_BGR_REG_UART14_RST_OFFSET 16
#define UART14_BGR_REG_UART14_RST_CLEAR_MASK 0x00010000
#define UART14_BGR_REG_UART14_RST_ASSERT 0b0
#define UART14_BGR_REG_UART14_RST_DE_ASSERT 0b1
#define UART14_BGR_REG_UART14_GATING_OFFSET 0
#define UART14_BGR_REG_UART14_GATING_CLEAR_MASK 0x00000001
#define UART14_BGR_REG_UART14_GATING_MASK 0b0
#define UART14_BGR_REG_UART14_GATING_PASS 0b1
 
#define TWI0_BGR_REG 0x00000e80//TWI0 Bus Gating Reset Register
#define TWI0_BGR_REG_TWI0_RST_OFFSET 16
#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK 0x00010000
#define TWI0_BGR_REG_TWI0_RST_ASSERT 0b0
#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT 0b1
#define TWI0_BGR_REG_TWI0_GATING_OFFSET 0
#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK 0x00000001
#define TWI0_BGR_REG_TWI0_GATING_MASK 0b0
#define TWI0_BGR_REG_TWI0_GATING_PASS 0b1
 
#define TWI1_BGR_REG 0x00000e84//TWI1 Bus Gating Reset Register
#define TWI1_BGR_REG_TWI1_RST_OFFSET 16
#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK 0x00010000
#define TWI1_BGR_REG_TWI1_RST_ASSERT 0b0
#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT 0b1
#define TWI1_BGR_REG_TWI1_GATING_OFFSET 0
#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK 0x00000001
#define TWI1_BGR_REG_TWI1_GATING_MASK 0b0
#define TWI1_BGR_REG_TWI1_GATING_PASS 0b1
 
#define TWI2_BGR_REG 0x00000e88//TWI2 Bus Gating Reset Register
#define TWI2_BGR_REG_TWI2_RST_OFFSET 16
#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK 0x00010000
#define TWI2_BGR_REG_TWI2_RST_ASSERT 0b0
#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT 0b1
#define TWI2_BGR_REG_TWI2_GATING_OFFSET 0
#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK 0x00000001
#define TWI2_BGR_REG_TWI2_GATING_MASK 0b0
#define TWI2_BGR_REG_TWI2_GATING_PASS 0b1
 
#define TWI3_BGR_REG 0x00000e8c//TWI3 Bus Gating Reset Register
#define TWI3_BGR_REG_TWI3_RST_OFFSET 16
#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK 0x00010000
#define TWI3_BGR_REG_TWI3_RST_ASSERT 0b0
#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT 0b1
#define TWI3_BGR_REG_TWI3_GATING_OFFSET 0
#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK 0x00000001
#define TWI3_BGR_REG_TWI3_GATING_MASK 0b0
#define TWI3_BGR_REG_TWI3_GATING_PASS 0b1
 
#define TWI4_BGR_REG 0x00000e90//TWI4 Bus Gating Reset Register
#define TWI4_BGR_REG_TWI4_RST_OFFSET 16
#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK 0x00010000
#define TWI4_BGR_REG_TWI4_RST_ASSERT 0b0
#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT 0b1
#define TWI4_BGR_REG_TWI4_GATING_OFFSET 0
#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK 0x00000001
#define TWI4_BGR_REG_TWI4_GATING_MASK 0b0
#define TWI4_BGR_REG_TWI4_GATING_PASS 0b1
 
#define TWI5_BGR_REG 0x00000e94//TWI5 Bus Gating Reset Register
#define TWI5_BGR_REG_TWI5_RST_OFFSET 16
#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK 0x00010000
#define TWI5_BGR_REG_TWI5_RST_ASSERT 0b0
#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT 0b1
#define TWI5_BGR_REG_TWI5_GATING_OFFSET 0
#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK 0x00000001
#define TWI5_BGR_REG_TWI5_GATING_MASK 0b0
#define TWI5_BGR_REG_TWI5_GATING_PASS 0b1
 
#define TWI6_BGR_REG 0x00000e98//TWI6 Bus Gating Reset Register
#define TWI6_BGR_REG_TWI6_RST_OFFSET 16
#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK 0x00010000
#define TWI6_BGR_REG_TWI6_RST_ASSERT 0b0
#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT 0b1
#define TWI6_BGR_REG_TWI6_GATING_OFFSET 0
#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK 0x00000001
#define TWI6_BGR_REG_TWI6_GATING_MASK 0b0
#define TWI6_BGR_REG_TWI6_GATING_PASS 0b1
 
#define SPI0_CLK_REG 0x00000f00//SPI0 Clock Register
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI0_CLK_REG_FACTOR_N_OFFSET 8
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI0_CLK_REG_FACTOR_M_OFFSET 0
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI0_BGR_REG 0x00000f04//SPI0 Bus Gating Reset Register
#define SPI0_BGR_REG_SPI0_RST_OFFSET 16
#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK 0x00010000
#define SPI0_BGR_REG_SPI0_RST_ASSERT 0b0
#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT 0b1
#define SPI0_BGR_REG_SPI0_GATING_OFFSET 0
#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK 0x00000001
#define SPI0_BGR_REG_SPI0_GATING_MASK 0b0
#define SPI0_BGR_REG_SPI0_GATING_PASS 0b1
 
#define SPI1_CLK_REG 0x00000f08//SPI1 Clock Register
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI1_CLK_REG_FACTOR_N_OFFSET 8
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI1_CLK_REG_FACTOR_M_OFFSET 0
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI1_BGR_REG 0x00000f0c//SPI1 Bus Gating Reset Register
#define SPI1_BGR_REG_SPI1_RST_OFFSET 16
#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK 0x00010000
#define SPI1_BGR_REG_SPI1_RST_ASSERT 0b0
#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT 0b1
#define SPI1_BGR_REG_SPI1_GATING_OFFSET 0
#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK 0x00000001
#define SPI1_BGR_REG_SPI1_GATING_MASK 0b0
#define SPI1_BGR_REG_SPI1_GATING_PASS 0b1
 
#define SPI2_CLK_REG 0x00000f10//SPI2 Clock Register
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI2_CLK_REG_FACTOR_N_OFFSET 8
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI2_CLK_REG_FACTOR_M_OFFSET 0
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI2_BGR_REG 0x00000f14//SPI2 Bus Gating Reset Register
#define SPI2_BGR_REG_SPI2_RST_OFFSET 16
#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK 0x00010000
#define SPI2_BGR_REG_SPI2_RST_ASSERT 0b0
#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT 0b1
#define SPI2_BGR_REG_SPI2_GATING_OFFSET 0
#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK 0x00000001
#define SPI2_BGR_REG_SPI2_GATING_MASK 0b0
#define SPI2_BGR_REG_SPI2_GATING_PASS 0b1
 
#define SPIF_CLK_REG 0x00000f18//SPIF Clock Register
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK 0x80000000
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b101
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b110
#define SPIF_CLK_REG_FACTOR_N_OFFSET 8
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPIF_CLK_REG_FACTOR_M_OFFSET 0
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPIF_BGR_REG 0x00000f1c//SPIF Bus Gating Reset Register
#define SPIF_BGR_REG_SPIF_RST_OFFSET 16
#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK 0x00010000
#define SPIF_BGR_REG_SPIF_RST_ASSERT 0b0
#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT 0b1
#define SPIF_BGR_REG_SPIF_GATING_OFFSET 0
#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK 0x00000001
#define SPIF_BGR_REG_SPIF_GATING_MASK 0b0
#define SPIF_BGR_REG_SPIF_GATING_PASS 0b1
 
#define SPI3_CLK_REG 0x00000f20//SPI3 Clock Register
#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI3_CLK_REG_FACTOR_N_OFFSET 8
#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI3_CLK_REG_FACTOR_M_OFFSET 0
#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI3_BGR_REG 0x00000f24//SPI3 Bus Gating Reset Register
#define SPI3_BGR_REG_SPI3_RST_OFFSET 16
#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK 0x00010000
#define SPI3_BGR_REG_SPI3_RST_ASSERT 0b0
#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT 0b1
#define SPI3_BGR_REG_SPI3_GATING_OFFSET 0
#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK 0x00000001
#define SPI3_BGR_REG_SPI3_GATING_MASK 0b0
#define SPI3_BGR_REG_SPI3_GATING_PASS 0b1
 
#define SPI4_CLK_REG 0x00000f28//SPI4 Clock Register
#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET 31
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF 0b0
#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON 0b1
#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101
#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110
#define SPI4_CLK_REG_FACTOR_N_OFFSET 8
#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPI4_CLK_REG_FACTOR_M_OFFSET 0
#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SPI4_BGR_REG 0x00000f2c//SPI4 Bus Gating Reset Register
#define SPI4_BGR_REG_SPI4_RST_OFFSET 16
#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK 0x00010000
#define SPI4_BGR_REG_SPI4_RST_ASSERT 0b0
#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT 0b1
#define SPI4_BGR_REG_SPI4_GATING_OFFSET 0
#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK 0x00000001
#define SPI4_BGR_REG_SPI4_GATING_MASK 0b0
#define SPI4_BGR_REG_SPI4_GATING_PASS 0b1
 
#define GPADC0_CLK_REG 0x00000fc0//GPADC0 Clock Register
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET 31
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPADC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC0_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GPADC0_BGR_REG 0x00000fc4//GPADC0 Bus Gating Reset Register
#define GPADC0_BGR_REG_GPADC0_RST_OFFSET 16
#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK 0x00010000
#define GPADC0_BGR_REG_GPADC0_RST_ASSERT 0b0
#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT 0b1
#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0
#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK 0x00000001
#define GPADC0_BGR_REG_GPADC0_GATING_MASK 0b0
#define GPADC0_BGR_REG_GPADC0_GATING_PASS 0b1
 
#define GPADC1_CLK_REG 0x00000fc8//GPADC1 Clock Register
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_OFFSET 31
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPADC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define GPADC1_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC1_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GPADC1_BGR_REG 0x00000fcc//GPADC1 Bus Gating Reset Register
#define GPADC1_BGR_REG_GPADC1_RST_OFFSET 16
#define GPADC1_BGR_REG_GPADC1_RST_CLEAR_MASK 0x00010000
#define GPADC1_BGR_REG_GPADC1_RST_ASSERT 0b0
#define GPADC1_BGR_REG_GPADC1_RST_DE_ASSERT 0b1
#define GPADC1_BGR_REG_GPADC1_GATING_OFFSET 0
#define GPADC1_BGR_REG_GPADC1_GATING_CLEAR_MASK 0x00000001
#define GPADC1_BGR_REG_GPADC1_GATING_MASK 0b0
#define GPADC1_BGR_REG_GPADC1_GATING_PASS 0b1
 
#define GPADC2_CLK_REG 0x00000fd0//GPADC2 Clock Register
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_OFFSET 31
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPADC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define GPADC2_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC2_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GPADC2_BGR_REG 0x00000fd4//GPADC2 Bus Gating Reset Register
#define GPADC2_BGR_REG_GPADC2_RST_OFFSET 16
#define GPADC2_BGR_REG_GPADC2_RST_CLEAR_MASK 0x00010000
#define GPADC2_BGR_REG_GPADC2_RST_ASSERT 0b0
#define GPADC2_BGR_REG_GPADC2_RST_DE_ASSERT 0b1
#define GPADC2_BGR_REG_GPADC2_GATING_OFFSET 0
#define GPADC2_BGR_REG_GPADC2_GATING_CLEAR_MASK 0x00000001
#define GPADC2_BGR_REG_GPADC2_GATING_MASK 0b0
#define GPADC2_BGR_REG_GPADC2_GATING_PASS 0b1
 
#define GPADC3_CLK_REG 0x00000fd8//GPADC3 Clock Register
#define GPADC3_CLK_REG_GPADC3_CLK_GATING_OFFSET 31
#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_OFF 0b0
#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_ON 0b1
#define GPADC3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPADC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPADC3_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define GPADC3_CLK_REG_CLK_SRC_SEL_CLK48M 0b001
#define GPADC3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010
#define GPADC3_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GPADC3_BGR_REG 0x00000fdc//GPADC3 Bus Gating Reset Register
#define GPADC3_BGR_REG_GPADC3_RST_OFFSET 16
#define GPADC3_BGR_REG_GPADC3_RST_CLEAR_MASK 0x00010000
#define GPADC3_BGR_REG_GPADC3_RST_ASSERT 0b0
#define GPADC3_BGR_REG_GPADC3_RST_DE_ASSERT 0b1
#define GPADC3_BGR_REG_GPADC3_GATING_OFFSET 0
#define GPADC3_BGR_REG_GPADC3_GATING_CLEAR_MASK 0x00000001
#define GPADC3_BGR_REG_GPADC3_GATING_MASK 0b0
#define GPADC3_BGR_REG_GPADC3_GATING_PASS 0b1
 
#define THS_BGR_REG 0x00000fe4//THS Bus Gating Reset Register
#define THS_BGR_REG_THS_RST_OFFSET 16
#define THS_BGR_REG_THS_RST_CLEAR_MASK 0x00010000
#define THS_BGR_REG_THS_RST_ASSERT 0b0
#define THS_BGR_REG_THS_RST_DE_ASSERT 0b1
#define THS_BGR_REG_THS_GATING_OFFSET 0
#define THS_BGR_REG_THS_GATING_CLEAR_MASK 0x00000001
#define THS_BGR_REG_THS_GATING_MASK 0b0
#define THS_BGR_REG_THS_GATING_PASS 0b1
 
#define IRRX0_CLK_REG 0x00001000//IRRX0 Clock Register
#define IRRX0_CLK_REG_IRRX0_CLK_GATING_OFFSET 31
#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLEAR_MASK 0x80000000
#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_OFF 0b0
#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_ON 0b1
#define IRRX0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRRX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define IRRX0_CLK_REG_CLK_SRC_SEL_CLK32K 0b0
#define IRRX0_CLK_REG_CLK_SRC_SEL_HOSC 0b1
#define IRRX0_CLK_REG_FACTOR_M_OFFSET 0
#define IRRX0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IRRX0_BGR_REG 0x00001004//IRRX0 Bus Gating Reset Register
#define IRRX0_BGR_REG_IRRX0_RST_OFFSET 16
#define IRRX0_BGR_REG_IRRX0_RST_CLEAR_MASK 0x00010000
#define IRRX0_BGR_REG_IRRX0_RST_ASSERT 0b0
#define IRRX0_BGR_REG_IRRX0_RST_DE_ASSERT 0b1
#define IRRX0_BGR_REG_IRRX0_GATING_OFFSET 0
#define IRRX0_BGR_REG_IRRX0_GATING_CLEAR_MASK 0x00000001
#define IRRX0_BGR_REG_IRRX0_GATING_MASK 0b0
#define IRRX0_BGR_REG_IRRX0_GATING_PASS 0b1
 
#define IRTX_CLK_REG 0x00001008//IRTX Clock Register
#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK 0x80000000
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0b0
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0b1
#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b1
#define IRTX_CLK_REG_FACTOR_M_OFFSET 0
#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IRTX_BGR_REG 0x0000100c//IRTX Bus Gating Reset Register
#define IRTX_BGR_REG_IRTX_RST_OFFSET 16
#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK 0x00010000
#define IRTX_BGR_REG_IRTX_RST_ASSERT 0b0
#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0b1
#define IRTX_BGR_REG_IRTX_GATING_OFFSET 0
#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK 0x00000001
#define IRTX_BGR_REG_IRTX_GATING_MASK 0b0
#define IRTX_BGR_REG_IRTX_GATING_PASS 0b1
 
#define LRADC_BGR_REG 0x00001024//LRADC Bus Gating Reset Register
#define LRADC_BGR_REG_LRADC_RST_OFFSET 16
#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK 0x00010000
#define LRADC_BGR_REG_LRADC_RST_ASSERT 0b0
#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0b1
#define LRADC_BGR_REG_LRADC_GATING_OFFSET 0
#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK 0x00000001
#define LRADC_BGR_REG_LRADC_GATING_MASK 0b0
#define LRADC_BGR_REG_LRADC_GATING_PASS 0b1
 
#define TPADC_24M_CLK_REG 0x00001030//TPADC 24M Clock Register
#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_OFFSET 31
#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLEAR_MASK 0x80000000
#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_OFF 0b0
#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_ON 0b1
#define TPADC_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TPADC_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define TPADC_24M_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define TPADC_24M_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b1
#define TPADC_24M_CLK_REG_FACTOR_M_OFFSET 0
#define TPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define TPADC_BGR_REG 0x00001034//TPADC Bus Gating Reset Register
#define TPADC_BGR_REG_TPADC_RST_OFFSET 16
#define TPADC_BGR_REG_TPADC_RST_CLEAR_MASK 0x00010000
#define TPADC_BGR_REG_TPADC_RST_ASSERT 0b0
#define TPADC_BGR_REG_TPADC_RST_DE_ASSERT 0b1
#define TPADC_BGR_REG_TPADC_GATING_OFFSET 0
#define TPADC_BGR_REG_TPADC_GATING_CLEAR_MASK 0x00000001
#define TPADC_BGR_REG_TPADC_GATING_MASK 0b0
#define TPADC_BGR_REG_TPADC_GATING_PASS 0b1
 
#define LBC_CLK_REG 0x00001040//LBC Clock Register
#define LBC_CLK_REG_LBC_CLK_GATING_OFFSET 31
#define LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK 0x80000000
#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF 0b0
#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON 0b1
#define LBC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011
#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100
#define LBC_CLK_REG_FACTOR_N_OFFSET 8
#define LBC_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define LBC_CLK_REG_FACTOR_M_OFFSET 0
#define LBC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define LBC_NSI_AHB_CLK_REG 0x00001048//LBC NSI AHB Clock Register
#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_OFFSET 31
#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLEAR_MASK 0x80000000
#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_OFF 0b0
#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_ON 0b1
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b01
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b10
#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11
#define LBC_NSI_AHB_CLK_REG_FACTOR_M_OFFSET 0
#define LBC_NSI_AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define LBC_BGR_REG 0x0000104c//LBC Bus Gating Reset Register
#define LBC_BGR_REG_LBC_RST_OFFSET 16
#define LBC_BGR_REG_LBC_RST_CLEAR_MASK 0x00010000
#define LBC_BGR_REG_LBC_RST_ASSERT 0b0
#define LBC_BGR_REG_LBC_RST_DE_ASSERT 0b1
#define LBC_BGR_REG_LBC_GATING_OFFSET 0
#define LBC_BGR_REG_LBC_GATING_CLEAR_MASK 0x00000001
#define LBC_BGR_REG_LBC_GATING_MASK 0b0
#define LBC_BGR_REG_LBC_GATING_PASS 0b1
 
#define IRRX1_CLK_REG 0x00001100//IRRX1 Clock Register
#define IRRX1_CLK_REG_IRRX1_CLK_GATING_OFFSET 31
#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLEAR_MASK 0x80000000
#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_OFF 0b0
#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_ON 0b1
#define IRRX1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRRX1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define IRRX1_CLK_REG_CLK_SRC_SEL_CLK32K 0b0
#define IRRX1_CLK_REG_CLK_SRC_SEL_HOSC 0b1
#define IRRX1_CLK_REG_FACTOR_M_OFFSET 0
#define IRRX1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IRRX1_BGR_REG 0x00001104//IRRX1 Bus Gating Reset Register
#define IRRX1_BGR_REG_IRRX1_RST_OFFSET 16
#define IRRX1_BGR_REG_IRRX1_RST_CLEAR_MASK 0x00010000
#define IRRX1_BGR_REG_IRRX1_RST_ASSERT 0b0
#define IRRX1_BGR_REG_IRRX1_RST_DE_ASSERT 0b1
#define IRRX1_BGR_REG_IRRX1_GATING_OFFSET 0
#define IRRX1_BGR_REG_IRRX1_GATING_CLEAR_MASK 0x00000001
#define IRRX1_BGR_REG_IRRX1_GATING_MASK 0b0
#define IRRX1_BGR_REG_IRRX1_GATING_PASS 0b1
 
#define IRRX2_CLK_REG 0x00001108//IRRX2 Clock Register
#define IRRX2_CLK_REG_IRRX2_CLK_GATING_OFFSET 31
#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLEAR_MASK 0x80000000
#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_OFF 0b0
#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_ON 0b1
#define IRRX2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRRX2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define IRRX2_CLK_REG_CLK_SRC_SEL_CLK32K 0b0
#define IRRX2_CLK_REG_CLK_SRC_SEL_HOSC 0b1
#define IRRX2_CLK_REG_FACTOR_M_OFFSET 0
#define IRRX2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IRRX2_BGR_REG 0x0000110c//IRRX2 Bus Gating Reset Register
#define IRRX2_BGR_REG_IRRX2_RST_OFFSET 16
#define IRRX2_BGR_REG_IRRX2_RST_CLEAR_MASK 0x00010000
#define IRRX2_BGR_REG_IRRX2_RST_ASSERT 0b0
#define IRRX2_BGR_REG_IRRX2_RST_DE_ASSERT 0b1
#define IRRX2_BGR_REG_IRRX2_GATING_OFFSET 0
#define IRRX2_BGR_REG_IRRX2_GATING_CLEAR_MASK 0x00000001
#define IRRX2_BGR_REG_IRRX2_GATING_MASK 0b0
#define IRRX2_BGR_REG_IRRX2_GATING_PASS 0b1
 
#define IRRX3_CLK_REG 0x00001110//IRRX3 Clock Register
#define IRRX3_CLK_REG_IRRX3_CLK_GATING_OFFSET 31
#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLEAR_MASK 0x80000000
#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_OFF 0b0
#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_ON 0b1
#define IRRX3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRRX3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define IRRX3_CLK_REG_CLK_SRC_SEL_CLK32K 0b0
#define IRRX3_CLK_REG_CLK_SRC_SEL_HOSC 0b1
#define IRRX3_CLK_REG_FACTOR_M_OFFSET 0
#define IRRX3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define IRRX3_BGR_REG 0x00001114//IRRX3 Bus Gating Reset Register
#define IRRX3_BGR_REG_IRRX3_RST_OFFSET 16
#define IRRX3_BGR_REG_IRRX3_RST_CLEAR_MASK 0x00010000
#define IRRX3_BGR_REG_IRRX3_RST_ASSERT 0b0
#define IRRX3_BGR_REG_IRRX3_RST_DE_ASSERT 0b1
#define IRRX3_BGR_REG_IRRX3_GATING_OFFSET 0
#define IRRX3_BGR_REG_IRRX3_GATING_CLEAR_MASK 0x00000001
#define IRRX3_BGR_REG_IRRX3_GATING_MASK 0b0
#define IRRX3_BGR_REG_IRRX3_GATING_PASS 0b1
 
#define I2SPCM0_CLK_REG 0x00001200//I2SPCM0 Clock Register
#define I2SPCM0_CLK_REG_SCLK_GATING_OFFSET 31
#define I2SPCM0_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0
#define I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001
#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET 0
#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2SPCM0_BGR_REG 0x0000120c//I2SPCM0 Bus Gating Reset Register
#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET 16
#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK 0x00010000
#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT 0b0
#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT 0b1
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET 0
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK 0x00000001
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK 0b0
#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS 0b1
 
#define I2SPCM1_CLK_REG 0x00001210//I2SPCM1 Clock Register
#define I2SPCM1_CLK_REG_SCLK_GATING_OFFSET 31
#define I2SPCM1_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0
#define I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001
#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0
#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2SPCM1_BGR_REG 0x0000121c//I2SPCM1 Bus Gating Reset Register
#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16
#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK 0x00010000
#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT 0b0
#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT 0b1
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK 0x00000001
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK 0b0
#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS 0b1
 
#define I2SPCM2_CLK_REG 0x00001220//I2SPCM2 Clock Register
#define I2SPCM2_CLK_REG_SCLK_GATING_OFFSET 31
#define I2SPCM2_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0
#define I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001
#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0
#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2SPCM2_BGR_REG 0x0000122c//I2SPCM2 Bus Gating Reset Register
#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16
#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK 0x00010000
#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT 0b0
#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT 0b1
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK 0x00000001
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK 0b0
#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS 0b1
 
#define I2SPCM3_CLK_REG 0x00001230//I2SPCM3 Clock Register
#define I2SPCM3_CLK_REG_SCLK_GATING_OFFSET 31
#define I2SPCM3_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0
#define I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001
#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010
#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0
#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define I2SPCM3_BGR_REG 0x0000123c//I2SPCM3 Bus Gating Reset Register
#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16
#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK 0x00010000
#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT 0b0
#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT 0b1
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK 0x00000001
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK 0b0
#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS 0b1
 
#define OWA_TX_CLK_REG 0x00001280//OWA TX Clock Register
#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_OFFSET 31
#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLEAR_MASK 0x80000000
#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0
#define OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1
#define OWA_TX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA_TX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define OWA_RX_CLK_REG 0x00001284//OWA RX Clock Register
#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_OFFSET 31
#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLEAR_MASK 0x80000000
#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_OFF 0b0
#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_ON 0b1
#define OWA_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define OWA_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b000
#define OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001
#define OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b010
#define OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b011
#define OWA_RX_CLK_REG_FACTOR_M_OFFSET 0
#define OWA_RX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define OWA_BGR_REG 0x0000128c//OWA Bus Gating Reset Register
#define OWA_BGR_REG_OWA_RST_OFFSET 16
#define OWA_BGR_REG_OWA_RST_CLEAR_MASK 0x00010000
#define OWA_BGR_REG_OWA_RST_ASSERT 0b0
#define OWA_BGR_REG_OWA_RST_DE_ASSERT 0b1
#define OWA_BGR_REG_OWA_GATING_OFFSET 0
#define OWA_BGR_REG_OWA_GATING_CLEAR_MASK 0x00000001
#define OWA_BGR_REG_OWA_GATING_MASK 0b0
#define OWA_BGR_REG_OWA_GATING_PASS 0b1
 
#define DMIC_CLK_REG 0x000012c0//DMIC Clock Register
#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK 0x80000000
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0
#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1
#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0
#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1
#define DMIC_CLK_REG_FACTOR_M_OFFSET 0
#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DMIC_BGR_REG 0x000012cc//DMIC Bus Gating Reset Register
#define DMIC_BGR_REG_DMIC_RST_OFFSET 16
#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK 0x00010000
#define DMIC_BGR_REG_DMIC_RST_ASSERT 0b0
#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT 0b1
#define DMIC_BGR_REG_DMIC_GATING_OFFSET 0
#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK 0x00000001
#define DMIC_BGR_REG_DMIC_GATING_MASK 0b0
#define DMIC_BGR_REG_DMIC_GATING_PASS 0b1
 
#define AUDIO_CODEC_DAC_1X_CLK_REG 0x000012e0//AUDIO CODEC DAC 1X Clock Register
#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_OFFSET 31
#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0
#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1
#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0
#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1
#define AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_OFFSET 0
#define AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define AUDIO_CODEC_BGR_REG 0x000012ec//AUDIO CODEC Bus Gating Reset Register
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET 16
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK 0x00010000
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT 0b0
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT 0b1
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET 0
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK 0x00000001
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK 0b0
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS 0b1
 
#define USB0_CLK_REG 0x00001300//USB0 Clock Register
#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1
#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET 30
#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK 0x40000000
#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT 0b0
#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT 0b1
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K 0b10
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC 0b11
 
#define USB0_BGR_REG 0x00001304//USB0 Bus Gating Reset Register
#define USB0_BGR_REG_USB20_0_DEVICE_RST_OFFSET 24
#define USB0_BGR_REG_USB20_0_DEVICE_RST_CLEAR_MASK 0x01000000
#define USB0_BGR_REG_USB20_0_DEVICE_RST_ASSERT 0b0
#define USB0_BGR_REG_USB20_0_DEVICE_RST_DE_ASSERT 0b1
#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_OFFSET 20
#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_CLEAR_MASK 0x00100000
#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_ASSERT 0b0
#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_DE_ASSERT 0b1
#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_OFFSET 16
#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_CLEAR_MASK 0x00010000
#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_ASSERT 0b0
#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_DE_ASSERT 0b1
#define USB0_BGR_REG_USB20_0_DEVICE_GATING_OFFSET 8
#define USB0_BGR_REG_USB20_0_DEVICE_GATING_CLEAR_MASK 0x00000100
#define USB0_BGR_REG_USB20_0_DEVICE_GATING_MASK 0b0
#define USB0_BGR_REG_USB20_0_DEVICE_GATING_PASS 0b1
#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_OFFSET 4
#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_CLEAR_MASK 0x00000010
#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_MASK 0b0
#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_PASS 0b1
#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_OFFSET 0
#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_CLEAR_MASK 0x00000001
#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_MASK 0b0
#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_PASS 0b1
 
#define USB1_CLK_REG 0x00001308//USB1 Clock Register
#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1
#define USB1_CLK_REG_USBPHY1_RSTN_OFFSET 30
#define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK 0x40000000
#define USB1_CLK_REG_USBPHY1_RSTN_ASSERT 0b0
#define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT 0b1
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K 0b10
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC 0b11
 
#define USB1_BGR_REG 0x0000130c//USB1 Bus Gating Reset Register
#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_OFFSET 20
#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_CLEAR_MASK 0x00100000
#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_ASSERT 0b0
#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_DE_ASSERT 0b1
#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_OFFSET 16
#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_CLEAR_MASK 0x00010000
#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_ASSERT 0b0
#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_DE_ASSERT 0b1
#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_OFFSET 4
#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_CLEAR_MASK 0x00000010
#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_MASK 0b0
#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_PASS 0b1
#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_OFFSET 0
#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_CLEAR_MASK 0x00000001
#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_MASK 0b0
#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_PASS 0b1
 
#define USB2_U2_REF_CLK_REG 0x00001348//USB2 U2 Reference Clock Register
#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31
#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON 0b1
 
#define USB2_SUSPEND_CLK_REG 0x00001350//USB2 SUSPEND Clock Register
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K 0b0
#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_HOSC 0b1
#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define USB2_MF_CLK_REG 0x00001354//USB2 MF Clock Register
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0
#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1
#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b01
#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b10
#define USB2_MF_CLK_REG_FACTOR_M_OFFSET 0
#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define USB2_BGR_REG 0x0000135c//USB2 Bus Gating Reset Register
#define USB2_BGR_REG_USB30_RST_OFFSET 16
#define USB2_BGR_REG_USB30_RST_CLEAR_MASK 0x00010000
#define USB2_BGR_REG_USB30_RST_ASSERT 0b0
#define USB2_BGR_REG_USB30_RST_DE_ASSERT 0b1
#define USB2_BGR_REG_USB30_GATING_OFFSET 0
#define USB2_BGR_REG_USB30_GATING_CLEAR_MASK 0x00000001
#define USB2_BGR_REG_USB30_GATING_MASK 0b0
#define USB2_BGR_REG_USB30_GATING_PASS 0b1
 
#define PCIE_AUX_CLK_REG 0x00001380//PCIE_AUX Clock Register
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET 31
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF 0b0
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON 0b1
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0b1
#define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET 0
#define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define PCIE_SLV_CLK_REG 0x00001384//PCIE Slave Clock Register
#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_OFFSET 31
#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_OFF 0b0
#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_ON 0b1
#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b0
#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1
#define PCIE_SLV_CLK_REG_FACTOR_M_OFFSET 0
#define PCIE_SLV_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define PCIE_BGR_REG 0x0000138c//PCIE Bus Gating Reset Register
#define PCIE_BGR_REG_PCIE_RST_OFFSET 17
#define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK 0x00020000
#define PCIE_BGR_REG_PCIE_RST_ASSERT 0b0
#define PCIE_BGR_REG_PCIE_RST_DE_ASSERT 0b1
#define PCIE_BGR_REG_PCIE_PWRUP_RST_OFFSET 16
#define PCIE_BGR_REG_PCIE_PWRUP_RST_CLEAR_MASK 0x00010000
#define PCIE_BGR_REG_PCIE_PWRUP_RST_ASSERT 0b0
#define PCIE_BGR_REG_PCIE_PWRUP_RST_DE_ASSERT 0b1
 
#define SERDES_PHY_CFG_CLK_REG 0x000013c0//SERDES PHY Configure Clock Register
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET 31
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK 0x80000000
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0
#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0
#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1
#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0
#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SERDES_PHY_REF_CLK_REG 0x000013c4//SERDES PHY Reference Clock Register
#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_OFFSET 31
#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0
#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1
#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1
#define SERDES_PHY_REF_CLK_REG_FACTOR_M_OFFSET 0
#define SERDES_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define SERDES_BGR_REG 0x000013cc//SERDES Bus Gating Reset Register
#define SERDES_BGR_REG_SERDES_NOPPU_RST_OFFSET 17
#define SERDES_BGR_REG_SERDES_NOPPU_RST_CLEAR_MASK 0x00020000
#define SERDES_BGR_REG_SERDES_NOPPU_RST_ASSERT 0b0
#define SERDES_BGR_REG_SERDES_NOPPU_RST_DE_ASSERT 0b1
#define SERDES_BGR_REG_SERDES_RST_OFFSET 16
#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK 0x00010000
#define SERDES_BGR_REG_SERDES_RST_ASSERT 0b0
#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT 0b1
 
#define SERDES_AXI_CLK_REG 0x000013e0//SERDES AXI Clock Register
#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_OFFSET 31
#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLEAR_MASK 0x80000000
#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_OFF 0b0
#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_ON 0b1
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_HOSC 0b00
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b01
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b10
#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b11
#define SERDES_AXI_CLK_REG_FACTOR_M_OFFSET 0
#define SERDES_AXI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC0_PHY_CLK_REG 0x00001400//GMAC0_PHY Clock Register
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC0_PTP_CLK_REG 0x00001404//GMAC0_PTP Clock Register
#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_OFFSET 31
#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1
#define GMAC0_PTP_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC0_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC0_BGR_REG 0x0000140c//GMAC0 Bus Gating Reset Register
#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17
#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK 0x00020000
#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT 0b0
#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT 0b1
#define GMAC0_BGR_REG_GMAC0_RST_OFFSET 16
#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK 0x00010000
#define GMAC0_BGR_REG_GMAC0_RST_ASSERT 0b0
#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT 0b1
#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0
#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK 0x00000001
#define GMAC0_BGR_REG_GMAC0_GATING_MASK 0b0
#define GMAC0_BGR_REG_GMAC0_GATING_PASS 0b1
 
#define GMAC1_PHY_CLK_REG 0x00001410//GMAC1_PHY Clock Register
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC1_PTP_CLK_REG 0x00001414//GMAC1_PTP Clock Register
#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_OFFSET 31
#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_OFF 0b0
#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_ON 0b1
#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1
#define GMAC1_PTP_CLK_REG_FACTOR_M_OFFSET 0
#define GMAC1_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define GMAC1_BGR_REG 0x0000141c//GMAC1 Bus Gating Reset Register
#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17
#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK 0x00020000
#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT 0b0
#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT 0b1
#define GMAC1_BGR_REG_GMAC1_RST_OFFSET 16
#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK 0x00010000
#define GMAC1_BGR_REG_GMAC1_RST_ASSERT 0b0
#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT 0b1
#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0
#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK 0x00000001
#define GMAC1_BGR_REG_GMAC1_GATING_MASKS 0b0
#define GMAC1_BGR_REG_GMAC1_GATING_PASS 0b1
 
#define VO0_TCONLCD0_CLK_REG 0x00001500//VO0_TCONLCD0 Clock Register
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0b0
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0b1
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b000
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b010
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define VO0_TCONLCD0_BGR_REG 0x00001504//VO0_TCONLCD0 Bus Gating Reset Register
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK 0x00010000
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0b0
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0b1
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK 0x00000001
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK 0b0
#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS 0b1
 
#define LVDS0_BGR_REG 0x00001544//LVDS0 Bus Gating Reset Register
#define LVDS0_BGR_REG_LVDS0_RST_OFFSET 16
#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK 0x00010000
#define LVDS0_BGR_REG_LVDS0_RST_ASSERT 0b0
#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT 0b1
 
#define DSI0_CLK_REG 0x00001580//DSI0 Clock Register
#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK 0x80000000
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0b1
#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DSI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010
#define DSI0_CLK_REG_FACTOR_M_OFFSET 0
#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DSI0_BGR_REG 0x00001584//DSI0 Bus Gating Reset Register
#define DSI0_BGR_REG_DSI0_RST_OFFSET 16
#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK 0x00010000
#define DSI0_BGR_REG_DSI0_RST_ASSERT 0b0
#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT 0b1
#define DSI0_BGR_REG_DSI0_GATING_OFFSET 0
#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK 0x00000001
#define DSI0_BGR_REG_DSI0_GATING_MASK 0b0
#define DSI0_BGR_REG_DSI0_GATING_PASS 0b1
 
#define VO0_COMBPHY0_CLK_REG 0x000015c0//VO0_COMBPHY0 Clock Register
#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_OFFSET 31
#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLEAR_MASK 0x80000000
#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0b0
#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0b1
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b010
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b011
#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b100
#define VO0_COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0
#define VO0_COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define DPSS_BGR_REG 0x000016c4//DPSS Bus Gating Reset Register
#define DPSS_BGR_REG_DPSS_RST_OFFSET 16
#define DPSS_BGR_REG_DPSS_RST_CLEAR_MASK 0x00010000
#define DPSS_BGR_REG_DPSS_RST_ASSERT 0b0
#define DPSS_BGR_REG_DPSS_RST_DE_ASSERT 0b1
#define DPSS_BGR_REG_DPSS_GATING_OFFSET 0
#define DPSS_BGR_REG_DPSS_GATING_CLEAR_MASK 0x00000001
#define DPSS_BGR_REG_DPSS_GATING_MASK 0b0
#define DPSS_BGR_REG_DPSS_GATING_PASS 0b1
 
#define VIDEO_OUT0_BGR_REG 0x000016e4//Video_out0 Bus Gating Reset Register
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK 0x00010000
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT 0b0
#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT 0b1
 
#define LEDC_CLK_REG 0x00001700//LEDC Clock Register
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1
#define LEDC_CLK_REG_FACTOR_M_OFFSET 0
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define LEDC_BGR_REG 0x00001704//LEDC Bus Gating Reset Register
#define LEDC_BGR_REG_LEDC_RST_OFFSET 16
#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK 0x00010000
#define LEDC_BGR_REG_LEDC_RST_ASSERT 0b0
#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0b1
#define LEDC_BGR_REG_LEDC_GATING_OFFSET 0
#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK 0x00000001
#define LEDC_BGR_REG_LEDC_GATING_MASK 0b0
#define LEDC_BGR_REG_LEDC_GATING_PASS 0b1
 
#define CSI_MASTER0_CLK_REG 0x00001800//CSI Master0 Clock Register
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_MASTER1_CLK_REG 0x00001804//CSI Master1 Clock Register
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_MASTER2_CLK_REG 0x00001808//CSI Master2 Clock Register
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_MASTER3_CLK_REG 0x0000180c//CSI Master3 Clock Register
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100
#define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_CLK_REG 0x00001840//CSI Clock Register
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b101
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b110
#define CSI_CLK_REG_CLK_SRC_SEL_VEPLL 0b111
#define CSI_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define CSI_BGR_REG 0x00001844//CSI Bus Gating Reset Register
#define CSI_BGR_REG_CSI_RST_OFFSET 16
#define CSI_BGR_REG_CSI_RST_CLEAR_MASK 0x00010000
#define CSI_BGR_REG_CSI_RST_ASSERT 0b0
#define CSI_BGR_REG_CSI_RST_DE_ASSERT 0b1
#define CSI_BGR_REG_CSI_GATING_OFFSET 0
#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK 0x00000001
#define CSI_BGR_REG_CSI_GATING_MASK 0b0
#define CSI_BGR_REG_CSI_GATING_PASS 0b1
 
#define ISP_CLK_REG 0x00001860//ISP Clock Register
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b010
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b100
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101
#define ISP_CLK_REG_CLK_SRC_SEL_VEPLL 0b110
#define ISP_CLK_REG_CLK_SRC_SEL_NPUPLL 0b111
#define ISP_CLK_REG_FACTOR_M_OFFSET 0
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f
 
#define ISP_BGR_REG 0x00001864//ISP Bus Gating Reset Register
#define ISP_BGR_REG_ISP_RST_OFFSET 16
#define ISP_BGR_REG_ISP_RST_CLEAR_MASK 0x00010000
#define ISP_BGR_REG_ISP_RST_ASSERT 0b0
#define ISP_BGR_REG_ISP_RST_DE_ASSERT 0b1
#define ISP_BGR_REG_ISP_GATING_OFFSET 0
#define ISP_BGR_REG_ISP_GATING_CLEAR_MASK 0x00000001
#define ISP_BGR_REG_ISP_GATING_MASK 0b0
#define ISP_BGR_REG_ISP_GATING_PASS 0b1
 
#define PERI0PLL_GATE_EN_REG 0x00001908//PERI0PLL Gate Enable Register
#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_OFFSET 31
#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI1PLL_GATE_EN_REG 0x0000190c//PERI1PLL Gate Enable Register
#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_OFFSET 31
#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK 0x04000000
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000800
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000400
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0
#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1
 
#define VIDEOPLL_GATE_EN_REG 0x00001910//VIDEOPLL Gate Enable Register
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00200000
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_OFFSET 20
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000020
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_OFFSET 4
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0
#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1
 
#define PERI0PLL_GATE_STAT_REG 0x00001988//PERI0PLL Gate Status Register
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 11
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK 0x00000800
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 10
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK 0x00000400
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 9
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK 0x00000200
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 8
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK 0x00000100
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 7
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK 0x00000080
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 6
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000040
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 5
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK 0x00000020
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 4
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000010
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 3
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK 0x00000008
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 2
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK 0x00000004
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 1
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK 0x00000002
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 0
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK 0x00000001
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0
#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1
 
#define PERI1PLL_GATE_STAT_REG 0x0000198c//PERI1PLL Gate Status Register
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 9
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK 0x00000200
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 8
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK 0x00000100
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 7
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK 0x00000080
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 6
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK 0x00000040
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 5
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000020
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 4
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK 0x00000010
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 3
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000008
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 2
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK 0x00000004
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 1
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK 0x00000002
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 0
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK 0x00000001
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0
#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1
 
#define VIDEOPLL_GATE_STAT_REG 0x00001998//VIDEOPLL Gate Status Register
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_OFFSET 17
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_CLEAR_MASK 0x00020000
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_OFFSET 16
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_CLEAR_MASK 0x00010000
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_OFFSET 1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_CLEAR_MASK 0x00000002
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_ENABLE 0b1
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_OFFSET 0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_CLEAR_MASK 0x00000001
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_DISABLE 0b0
#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_ENABLE 0b1
 
#define CLK24M_GATE_EN_REG 0x00001a00//CLK24M Gate Enable Register
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK 0x00000008
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0b0
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0b1
#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_OFFSET 0
#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_CLEAR_MASK 0x00000001
#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_DISABLE 0b0
#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_ENABLE 0b1
 
#define PERI1_FOCPU_EN_REG 0x00001a10//PERI1PLL_2X Fanout To CPU Enable Register
#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_OFFSET 0
#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_CLEAR_MASK 0x00000001
#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_DISABLE 0b0
#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_ENABLE 0b1
 
#define CM_VI_CFG_REG 0x00001b00//CM VI Enable Configuration Register
#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16
#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK 0x00030000
#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF 0b01
#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON 0b10
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE 0b0
#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE 0b1
 
#define CM_VE_CFG_REG 0x00001b10//CM VE Enable Configuration Register
#define CM_VE_CFG_REG_CM_VE_STATUS_OFFSET 16
#define CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK 0x00030000
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF 0b01
#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON 0b10
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET 0
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE 0b0
#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE 0b1
 
#define CM_NPU_CFG_REG 0x00001b1c//CM NPU Enable Configuration Register
#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16
#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK 0x00030000
#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF 0b01
#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON 0b10
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE 0b0
#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE 0b1
 
#define CM_SERDES_CFG_REG 0x00001b28//CM SERDES Enable Configuration Register
#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_OFFSET 16
#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_CLEAR_MASK 0x00030000
#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_OFF 0b01
#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_ON 0b10
#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_OFFSET 0
#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_DISABLE 0b0
#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_ENABLE 0b1
 
#define CM_VO_CFG_REG 0x00001b34//CM VO Enable Configuration Register
#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16
#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK 0x00030000
#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF 0b01
#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON 0b10
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE 0b0
#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE 0b1
 
#define CM_RV_CFG_REG 0x00001b40//CM RV Enable Configuration Register
#define CM_RV_CFG_REG_CM_RV_STATUS_OFFSET 16
#define CM_RV_CFG_REG_CM_RV_STATUS_CLEAR_MASK 0x00030000
#define CM_RV_CFG_REG_CM_RV_STATUS_POWER_OFF 0b01
#define CM_RV_CFG_REG_CM_RV_STATUS_POWER_ON 0b10
#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_OFFSET 0
#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_CLEAR_MASK 0x00000001
#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_DISABLE 0b0
#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_ENABLE 0b1
 
#define CCU_SEC_SWITCH_REG 0x00001f00//CCU Security Switch Register
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1
 
#define SYSDAP_REQ_CTRL_REG 0x00001f10//SYSDAP REQ Control Register
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK 0x00000001
 
#define PLL_CFG0_REG 0x00001f20//PLL Configuration0 Register
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff
 
#define PLL_CFG1_REG 0x00001f24//PLL Configuration1 Register
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff
 
#define PLL_CFG2_REG 0x00001f28//PLL Configuration2 Register
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff
 
#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c//PLL Lock Debug Control Register
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x00f00000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL 0b0000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0b0001
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL 0b0010
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL 0b0011
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0100
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0101
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL 0b0110
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0111
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0b1000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b1001
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL 0b1010
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL 0b1011
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_USBPLL 0b1100
 
#define CCU_FAN_GATE_REG 0x00001f30//CCU FANOUT CLOCK GATE Register
#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET 4
#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK 0x00000010
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1
 
#define CLK27M_FAN_REG 0x00001f34//CLK27M FANOUT Register
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f
 
#define CLK_FAN_REG 0x00001f38//CLK FANOUT Register
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1
#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0
#define CLK_FAN_REG_PCLK_DIV_OFFSET 0
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f
 
#define CCU_FAN_REG 0x00001f3c//CCU FANOUT Register
#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK 0x00800000
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK 0x00400000
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK 0x00200000
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0b0
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0b1
#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK 0x000001c0
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0b101
#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0b110
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK 0x00000038
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0b101
#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0b110
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK50M_FROM_PERI0_150M_3 0b111
#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK 0x00000007
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2 0b001
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 0b010
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO 0b011
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 0b100
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0b101
#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0b110
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK50M_FROM_PERI0_150M_3 0b111
 
#define BUS_CLK_DBG_REG 0x00001f50//Bus Clock Debug Register
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK 0x00000007
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK 0b000
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK 0b001
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK 0b010
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK 0b011
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK 0b100
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK 0b101
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR_CLK 0b110
#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_1_B0 0b111
 
#define CCU_VERSION_REG 0x00001ff0//CCU Version Register
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK 0xffff0000
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK 0x0000ffff
 
/* cfg list */
#define CCU_REG_PLL_C0_CPUX (SUNXI_CPU_PLL_CFG_BASE + 0x4)
#define CCU_REG_PLL_C0_DSU (SUNXI_CPU_PLL_CFG_BASE + 0x8)
#define CCU_REG_DSU_CLK (SUNXI_CPU_PLL_CFG_BASE + 0x4c)
 
#define CCU_APB_CFG_GREG (SUNXI_CCU_BASE + APB0_CLK_REG)
#define CCU_APB1_CFG_GREG (SUNXI_CCU_BASE + APB1_CLK_REG)
#define CCU_MBUS_CFG_REG (SUNXI_CCU_BASE + MBUS_CLK_REG)
#define CCU_NSI_CLK_GREG (SUNXI_CCU_BASE + NSI_CLK_REG)
#define CCU_NSI_BGR_REG (SUNXI_CCU_BASE + NSI_BGR_REG)
 
#define CCU_CE_CLK_REG (SUNXI_CCU_BASE + CE_CLK_REG)
#define CCU_CE_BGR_REG (SUNXI_CCU_BASE + CE_BGR_REG)
 
/*SYS*/
#define CCU_DMA_BGR_REG (SUNXI_CCU_BASE + DMA0_BGR_REG)
 
/* storage */
#define CCU_MBUS_MST_CLK_GATING_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)
 
#define CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG)
#define CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG)
#define CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG)
#define CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_BGR_REG)
 
/*normal interface*/
#define CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_BGR_REG)
 
/*CE */
#define CE_CLK_SRC_MASK (0x1)
#define CE_CLK_SRC_SEL_BIT CE_CLK_REG_CLK_SRC_SEL_OFFSET
#define CE_CLK_SRC CE_CLK_REG_CLK_SRC_SEL_PERI0_400M
 
#define CE_CLK_DIV_RATION_M_BIT CE_CLK_REG_FACTOR_M_OFFSET
#define CE_CLK_DIV_RATION_M_MASK CE_CLK_REG_FACTOR_M_CLEAR_MASK
#define CE_CLK_DIV_RATION_M (2)
 
#define CE_SCLK_ONOFF_BIT (31)
#define CE_SCLK_ON (1)
 
#define CE_GATING_BASE CCU_CE_BGR_REG
#define CE_GATING_PASS (1)
#define CE_GATING_BIT (0)
 
#define CE_RST_REG_BASE CCU_CE_BGR_REG
#define CE_RST_BIT CE_BGR_REG_CE_RST_OFFSET
#define CE_DEASSERT (1)
 
#define CE_SYS_GATING_BIT CE_BGR_REG_CE_GATING_MASK
#define CE_SYS_RST_BIT CE_BGR_REG_CE_SYS_RST_OFFSET
 
/*gpadc gate and reset reg*/
#define CCU_GPADC_CLK_REG (SUNXI_CCU_BASE + GPADC1_CLK_REG)
#define CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC1_BGR_REG)
 
/*lpadc gate and reset reg*/
#define CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + LRADC_BGR_REG)
 
#define APB0_CLK_REG_FACTOR_N_OFFSET 8
#define APB0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00000300
 
#endif// __SUN55IW6_REG_CCU_H__