#include <reg-ncat.h>

Include dependency graph for reg-ccu.h:

Macros
#define	PLL_DDR_CTRL_REG 0x00000020

#define	PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_DDR_CTRL_REG_LOCK_OFFSET 28

#define	PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_DDR_CTRL_REG_PLL_P0_OFFSET 20

#define	PLL_DDR_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

#define	PLL_DDR_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_DDR_PAT0_CTRL_REG 0x00000028

#define	PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_DDR_PAT1_CTRL_REG 0x0000002c

#define	PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_DDR_BIAS_REG 0x00000030

#define	PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_PERI0_CTRL_REG 0x000000a0

#define	PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_PERI0_CTRL_REG_LOCK_OFFSET 28

#define	PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20

#define	PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000

#define	PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16

#define	PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000

#define	PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2

#define	PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c

#define	PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_PERI0_PAT0_CTRL_REG 0x000000a8

#define	PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_PERI0_PAT1_CTRL_REG 0x000000ac

#define	PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_PERI0_BIAS_REG 0x000000b0

#define	PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_PERI1_CTRL_REG 0x000000c0

#define	PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_PERI1_CTRL_REG_LOCK_OFFSET 28

#define	PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20

#define	PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000

#define	PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16

#define	PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000

#define	PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2

#define	PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c

#define	PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_PERI1_PAT0_CTRL_REG 0x000000c8

#define	PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_PERI1_PAT1_CTRL_REG 0x000000cc

#define	PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_PERI1_BIAS_REG 0x000000d0

#define	PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_VIDEO0_CTRL_REG 0x00000120

#define	PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28

#define	PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET 20

#define	PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

#define	PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET 16

#define	PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000

#define	PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

#define	PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define	PLL_VIDEO0_PAT0_CTRL_REG 0x00000128

#define	PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c

#define	PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_VIDEO0_BIAS_REG 0x00000130

#define	PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_VIDEO1_CTRL_REG 0x00000140

#define	PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28

#define	PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET 20

#define	PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

#define	PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET 16

#define	PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000

#define	PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

#define	PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define	PLL_VIDEO1_PAT0_CTRL_REG 0x00000148

#define	PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c

#define	PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_VIDEO1_BIAS_REG 0x00000150

#define	PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_VE_CTRL_REG 0x00000220

#define	PLL_VE_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_VE_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_VE_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_VE_CTRL_REG_LOCK_OFFSET 28

#define	PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_VE_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_VE_CTRL_REG_PLL_P0_OFFSET 20

#define	PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

#define	PLL_VE_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_VE_PAT0_CTRL_REG 0x00000228

#define	PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_VE_PAT1_CTRL_REG 0x0000022c

#define	PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_VE_BIAS_REG 0x00000230

#define	PLL_VE_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_AUDIO0_CTRL_REG 0x00000260

#define	PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28

#define	PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET 16

#define	PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000

#define	PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

#define	PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define	PLL_AUDIO0_PAT0_CTRL_REG 0x00000268

#define	PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c

#define	PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_AUDIO0_BIAS_REG 0x00000270

#define	PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_AUDIO1_CTRL_REG 0x00000280

#define	PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28

#define	PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_AUDIO1_CTRL_REG_PLL_P_OFFSET 16

#define	PLL_AUDIO1_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000

#define	PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

#define	PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define	PLL_AUDIO1_PAT0_CTRL_REG 0x00000288

#define	PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_AUDIO1_PAT1_CTRL_REG 0x0000028c

#define	PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_AUDIO1_BIAS_REG 0x00000290

#define	PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	PLL_NPU_CTRL_REG 0x000002a0

#define	PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31

#define	PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

#define	PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0b0

#define	PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0b1

#define	PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30

#define	PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

#define	PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

#define	PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

#define	PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29

#define	PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

#define	PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

#define	PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

#define	PLL_NPU_CTRL_REG_LOCK_OFFSET 28

#define	PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

#define	PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0b0

#define	PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

#define	PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

#define	PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

#define	PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

#define	PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

#define	PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET 24

#define	PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

#define	PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

#define	PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

#define	PLL_NPU_CTRL_REG_PLL_P0_OFFSET 20

#define	PLL_NPU_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

#define	PLL_NPU_CTRL_REG_PLL_N_OFFSET 8

#define	PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

#define	PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

#define	PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

#define	PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

#define	PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

#define	PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

#define	PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

#define	PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

#define	PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

#define	PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

#define	PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

#define	PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define	PLL_NPU_PAT0_CTRL_REG 0x000002a8

#define	PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

#define	PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

#define	PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

#define	PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

#define	PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

#define	PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

#define	PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

#define	PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

#define	PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

#define	PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11

#define	PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

#define	PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define	PLL_NPU_PAT1_CTRL_REG 0x000002ac

#define	PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

#define	PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

#define	PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

#define	PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

#define	PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

#define	PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define	PLL_NPU_BIAS_REG 0x000002b0

#define	PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16

#define	PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define	AHB_CLK_REG 0x00000500

#define	AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define	AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define	AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define	AHB_CLK_REG_FACTOR_M_OFFSET 0

#define	AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	APB0_CLK_REG 0x00000510

#define	APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	APB0_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define	APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define	APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define	APB0_CLK_REG_FACTOR_M_OFFSET 0

#define	APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	APB1_CLK_REG 0x00000518

#define	APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	APB1_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define	APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define	APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

#define	APB1_CLK_REG_FACTOR_M_OFFSET 0

#define	APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	APB_UART_CLK_REG 0x00000538

#define	APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	APB_UART_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define	APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

#define	APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011

#define	APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100

#define	APB_UART_CLK_REG_FACTOR_M_OFFSET 0

#define	APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	TRACE_CLK_REG 0x00000540

#define	TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31

#define	TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK 0x80000000

#define	TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0b0

#define	TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0b1

#define	TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	TRACE_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

#define	TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

#define	TRACE_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11

#define	TRACE_CLK_REG_FACTOR_M_OFFSET 0

#define	TRACE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GIC_CLK_REG 0x00000560

#define	GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31

#define	GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK 0x80000000

#define	GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0b1

#define	GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	GIC_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

#define	GIC_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

#define	GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

#define	GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

#define	GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101

#define	GIC_CLK_REG_FACTOR_M_OFFSET 0

#define	GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	ITS0_BGR_REG 0x00000574

#define	ITS0_BGR_REG_ITS0_RST_OFFSET 16

#define	ITS0_BGR_REG_ITS0_RST_CLEAR_MASK 0x00010000

#define	ITS0_BGR_REG_ITS0_RST_ASSERT 0b0

#define	ITS0_BGR_REG_ITS0_RST_DE_ASSERT 0b1

#define	ITS0_BGR_REG_ITS0_ACLK_GATING_OFFSET 1

#define	ITS0_BGR_REG_ITS0_ACLK_GATING_CLEAR_MASK 0x00000002

#define	ITS0_BGR_REG_ITS0_ACLK_GATING_MASK 0b0

#define	ITS0_BGR_REG_ITS0_ACLK_GATING_PASS 0b1

#define	ITS0_BGR_REG_ITS0_HCLK_GATING_OFFSET 0

#define	ITS0_BGR_REG_ITS0_HCLK_GATING_CLEAR_MASK 0x00000001

#define	ITS0_BGR_REG_ITS0_HCLK_GATING_MASK 0b0

#define	ITS0_BGR_REG_ITS0_HCLK_GATING_PASS 0b1

#define	NSI_CLK_REG 0x00000580

#define	NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31

#define	NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK 0x80000000

#define	NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0

#define	NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1

#define	NSI_CLK_REG_NSI_RST_OFFSET 30

#define	NSI_CLK_REG_NSI_RST_CLEAR_MASK 0x40000000

#define	NSI_CLK_REG_NSI_RST_ASSERT 0b0

#define	NSI_CLK_REG_NSI_RST_DE_ASSERT 0b1

#define	NSI_CLK_REG_NSI_DFS_EN_OFFSET 28

#define	NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK 0x10000000

#define	NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0

#define	NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1

#define	NSI_CLK_REG_NSI_UPD_OFFSET 27

#define	NSI_CLK_REG_NSI_UPD_CLEAR_MASK 0x08000000

#define	NSI_CLK_REG_NSI_UPD_INVALID 0b0

#define	NSI_CLK_REG_NSI_UPD_VALID 0b1

#define	NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24

#define	NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK 0x07000000

#define	NSI_CLK_REG_NSI_CLK_SEL_HOSC 0b000

#define	NSI_CLK_REG_NSI_CLK_SEL_DDRPLL 0b001

#define	NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL4X 0b010

#define	NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS 0b011

#define	NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b100

#define	NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M 0b101

#define	NSI_CLK_REG_NSI_DIV1_OFFSET 0

#define	NSI_CLK_REG_NSI_DIV1_CLEAR_MASK 0x0000001f

#define	NSI_BGR_REG 0x00000584

#define	NSI_BGR_REG_NSI_CFG_RST_OFFSET 16

#define	NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK 0x00010000

#define	NSI_BGR_REG_NSI_CFG_RST_ASSERT 0b0

#define	NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT 0b1

#define	NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0

#define	NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK 0x00000001

#define	NSI_BGR_REG_NSI_CFG_GATING_MASK 0b0

#define	NSI_BGR_REG_NSI_CFG_GATING_PASS 0b1

#define	MBUS_CLK_REG 0x00000588

#define	MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31

#define	MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK 0x80000000

#define	MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0

#define	MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1

#define	MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28

#define	MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK 0x10000000

#define	MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0

#define	MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1

#define	MBUS_CLK_REG_MBUS_UPD_OFFSET 27

#define	MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK 0x08000000

#define	MBUS_CLK_REG_MBUS_UPD_INVALID 0b0

#define	MBUS_CLK_REG_MBUS_UPD_VALID 0b1

#define	MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24

#define	MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK 0x07000000

#define	MBUS_CLK_REG_MBUS_CLK_SEL_HOSC 0b000

#define	MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS 0b001

#define	MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b010

#define	MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b011

#define	MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL 0b100

#define	MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL 0b101

#define	MBUS_CLK_REG_MBUS_DIV1_OFFSET 0

#define	MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK 0x0000001f

#define	IOMMU_BGR_REG 0x0000058c

#define	IOMMU_BGR_REG_IOMMU_GATING_OFFSET 0

#define	IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK 0x00000001

#define	IOMMU_BGR_REG_IOMMU_GATING_MASK 0b0

#define	IOMMU_BGR_REG_IOMMU_GATING_PASS 0b1

#define	AHB_GATE_EN_REG 0x000005c0

#define	AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31

#define	AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000

#define	AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

#define	AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

#define	AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29

#define	AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000

#define	AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

#define	AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

#define	AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28

#define	AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK 0x10000000

#define	AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET 22

#define	AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00400000

#define	AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET 19

#define	AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00080000

#define	AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET 18

#define	AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00040000

#define	AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET 17

#define	AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00020000

#define	AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET 16

#define	AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000

#define	AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 15

#define	AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00008000

#define	AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 14

#define	AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00004000

#define	AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 13

#define	AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00002000

#define	AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_OFFSET 12

#define	AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00001000

#define	AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_OFFSET 11

#define	AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000800

#define	AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7

#define	AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080

#define	AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6

#define	AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000040

#define	AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5

#define	AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000020

#define	AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET 4

#define	AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000010

#define	AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3

#define	AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008

#define	AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2

#define	AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004

#define	AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0b1

#define	AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET 1

#define	AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002

#define	AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE 0b0

#define	AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_GATE_EN_REG 0x000005e0

#define	MBUS_GATE_EN_REG_CAN_MCLK_EN_OFFSET 17

#define	MBUS_GATE_EN_REG_CAN_MCLK_EN_CLEAR_MASK 0x00020000

#define	MBUS_GATE_EN_REG_CAN_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_CAN_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET 12

#define	MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK 0x00001000

#define	MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET 11

#define	MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK 0x00000800

#define	MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET 9

#define	MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK 0x00000200

#define	MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET 8

#define	MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK 0x00000100

#define	MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_NAND0_MCLK_EN_OFFSET 5

#define	MBUS_GATE_EN_REG_NAND0_MCLK_EN_CLEAR_MASK 0x00000020

#define	MBUS_GATE_EN_REG_NAND0_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_NAND0_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET 3

#define	MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK 0x00000008

#define	MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET 2

#define	MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK 0x00000004

#define	MBUS_GATE_EN_REG_CE_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG 0b1

#define	MBUS_GATE_EN_REG_VE_MCLK_EN_OFFSET 1

#define	MBUS_GATE_EN_REG_VE_MCLK_EN_CLEAR_MASK 0x00000002

#define	MBUS_GATE_EN_REG_VE_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_VE_MCLK_EN_PASS 0b1

#define	MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET 0

#define	MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK 0x00000001

#define	MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK 0b0

#define	MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS 0b1

#define	MBUS_MAT_CLK_GATING_REG 0x000005e4

#define	MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_OFFSET 27

#define	MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_CLEAR_MASK 0x08000000

#define	MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_OFFSET 26

#define	MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x04000000

#define	MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 24

#define	MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK 0x01000000

#define	MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_OFFSET 23

#define	MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00800000

#define	MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 22

#define	MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00400000

#define	MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_OFFSET 21

#define	MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00200000

#define	MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 20

#define	MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000

#define	MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_OFFSET 19

#define	MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00080000

#define	MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET 18

#define	MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00040000

#define	MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET 17

#define	MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00020000

#define	MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE 0b0

#define	MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE 0b1

#define	DMA0_BGR_REG 0x00000704

#define	DMA0_BGR_REG_DMA0_RST_OFFSET 16

#define	DMA0_BGR_REG_DMA0_RST_CLEAR_MASK 0x00010000

#define	DMA0_BGR_REG_DMA0_RST_ASSERT 0b0

#define	DMA0_BGR_REG_DMA0_RST_DE_ASSERT 0b1

#define	DMA0_BGR_REG_DMA0_GATING_OFFSET 0

#define	DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK 0x00000001

#define	DMA0_BGR_REG_DMA0_GATING_MASK 0b0

#define	DMA0_BGR_REG_DMA0_GATING_PASS 0b1

#define	DMA1_BGR_REG 0x0000070c

#define	DMA1_BGR_REG_DMA1_RST_OFFSET 16

#define	DMA1_BGR_REG_DMA1_RST_CLEAR_MASK 0x00010000

#define	DMA1_BGR_REG_DMA1_RST_ASSERT 0b0

#define	DMA1_BGR_REG_DMA1_RST_DE_ASSERT 0b1

#define	DMA1_BGR_REG_DMA1_GATING_OFFSET 0

#define	DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK 0x00000001

#define	DMA1_BGR_REG_DMA1_GATING_MASK 0b0

#define	DMA1_BGR_REG_DMA1_GATING_PASS 0b1

#define	SPINLOCK_BGR_REG 0x00000724

#define	SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16

#define	SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK 0x00010000

#define	SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0b0

#define	SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0b1

#define	SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0

#define	SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK 0x00000001

#define	SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0b0

#define	SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0b1

#define	MSGBOX0_BGR_REG 0x00000744

#define	MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16

#define	MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK 0x00010000

#define	MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT 0b0

#define	MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT 0b1

#define	MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0

#define	MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK 0b0

#define	MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS 0b1

#define	MSGBOX_CORE0_BGR_REG 0x0000074c

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_OFFSET 16

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_CLEAR_MASK 0x00010000

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_ASSERT 0b0

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_DE_ASSERT 0b1

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_OFFSET 0

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_MASK 0b0

#define	MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_PASS 0b1

#define	MSGBOX_CORE1_BGR_REG 0x00000754

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_OFFSET 16

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_CLEAR_MASK 0x00010000

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_ASSERT 0b0

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_DE_ASSERT 0b1

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_OFFSET 0

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_MASK 0b0

#define	MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_PASS 0b1

#define	MSGBOX_CORE2_BGR_REG 0x0000075c

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_OFFSET 16

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_CLEAR_MASK 0x00010000

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_ASSERT 0b0

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_DE_ASSERT 0b1

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_OFFSET 0

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_MASK 0b0

#define	MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_PASS 0b1

#define	MSGBOX_CORE3_BGR_REG 0x00000764

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_OFFSET 16

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_CLEAR_MASK 0x00010000

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_ASSERT 0b0

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_DE_ASSERT 0b1

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_OFFSET 0

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_MASK 0b0

#define	MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_PASS 0b1

#define	MSGBOX_RV_BGR_REG 0x0000076c

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_OFFSET 16

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_CLEAR_MASK 0x00010000

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_ASSERT 0b0

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_DE_ASSERT 0b1

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_OFFSET 0

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_CLEAR_MASK 0x00000001

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_MASK 0b0

#define	MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_PASS 0b1

#define	PWM0_BGR_REG 0x00000784

#define	PWM0_BGR_REG_PWM0_RST_OFFSET 16

#define	PWM0_BGR_REG_PWM0_RST_CLEAR_MASK 0x00010000

#define	PWM0_BGR_REG_PWM0_RST_ASSERT 0b0

#define	PWM0_BGR_REG_PWM0_RST_DE_ASSERT 0b1

#define	PWM0_BGR_REG_PWM0_GATING_OFFSET 0

#define	PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK 0x00000001

#define	PWM0_BGR_REG_PWM0_GATING_MASK 0b0

#define	PWM0_BGR_REG_PWM0_GATING_PASS 0b1

#define	PWM1_BGR_REG 0x0000078c

#define	PWM1_BGR_REG_PWM1_RST_OFFSET 16

#define	PWM1_BGR_REG_PWM1_RST_CLEAR_MASK 0x00010000

#define	PWM1_BGR_REG_PWM1_RST_ASSERT 0b0

#define	PWM1_BGR_REG_PWM1_RST_DE_ASSERT 0b1

#define	PWM1_BGR_REG_PWM1_GATING_OFFSET 0

#define	PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK 0x00000001

#define	PWM1_BGR_REG_PWM1_GATING_MASK 0b0

#define	PWM1_BGR_REG_PWM1_GATING_PASS 0b1

#define	PWM2_BGR_REG 0x00000794

#define	PWM2_BGR_REG_PWM2_RST_OFFSET 16

#define	PWM2_BGR_REG_PWM2_RST_CLEAR_MASK 0x00010000

#define	PWM2_BGR_REG_PWM2_RST_ASSERT 0b0

#define	PWM2_BGR_REG_PWM2_RST_DE_ASSERT 0b1

#define	PWM2_BGR_REG_PWM2_GATING_OFFSET 0

#define	PWM2_BGR_REG_PWM2_GATING_CLEAR_MASK 0x00000001

#define	PWM2_BGR_REG_PWM2_GATING_MASK 0b0

#define	PWM2_BGR_REG_PWM2_GATING_PASS 0b1

#define	DBGSYS_BGR_REG 0x000007a4

#define	DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16

#define	DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK 0x00010000

#define	DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0b0

#define	DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0b1

#define	DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0

#define	DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK 0x00000001

#define	DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0b0

#define	DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0b1

#define	SYSDAP_BGR_REG 0x000007ac

#define	SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16

#define	SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK 0x00010000

#define	SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0b0

#define	SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG 0b1

#define	SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0

#define	SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK 0x00000001

#define	SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0b0

#define	SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG 0b1

#define	TIMER0_CLK_REG 0x00000800

#define	TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET 31

#define	TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE 0b0

#define	TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE 0b1

#define	TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER0_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER0_CLK_REG_FACTOR_M__1 0b000

#define	TIMER0_CLK_REG_FACTOR_M__2 0b001

#define	TIMER0_CLK_REG_FACTOR_M__4 0b010

#define	TIMER0_CLK_REG_FACTOR_M__8 0b011

#define	TIMER0_CLK_REG_FACTOR_M__16 0b100

#define	TIMER0_CLK_REG_FACTOR_M__32 0b101

#define	TIMER0_CLK_REG_FACTOR_M__64 0b110

#define	TIMER0_CLK_REG_FACTOR_M__128 0b111

#define	TIMER1_CLK_REG 0x00000804

#define	TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET 31

#define	TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE 0b0

#define	TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE 0b1

#define	TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER1_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER1_CLK_REG_FACTOR_M__1 0b000

#define	TIMER1_CLK_REG_FACTOR_M__2 0b001

#define	TIMER1_CLK_REG_FACTOR_M__4 0b010

#define	TIMER1_CLK_REG_FACTOR_M__8 0b011

#define	TIMER1_CLK_REG_FACTOR_M__16 0b100

#define	TIMER1_CLK_REG_FACTOR_M__32 0b101

#define	TIMER1_CLK_REG_FACTOR_M__64 0b110

#define	TIMER1_CLK_REG_FACTOR_M__128 0b111

#define	TIMER2_CLK_REG 0x00000808

#define	TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET 31

#define	TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE 0b0

#define	TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE 0b1

#define	TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER2_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER2_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER2_CLK_REG_FACTOR_M__1 0b000

#define	TIMER2_CLK_REG_FACTOR_M__2 0b001

#define	TIMER2_CLK_REG_FACTOR_M__4 0b010

#define	TIMER2_CLK_REG_FACTOR_M__8 0b011

#define	TIMER2_CLK_REG_FACTOR_M__16 0b100

#define	TIMER2_CLK_REG_FACTOR_M__32 0b101

#define	TIMER2_CLK_REG_FACTOR_M__64 0b110

#define	TIMER2_CLK_REG_FACTOR_M__128 0b111

#define	TIMER3_CLK_REG 0x0000080c

#define	TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET 31

#define	TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE 0b0

#define	TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE 0b1

#define	TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER3_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER3_CLK_REG_FACTOR_M__1 0b000

#define	TIMER3_CLK_REG_FACTOR_M__2 0b001

#define	TIMER3_CLK_REG_FACTOR_M__4 0b010

#define	TIMER3_CLK_REG_FACTOR_M__8 0b011

#define	TIMER3_CLK_REG_FACTOR_M__16 0b100

#define	TIMER3_CLK_REG_FACTOR_M__32 0b101

#define	TIMER3_CLK_REG_FACTOR_M__64 0b110

#define	TIMER3_CLK_REG_FACTOR_M__128 0b111

#define	TIMER4_CLK_REG 0x00000810

#define	TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET 31

#define	TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE 0b0

#define	TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE 0b1

#define	TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER4_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER4_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER4_CLK_REG_FACTOR_M__1 0b000

#define	TIMER4_CLK_REG_FACTOR_M__2 0b001

#define	TIMER4_CLK_REG_FACTOR_M__4 0b010

#define	TIMER4_CLK_REG_FACTOR_M__8 0b011

#define	TIMER4_CLK_REG_FACTOR_M__16 0b100

#define	TIMER4_CLK_REG_FACTOR_M__32 0b101

#define	TIMER4_CLK_REG_FACTOR_M__64 0b110

#define	TIMER4_CLK_REG_FACTOR_M__128 0b111

#define	TIMER5_CLK_REG 0x00000814

#define	TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET 31

#define	TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE 0b0

#define	TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE 0b1

#define	TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER5_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER5_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER5_CLK_REG_FACTOR_M__1 0b000

#define	TIMER5_CLK_REG_FACTOR_M__2 0b001

#define	TIMER5_CLK_REG_FACTOR_M__4 0b010

#define	TIMER5_CLK_REG_FACTOR_M__8 0b011

#define	TIMER5_CLK_REG_FACTOR_M__16 0b100

#define	TIMER5_CLK_REG_FACTOR_M__32 0b101

#define	TIMER5_CLK_REG_FACTOR_M__64 0b110

#define	TIMER5_CLK_REG_FACTOR_M__128 0b111

#define	TIMER6_CLK_REG 0x00000818

#define	TIMER6_CLK_REG_TIMER6_CLK_GATING_OFFSET 31

#define	TIMER6_CLK_REG_TIMER6_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER6_CLK_REG_TIMER6_CLK_GATING_DISABLE 0b0

#define	TIMER6_CLK_REG_TIMER6_CLK_GATING_ENABLE 0b1

#define	TIMER6_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER6_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER6_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER6_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER6_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER6_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER6_CLK_REG_FACTOR_M__1 0b000

#define	TIMER6_CLK_REG_FACTOR_M__2 0b001

#define	TIMER6_CLK_REG_FACTOR_M__4 0b010

#define	TIMER6_CLK_REG_FACTOR_M__8 0b011

#define	TIMER6_CLK_REG_FACTOR_M__16 0b100

#define	TIMER6_CLK_REG_FACTOR_M__32 0b101

#define	TIMER6_CLK_REG_FACTOR_M__64 0b110

#define	TIMER6_CLK_REG_FACTOR_M__128 0b111

#define	TIMER7_CLK_REG 0x0000081c

#define	TIMER7_CLK_REG_TIMER7_CLK_GATING_OFFSET 31

#define	TIMER7_CLK_REG_TIMER7_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER7_CLK_REG_TIMER7_CLK_GATING_DISABLE 0b0

#define	TIMER7_CLK_REG_TIMER7_CLK_GATING_ENABLE 0b1

#define	TIMER7_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER7_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER7_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER7_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER7_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER7_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER7_CLK_REG_FACTOR_M__1 0b000

#define	TIMER7_CLK_REG_FACTOR_M__2 0b001

#define	TIMER7_CLK_REG_FACTOR_M__4 0b010

#define	TIMER7_CLK_REG_FACTOR_M__8 0b011

#define	TIMER7_CLK_REG_FACTOR_M__16 0b100

#define	TIMER7_CLK_REG_FACTOR_M__32 0b101

#define	TIMER7_CLK_REG_FACTOR_M__64 0b110

#define	TIMER7_CLK_REG_FACTOR_M__128 0b111

#define	TIMER_BGR_REG 0x00000850

#define	TIMER_BGR_REG_TIMER_RST_OFFSET 16

#define	TIMER_BGR_REG_TIMER_RST_CLEAR_MASK 0x00010000

#define	TIMER_BGR_REG_TIMER_RST_ASSERT 0b0

#define	TIMER_BGR_REG_TIMER_RST_DE_ASSERT 0b1

#define	TIMER_BGR_REG_TIMER_GATING_OFFSET 0

#define	TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK 0x00000001

#define	TIMER_BGR_REG_TIMER_GATING_MASK 0b0

#define	TIMER_BGR_REG_TIMER_GATING_PASS 0b1

#define	TIMER0_RV_CLK_REG 0x00000860

#define	TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_OFFSET 31

#define	TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_DISABLE 0b0

#define	TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_ENABLE 0b1

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER0_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER0_RV_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER0_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER0_RV_CLK_REG_FACTOR_M__1 0b000

#define	TIMER0_RV_CLK_REG_FACTOR_M__2 0b001

#define	TIMER0_RV_CLK_REG_FACTOR_M__4 0b010

#define	TIMER0_RV_CLK_REG_FACTOR_M__8 0b011

#define	TIMER0_RV_CLK_REG_FACTOR_M__16 0b100

#define	TIMER0_RV_CLK_REG_FACTOR_M__32 0b101

#define	TIMER0_RV_CLK_REG_FACTOR_M__64 0b110

#define	TIMER0_RV_CLK_REG_FACTOR_M__128 0b111

#define	TIMER1_RV_CLK_REG 0x00000864

#define	TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_OFFSET 31

#define	TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_DISABLE 0b0

#define	TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_ENABLE 0b1

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER1_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER1_RV_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER1_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER1_RV_CLK_REG_FACTOR_M__1 0b000

#define	TIMER1_RV_CLK_REG_FACTOR_M__2 0b001

#define	TIMER1_RV_CLK_REG_FACTOR_M__4 0b010

#define	TIMER1_RV_CLK_REG_FACTOR_M__8 0b011

#define	TIMER1_RV_CLK_REG_FACTOR_M__16 0b100

#define	TIMER1_RV_CLK_REG_FACTOR_M__32 0b101

#define	TIMER1_RV_CLK_REG_FACTOR_M__64 0b110

#define	TIMER1_RV_CLK_REG_FACTOR_M__128 0b111

#define	TIMER2_RV_CLK_REG 0x00000868

#define	TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_OFFSET 31

#define	TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_DISABLE 0b0

#define	TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_ENABLE 0b1

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER2_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER2_RV_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER2_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER2_RV_CLK_REG_FACTOR_M__1 0b000

#define	TIMER2_RV_CLK_REG_FACTOR_M__2 0b001

#define	TIMER2_RV_CLK_REG_FACTOR_M__4 0b010

#define	TIMER2_RV_CLK_REG_FACTOR_M__8 0b011

#define	TIMER2_RV_CLK_REG_FACTOR_M__16 0b100

#define	TIMER2_RV_CLK_REG_FACTOR_M__32 0b101

#define	TIMER2_RV_CLK_REG_FACTOR_M__64 0b110

#define	TIMER2_RV_CLK_REG_FACTOR_M__128 0b111

#define	TIMER3_RV_CLK_REG 0x0000086c

#define	TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_OFFSET 31

#define	TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_CLEAR_MASK 0x80000000

#define	TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_DISABLE 0b0

#define	TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_ENABLE 0b1

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	TIMER3_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	TIMER3_RV_CLK_REG_FACTOR_M_OFFSET 0

#define	TIMER3_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

#define	TIMER3_RV_CLK_REG_FACTOR_M__1 0b000

#define	TIMER3_RV_CLK_REG_FACTOR_M__2 0b001

#define	TIMER3_RV_CLK_REG_FACTOR_M__4 0b010

#define	TIMER3_RV_CLK_REG_FACTOR_M__8 0b011

#define	TIMER3_RV_CLK_REG_FACTOR_M__16 0b100

#define	TIMER3_RV_CLK_REG_FACTOR_M__32 0b101

#define	TIMER3_RV_CLK_REG_FACTOR_M__64 0b110

#define	TIMER3_RV_CLK_REG_FACTOR_M__128 0b111

#define	TIMER_RV_BGR_REG 0x00000870

#define	TIMER_RV_BGR_REG_TIMER_RV_RST_OFFSET 16

#define	TIMER_RV_BGR_REG_TIMER_RV_RST_CLEAR_MASK 0x00010000

#define	TIMER_RV_BGR_REG_TIMER_RV_RST_ASSERT 0b0

#define	TIMER_RV_BGR_REG_TIMER_RV_RST_DE_ASSERT 0b1

#define	TIMER_RV_BGR_REG_TIMER_RV_GATING_OFFSET 0

#define	TIMER_RV_BGR_REG_TIMER_RV_GATING_CLEAR_MASK 0x00000001

#define	TIMER_RV_BGR_REG_TIMER_RV_GATING_MASK 0b0

#define	TIMER_RV_BGR_REG_TIMER_RV_GATING_PASS 0b1

#define	DE0_CLK_REG 0x00000a00

#define	DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31

#define	DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK 0x80000000

#define	DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1

#define	DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

#define	DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

#define	DE0_CLK_REG_FACTOR_M_OFFSET 0

#define	DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	DE0_BGR_REG 0x00000a04

#define	DE0_BGR_REG_DE0_RST_OFFSET 16

#define	DE0_BGR_REG_DE0_RST_CLEAR_MASK 0x00010000

#define	DE0_BGR_REG_DE0_RST_ASSERT 0b0

#define	DE0_BGR_REG_DE0_RST_DE_ASSERT 0b1

#define	DE0_BGR_REG_DE0_GATING_OFFSET 0

#define	DE0_BGR_REG_DE0_GATING_CLEAR_MASK 0x00000001

#define	DE0_BGR_REG_DE0_GATING_MASK 0b0

#define	DE0_BGR_REG_DE0_GATING_PASS 0b1

#define	G2D_CLK_REG 0x00000a40

#define	G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31

#define	G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000

#define	G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0

#define	G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1

#define	G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

#define	G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

#define	G2D_CLK_REG_FACTOR_M_OFFSET 0

#define	G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	G2D_BGR_REG 0x00000a44

#define	G2D_BGR_REG_G2D_RST_OFFSET 16

#define	G2D_BGR_REG_G2D_RST_CLEAR_MASK 0x00010000

#define	G2D_BGR_REG_G2D_RST_ASSERT 0b0

#define	G2D_BGR_REG_G2D_RST_DE_ASSERT 0b1

#define	G2D_BGR_REG_G2D_GATING_OFFSET 0

#define	G2D_BGR_REG_G2D_GATING_CLEAR_MASK 0x00000001

#define	G2D_BGR_REG_G2D_GATING_MASK 0b0

#define	G2D_BGR_REG_G2D_GATING_PASS 0b1

#define	DE_SYS_BGR_REG 0x00000a74

#define	DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16

#define	DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK 0x00010000

#define	DE_SYS_BGR_REG_DE_SYS_RST_ASSERT 0b0

#define	DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT 0b1

#define	VE_CLK_REG 0x00000a80

#define	VE_CLK_REG_VE_CLK_GATING_OFFSET 31

#define	VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK 0x80000000

#define	VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF 0b0

#define	VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON 0b1

#define	VE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	VE_CLK_REG_CLK_SRC_SEL_VEPLL 0b000

#define	VE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	VE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define	VE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

#define	VE_CLK_REG_FACTOR_M_OFFSET 0

#define	VE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	VE_BGR_REG 0x00000a8c

#define	VE_BGR_REG_VE_RST_OFFSET 16

#define	VE_BGR_REG_VE_RST_CLEAR_MASK 0x00010000

#define	VE_BGR_REG_VE_RST_ASSERT 0b0

#define	VE_BGR_REG_VE_RST_DE_ASSERT 0b1

#define	VE_BGR_REG_VE_GATING_OFFSET 0

#define	VE_BGR_REG_VE_GATING_CLEAR_MASK 0x00000001

#define	VE_BGR_REG_VE_GATING_MASK 0b0

#define	VE_BGR_REG_VE_GATING_PASS 0b1

#define	CE_CLK_REG 0x00000ac0

#define	CE_CLK_REG_CE_CLK_GATING_OFFSET 31

#define	CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK 0x80000000

#define	CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG 0b1

#define	CE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CE_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	CE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	CE_CLK_REG_FACTOR_M_OFFSET 0

#define	CE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CE_BGR_REG 0x00000ac4

#define	CE_BGR_REG_CE_SYS_RST_OFFSET 17

#define	CE_BGR_REG_CE_SYS_RST_CLEAR_MASK 0x00020000

#define	CE_BGR_REG_CE_SYS_RST_ASSERT 0b0

#define	CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG 0b1

#define	CE_BGR_REG_CE_RST_OFFSET 16

#define	CE_BGR_REG_CE_RST_CLEAR_MASK 0x00010000

#define	CE_BGR_REG_CE_RST_ASSERT 0b0

#define	CE_BGR_REG_CE_RST_SECURE_DEBUG 0b1

#define	CE_BGR_REG_CE_SYS_GATING_OFFSET 1

#define	CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK 0x00000002

#define	CE_BGR_REG_CE_SYS_GATING_MASK 0b0

#define	CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG 0b1

#define	CE_BGR_REG_CE_GATING_OFFSET 0

#define	CE_BGR_REG_CE_GATING_CLEAR_MASK 0x00000001

#define	CE_BGR_REG_CE_GATING_MASK 0b0

#define	CE_BGR_REG_CE_GATING_SECURE_DEBUG 0b1

#define	NPU_CLK_REG 0x00000b00

#define	NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31

#define	NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK 0x80000000

#define	NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0b0

#define	NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0b1

#define	NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	NPU_CLK_REG_CLK_SRC_SEL_NPUPLL 0b000

#define	NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001

#define	NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define	NPU_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011

#define	NPU_CLK_REG_FACTOR_M_OFFSET 0

#define	NPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	NPU_BGR_REG 0x00000b04

#define	NPU_BGR_REG_NPU_GLB_RST_OFFSET 19

#define	NPU_BGR_REG_NPU_GLB_RST_CLEAR_MASK 0x00080000

#define	NPU_BGR_REG_NPU_GLB_RST_ASSERT 0b0

#define	NPU_BGR_REG_NPU_GLB_RST_DE_ASSERT 0b1

#define	NPU_BGR_REG_NPU_AHB_RST_OFFSET 18

#define	NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK 0x00040000

#define	NPU_BGR_REG_NPU_AHB_RST_ASSERT 0b0

#define	NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT 0b1

#define	NPU_BGR_REG_NPU_AXI_RST_OFFSET 17

#define	NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK 0x00020000

#define	NPU_BGR_REG_NPU_AXI_RST_ASSERT 0b0

#define	NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT 0b1

#define	NPU_BGR_REG_NPU_CORE_RST_OFFSET 16

#define	NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK 0x00010000

#define	NPU_BGR_REG_NPU_CORE_RST_ASSERT 0b0

#define	NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT 0b1

#define	NPU_BGR_REG_NPU_TZMA_GATING_OFFSET 1

#define	NPU_BGR_REG_NPU_TZMA_GATING_CLEAR_MASK 0x00000002

#define	NPU_BGR_REG_NPU_TZMA_GATING_MASK 0b0

#define	NPU_BGR_REG_NPU_TZMA_GATING_PASS 0b1

#define	NPU_BGR_REG_NPU_GATING_OFFSET 0

#define	NPU_BGR_REG_NPU_GATING_CLEAR_MASK 0x00000001

#define	NPU_BGR_REG_NPU_GATING_MASK 0b0

#define	NPU_BGR_REG_NPU_GATING_PASS 0b1

#define	RV_CORE_CLK_REG 0x00000b80

#define	RV_CORE_CLK_REG_RV_CORE_CLK_GATING_OFFSET 31

#define	RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLEAR_MASK 0x80000000

#define	RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_OFF 0b0

#define	RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_ON 0b1

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

#define	RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101

#define	RV_CORE_CLK_REG_E907_AXI_DIV_CFG_OFFSET 8

#define	RV_CORE_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK 0x00000300

#define	RV_CORE_CLK_REG_FACTOR_M_OFFSET 0

#define	RV_CORE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	RV_TS_CLK_REG 0x00000b88

#define	RV_TS_CLK_REG_RV_TS_CLK_GATING_OFFSET 31

#define	RV_TS_CLK_REG_RV_TS_CLK_GATING_CLEAR_MASK 0x80000000

#define	RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_OFF 0b0

#define	RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_ON 0b1

#define	RV_TS_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	RV_TS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	RV_TS_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	RV_TS_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

#define	RV_TS_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

#define	RV_SYS_BGR_REG 0x00000b94

#define	RV_SYS_BGR_REG_RV_SYS_RST_OFFSET 17

#define	RV_SYS_BGR_REG_RV_SYS_RST_CLEAR_MASK 0x00020000

#define	RV_SYS_BGR_REG_RV_SYS_RST_ASSERT 0b0

#define	RV_SYS_BGR_REG_RV_SYS_RST_DE_ASSERT 0b1

#define	RV_SYS_BGR_REG_RV_CORE_RST_OFFSET 16

#define	RV_SYS_BGR_REG_RV_CORE_RST_CLEAR_MASK 0x00010000

#define	RV_SYS_BGR_REG_RV_CORE_RST_ASSERT 0b0

#define	RV_SYS_BGR_REG_RV_CORE_RST_DE_ASSERT 0b1

#define	RV_CFG_BGR_REG 0x00000b9c

#define	RV_CFG_BGR_REG_RV_CFG_RST_OFFSET 16

#define	RV_CFG_BGR_REG_RV_CFG_RST_CLEAR_MASK 0x00010000

#define	RV_CFG_BGR_REG_RV_CFG_RST_ASSERT 0b0

#define	RV_CFG_BGR_REG_RV_CFG_RST_DE_ASSERT 0b1

#define	RV_CFG_BGR_REG_RV_CFG_GATING_OFFSET 0

#define	RV_CFG_BGR_REG_RV_CFG_GATING_CLEAR_MASK 0x00000001

#define	RV_CFG_BGR_REG_RV_CFG_GATING_MASK 0b0

#define	RV_CFG_BGR_REG_RV_CFG_GATING_PASS 0b1

#define	DRAM_CLK_REG 0x00000c00

#define	DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31

#define	DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK 0x80000000

#define	DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0b0

#define	DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0b1

#define	DRAM_CLK_REG_DRAM_UPD_OFFSET 27

#define	DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK 0x08000000

#define	DRAM_CLK_REG_DRAM_UPD_INVALID 0b0

#define	DRAM_CLK_REG_DRAM_UPD_VALID 0b1

#define	DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24

#define	DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK 0x07000000

#define	DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0b000

#define	DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_800M 0b001

#define	DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M 0b010

#define	DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M 0b011

#define	DRAM_CLK_REG_DRAM_CLK_SEL_NPUPLL 0b100

#define	DRAM_CLK_REG_DRAM_CLK_SEL_HOSC 0b101

#define	DRAM_CLK_REG_DRAM_DIV1_OFFSET 0

#define	DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK 0x0000001f

#define	DRAM_BGR_REG 0x00000c0c

#define	DRAM_BGR_REG_DRAM_RST_OFFSET 16

#define	DRAM_BGR_REG_DRAM_RST_CLEAR_MASK 0x00010000

#define	DRAM_BGR_REG_DRAM_RST_ASSERT 0b0

#define	DRAM_BGR_REG_DRAM_RST_DE_ASSERT 0b1

#define	DRAM_BGR_REG_DRAM_GATING_OFFSET 0

#define	DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK 0x00000001

#define	DRAM_BGR_REG_DRAM_GATING_MASK 0b0

#define	DRAM_BGR_REG_DRAM_GATING_PASS 0b1

#define	NAND0_CLK2X_CLK_REG 0x00000c80

#define	NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_OFFSET 31

#define	NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLEAR_MASK 0x80000000

#define	NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_OFF 0b0

#define	NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_ON 0b1

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define	NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define	NAND0_CLK2X_CLK_REG_FACTOR_M_OFFSET 0

#define	NAND0_CLK2X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	NAND0_CLK1_CLK_REG 0x00000c84

#define	NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31

#define	NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK 0x80000000

#define	NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0b1

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define	NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define	NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0

#define	NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	NAND0_BGR_REG 0x00000c8c

#define	NAND0_BGR_REG_NAND0_RST_OFFSET 16

#define	NAND0_BGR_REG_NAND0_RST_CLEAR_MASK 0x00010000

#define	NAND0_BGR_REG_NAND0_RST_ASSERT 0b0

#define	NAND0_BGR_REG_NAND0_RST_DE_ASSERT 0b1

#define	NAND0_BGR_REG_NAND0_GATING_OFFSET 0

#define	NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK 0x00000001

#define	NAND0_BGR_REG_NAND0_GATING_MASK 0b0

#define	NAND0_BGR_REG_NAND0_GATING_PASS 0b1

#define	SMHC0_CLK_REG 0x00000d00

#define	SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31

#define	SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000

#define	SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1

#define	SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SMHC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define	SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define	SMHC0_CLK_REG_FACTOR_N_OFFSET 8

#define	SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SMHC0_CLK_REG_FACTOR_M_OFFSET 0

#define	SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SMHC0_BGR_REG 0x00000d0c

#define	SMHC0_BGR_REG_SMHC0_RST_OFFSET 16

#define	SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK 0x00010000

#define	SMHC0_BGR_REG_SMHC0_RST_ASSERT 0b0

#define	SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT 0b1

#define	SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0

#define	SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK 0x00000001

#define	SMHC0_BGR_REG_SMHC0_GATING_MASK 0b0

#define	SMHC0_BGR_REG_SMHC0_GATING_PASS 0b1

#define	SMHC1_CLK_REG 0x00000d10

#define	SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31

#define	SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000

#define	SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1

#define	SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SMHC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

#define	SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

#define	SMHC1_CLK_REG_FACTOR_N_OFFSET 8

#define	SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SMHC1_CLK_REG_FACTOR_M_OFFSET 0

#define	SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SMHC1_BGR_REG 0x00000d1c

#define	SMHC1_BGR_REG_SMHC1_RST_OFFSET 16

#define	SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK 0x00010000

#define	SMHC1_BGR_REG_SMHC1_RST_ASSERT 0b0

#define	SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT 0b1

#define	SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0

#define	SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK 0x00000001

#define	SMHC1_BGR_REG_SMHC1_GATING_MASK 0b0

#define	SMHC1_BGR_REG_SMHC1_GATING_PASS 0b1

#define	SMHC2_CLK_REG 0x00000d20

#define	SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31

#define	SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000

#define	SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1

#define	SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SMHC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001

#define	SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

#define	SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011

#define	SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100

#define	SMHC2_CLK_REG_FACTOR_N_OFFSET 8

#define	SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SMHC2_CLK_REG_FACTOR_M_OFFSET 0

#define	SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SMHC2_BGR_REG 0x00000d2c

#define	SMHC2_BGR_REG_SMHC2_RST_OFFSET 16

#define	SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK 0x00010000

#define	SMHC2_BGR_REG_SMHC2_RST_ASSERT 0b0

#define	SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT 0b1

#define	SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0

#define	SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK 0x00000001

#define	SMHC2_BGR_REG_SMHC2_GATING_MASK 0b0

#define	SMHC2_BGR_REG_SMHC2_GATING_PASS 0b1

#define	UART0_BGR_REG 0x00000e00

#define	UART0_BGR_REG_UART0_RST_OFFSET 16

#define	UART0_BGR_REG_UART0_RST_CLEAR_MASK 0x00010000

#define	UART0_BGR_REG_UART0_RST_ASSERT 0b0

#define	UART0_BGR_REG_UART0_RST_DE_ASSERT 0b1

#define	UART0_BGR_REG_UART0_GATING_OFFSET 0

#define	UART0_BGR_REG_UART0_GATING_CLEAR_MASK 0x00000001

#define	UART0_BGR_REG_UART0_GATING_MASK 0b0

#define	UART0_BGR_REG_UART0_GATING_PASS 0b1

#define	UART1_BGR_REG 0x00000e04

#define	UART1_BGR_REG_UART1_RST_OFFSET 16

#define	UART1_BGR_REG_UART1_RST_CLEAR_MASK 0x00010000

#define	UART1_BGR_REG_UART1_RST_ASSERT 0b0

#define	UART1_BGR_REG_UART1_RST_DE_ASSERT 0b1

#define	UART1_BGR_REG_UART1_GATING_OFFSET 0

#define	UART1_BGR_REG_UART1_GATING_CLEAR_MASK 0x00000001

#define	UART1_BGR_REG_UART1_GATING_MASK 0b0

#define	UART1_BGR_REG_UART1_GATING_PASS 0b1

#define	UART2_BGR_REG 0x00000e08

#define	UART2_BGR_REG_UART2_RST_OFFSET 16

#define	UART2_BGR_REG_UART2_RST_CLEAR_MASK 0x00010000

#define	UART2_BGR_REG_UART2_RST_ASSERT 0b0

#define	UART2_BGR_REG_UART2_RST_DE_ASSERT 0b1

#define	UART2_BGR_REG_UART2_GATING_OFFSET 0

#define	UART2_BGR_REG_UART2_GATING_CLEAR_MASK 0x00000001

#define	UART2_BGR_REG_UART2_GATING_MASK 0b0

#define	UART2_BGR_REG_UART2_GATING_PASS 0b1

#define	UART3_BGR_REG 0x00000e0c

#define	UART3_BGR_REG_UART3_RST_OFFSET 16

#define	UART3_BGR_REG_UART3_RST_CLEAR_MASK 0x00010000

#define	UART3_BGR_REG_UART3_RST_ASSERT 0b0

#define	UART3_BGR_REG_UART3_RST_DE_ASSERT 0b1

#define	UART3_BGR_REG_UART3_GATING_OFFSET 0

#define	UART3_BGR_REG_UART3_GATING_CLEAR_MASK 0x00000001

#define	UART3_BGR_REG_UART3_GATING_MASK 0b0

#define	UART3_BGR_REG_UART3_GATING_PASS 0b1

#define	UART4_BGR_REG 0x00000e10

#define	UART4_BGR_REG_UART4_RST_OFFSET 16

#define	UART4_BGR_REG_UART4_RST_CLEAR_MASK 0x00010000

#define	UART4_BGR_REG_UART4_RST_ASSERT 0b0

#define	UART4_BGR_REG_UART4_RST_DE_ASSERT 0b1

#define	UART4_BGR_REG_UART4_GATING_OFFSET 0

#define	UART4_BGR_REG_UART4_GATING_CLEAR_MASK 0x00000001

#define	UART4_BGR_REG_UART4_GATING_MASK 0b0

#define	UART4_BGR_REG_UART4_GATING_PASS 0b1

#define	UART5_BGR_REG 0x00000e14

#define	UART5_BGR_REG_UART5_RST_OFFSET 16

#define	UART5_BGR_REG_UART5_RST_CLEAR_MASK 0x00010000

#define	UART5_BGR_REG_UART5_RST_ASSERT 0b0

#define	UART5_BGR_REG_UART5_RST_DE_ASSERT 0b1

#define	UART5_BGR_REG_UART5_GATING_OFFSET 0

#define	UART5_BGR_REG_UART5_GATING_CLEAR_MASK 0x00000001

#define	UART5_BGR_REG_UART5_GATING_MASK 0b0

#define	UART5_BGR_REG_UART5_GATING_PASS 0b1

#define	UART6_BGR_REG 0x00000e18

#define	UART6_BGR_REG_UART6_RST_OFFSET 16

#define	UART6_BGR_REG_UART6_RST_CLEAR_MASK 0x00010000

#define	UART6_BGR_REG_UART6_RST_ASSERT 0b0

#define	UART6_BGR_REG_UART6_RST_DE_ASSERT 0b1

#define	UART6_BGR_REG_UART6_GATING_OFFSET 0

#define	UART6_BGR_REG_UART6_GATING_CLEAR_MASK 0x00000001

#define	UART6_BGR_REG_UART6_GATING_MASK 0b0

#define	UART6_BGR_REG_UART6_GATING_PASS 0b1

#define	UART7_BGR_REG 0x00000e20

#define	UART7_BGR_REG_UART7_RST_OFFSET 16

#define	UART7_BGR_REG_UART7_RST_CLEAR_MASK 0x00010000

#define	UART7_BGR_REG_UART7_RST_ASSERT 0b0

#define	UART7_BGR_REG_UART7_RST_DE_ASSERT 0b1

#define	UART7_BGR_REG_UART7_GATING_OFFSET 0

#define	UART7_BGR_REG_UART7_GATING_CLEAR_MASK 0x00000001

#define	UART7_BGR_REG_UART7_GATING_MASK 0b0

#define	UART7_BGR_REG_UART7_GATING_PASS 0b1

#define	UART8_BGR_REG 0x00000e24

#define	UART8_BGR_REG_UART8_RST_OFFSET 16

#define	UART8_BGR_REG_UART8_RST_CLEAR_MASK 0x00010000

#define	UART8_BGR_REG_UART8_RST_ASSERT 0b0

#define	UART8_BGR_REG_UART8_RST_DE_ASSERT 0b1

#define	UART8_BGR_REG_UART8_GATING_OFFSET 0

#define	UART8_BGR_REG_UART8_GATING_CLEAR_MASK 0x00000001

#define	UART8_BGR_REG_UART8_GATING_MASK 0b0

#define	UART8_BGR_REG_UART8_GATING_PASS 0b1

#define	UART9_BGR_REG 0x00000e28

#define	UART9_BGR_REG_UART9_RST_OFFSET 16

#define	UART9_BGR_REG_UART9_RST_CLEAR_MASK 0x00010000

#define	UART9_BGR_REG_UART9_RST_ASSERT 0b0

#define	UART9_BGR_REG_UART9_RST_DE_ASSERT 0b1

#define	UART9_BGR_REG_UART9_GATING_OFFSET 0

#define	UART9_BGR_REG_UART9_GATING_CLEAR_MASK 0x00000001

#define	UART9_BGR_REG_UART9_GATING_MASK 0b0

#define	UART9_BGR_REG_UART9_GATING_PASS 0b1

#define	UART10_BGR_REG 0x00000e2c

#define	UART10_BGR_REG_UART10_RST_OFFSET 16

#define	UART10_BGR_REG_UART10_RST_CLEAR_MASK 0x00010000

#define	UART10_BGR_REG_UART10_RST_ASSERT 0b0

#define	UART10_BGR_REG_UART10_RST_DE_ASSERT 0b1

#define	UART10_BGR_REG_UART10_GATING_OFFSET 0

#define	UART10_BGR_REG_UART10_GATING_CLEAR_MASK 0x00000001

#define	UART10_BGR_REG_UART10_GATING_MASK 0b0

#define	UART10_BGR_REG_UART10_GATING_PASS 0b1

#define	UART11_BGR_REG 0x00000e30

#define	UART11_BGR_REG_UART11_RST_OFFSET 16

#define	UART11_BGR_REG_UART11_RST_CLEAR_MASK 0x00010000

#define	UART11_BGR_REG_UART11_RST_ASSERT 0b0

#define	UART11_BGR_REG_UART11_RST_DE_ASSERT 0b1

#define	UART11_BGR_REG_UART11_GATING_OFFSET 0

#define	UART11_BGR_REG_UART11_GATING_CLEAR_MASK 0x00000001

#define	UART11_BGR_REG_UART11_GATING_MASK 0b0

#define	UART11_BGR_REG_UART11_GATING_PASS 0b1

#define	UART12_BGR_REG 0x00000e34

#define	UART12_BGR_REG_UART12_RST_OFFSET 16

#define	UART12_BGR_REG_UART12_RST_CLEAR_MASK 0x00010000

#define	UART12_BGR_REG_UART12_RST_ASSERT 0b0

#define	UART12_BGR_REG_UART12_RST_DE_ASSERT 0b1

#define	UART12_BGR_REG_UART12_GATING_OFFSET 0

#define	UART12_BGR_REG_UART12_GATING_CLEAR_MASK 0x00000001

#define	UART12_BGR_REG_UART12_GATING_MASK 0b0

#define	UART12_BGR_REG_UART12_GATING_PASS 0b1

#define	UART13_BGR_REG 0x00000e38

#define	UART13_BGR_REG_UART13_RST_OFFSET 16

#define	UART13_BGR_REG_UART13_RST_CLEAR_MASK 0x00010000

#define	UART13_BGR_REG_UART13_RST_ASSERT 0b0

#define	UART13_BGR_REG_UART13_RST_DE_ASSERT 0b1

#define	UART13_BGR_REG_UART13_GATING_OFFSET 0

#define	UART13_BGR_REG_UART13_GATING_CLEAR_MASK 0x00000001

#define	UART13_BGR_REG_UART13_GATING_MASK 0b0

#define	UART13_BGR_REG_UART13_GATING_PASS 0b1

#define	UART14_BGR_REG 0x00000e3c

#define	UART14_BGR_REG_UART14_RST_OFFSET 16

#define	UART14_BGR_REG_UART14_RST_CLEAR_MASK 0x00010000

#define	UART14_BGR_REG_UART14_RST_ASSERT 0b0

#define	UART14_BGR_REG_UART14_RST_DE_ASSERT 0b1

#define	UART14_BGR_REG_UART14_GATING_OFFSET 0

#define	UART14_BGR_REG_UART14_GATING_CLEAR_MASK 0x00000001

#define	UART14_BGR_REG_UART14_GATING_MASK 0b0

#define	UART14_BGR_REG_UART14_GATING_PASS 0b1

#define	TWI0_BGR_REG 0x00000e80

#define	TWI0_BGR_REG_TWI0_RST_OFFSET 16

#define	TWI0_BGR_REG_TWI0_RST_CLEAR_MASK 0x00010000

#define	TWI0_BGR_REG_TWI0_RST_ASSERT 0b0

#define	TWI0_BGR_REG_TWI0_RST_DE_ASSERT 0b1

#define	TWI0_BGR_REG_TWI0_GATING_OFFSET 0

#define	TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK 0x00000001

#define	TWI0_BGR_REG_TWI0_GATING_MASK 0b0

#define	TWI0_BGR_REG_TWI0_GATING_PASS 0b1

#define	TWI1_BGR_REG 0x00000e84

#define	TWI1_BGR_REG_TWI1_RST_OFFSET 16

#define	TWI1_BGR_REG_TWI1_RST_CLEAR_MASK 0x00010000

#define	TWI1_BGR_REG_TWI1_RST_ASSERT 0b0

#define	TWI1_BGR_REG_TWI1_RST_DE_ASSERT 0b1

#define	TWI1_BGR_REG_TWI1_GATING_OFFSET 0

#define	TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK 0x00000001

#define	TWI1_BGR_REG_TWI1_GATING_MASK 0b0

#define	TWI1_BGR_REG_TWI1_GATING_PASS 0b1

#define	TWI2_BGR_REG 0x00000e88

#define	TWI2_BGR_REG_TWI2_RST_OFFSET 16

#define	TWI2_BGR_REG_TWI2_RST_CLEAR_MASK 0x00010000

#define	TWI2_BGR_REG_TWI2_RST_ASSERT 0b0

#define	TWI2_BGR_REG_TWI2_RST_DE_ASSERT 0b1

#define	TWI2_BGR_REG_TWI2_GATING_OFFSET 0

#define	TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK 0x00000001

#define	TWI2_BGR_REG_TWI2_GATING_MASK 0b0

#define	TWI2_BGR_REG_TWI2_GATING_PASS 0b1

#define	TWI3_BGR_REG 0x00000e8c

#define	TWI3_BGR_REG_TWI3_RST_OFFSET 16

#define	TWI3_BGR_REG_TWI3_RST_CLEAR_MASK 0x00010000

#define	TWI3_BGR_REG_TWI3_RST_ASSERT 0b0

#define	TWI3_BGR_REG_TWI3_RST_DE_ASSERT 0b1

#define	TWI3_BGR_REG_TWI3_GATING_OFFSET 0

#define	TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK 0x00000001

#define	TWI3_BGR_REG_TWI3_GATING_MASK 0b0

#define	TWI3_BGR_REG_TWI3_GATING_PASS 0b1

#define	TWI4_BGR_REG 0x00000e90

#define	TWI4_BGR_REG_TWI4_RST_OFFSET 16

#define	TWI4_BGR_REG_TWI4_RST_CLEAR_MASK 0x00010000

#define	TWI4_BGR_REG_TWI4_RST_ASSERT 0b0

#define	TWI4_BGR_REG_TWI4_RST_DE_ASSERT 0b1

#define	TWI4_BGR_REG_TWI4_GATING_OFFSET 0

#define	TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK 0x00000001

#define	TWI4_BGR_REG_TWI4_GATING_MASK 0b0

#define	TWI4_BGR_REG_TWI4_GATING_PASS 0b1

#define	TWI5_BGR_REG 0x00000e94

#define	TWI5_BGR_REG_TWI5_RST_OFFSET 16

#define	TWI5_BGR_REG_TWI5_RST_CLEAR_MASK 0x00010000

#define	TWI5_BGR_REG_TWI5_RST_ASSERT 0b0

#define	TWI5_BGR_REG_TWI5_RST_DE_ASSERT 0b1

#define	TWI5_BGR_REG_TWI5_GATING_OFFSET 0

#define	TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK 0x00000001

#define	TWI5_BGR_REG_TWI5_GATING_MASK 0b0

#define	TWI5_BGR_REG_TWI5_GATING_PASS 0b1

#define	TWI6_BGR_REG 0x00000e98

#define	TWI6_BGR_REG_TWI6_RST_OFFSET 16

#define	TWI6_BGR_REG_TWI6_RST_CLEAR_MASK 0x00010000

#define	TWI6_BGR_REG_TWI6_RST_ASSERT 0b0

#define	TWI6_BGR_REG_TWI6_RST_DE_ASSERT 0b1

#define	TWI6_BGR_REG_TWI6_GATING_OFFSET 0

#define	TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK 0x00000001

#define	TWI6_BGR_REG_TWI6_GATING_MASK 0b0

#define	TWI6_BGR_REG_TWI6_GATING_PASS 0b1

#define	SPI0_CLK_REG 0x00000f00

#define	SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31

#define	SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

#define	SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define	SPI0_CLK_REG_FACTOR_N_OFFSET 8

#define	SPI0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPI0_CLK_REG_FACTOR_M_OFFSET 0

#define	SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPI0_BGR_REG 0x00000f04

#define	SPI0_BGR_REG_SPI0_RST_OFFSET 16

#define	SPI0_BGR_REG_SPI0_RST_CLEAR_MASK 0x00010000

#define	SPI0_BGR_REG_SPI0_RST_ASSERT 0b0

#define	SPI0_BGR_REG_SPI0_RST_DE_ASSERT 0b1

#define	SPI0_BGR_REG_SPI0_GATING_OFFSET 0

#define	SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK 0x00000001

#define	SPI0_BGR_REG_SPI0_GATING_MASK 0b0

#define	SPI0_BGR_REG_SPI0_GATING_PASS 0b1

#define	SPI1_CLK_REG 0x00000f08

#define	SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31

#define	SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

#define	SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define	SPI1_CLK_REG_FACTOR_N_OFFSET 8

#define	SPI1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPI1_CLK_REG_FACTOR_M_OFFSET 0

#define	SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPI1_BGR_REG 0x00000f0c

#define	SPI1_BGR_REG_SPI1_RST_OFFSET 16

#define	SPI1_BGR_REG_SPI1_RST_CLEAR_MASK 0x00010000

#define	SPI1_BGR_REG_SPI1_RST_ASSERT 0b0

#define	SPI1_BGR_REG_SPI1_RST_DE_ASSERT 0b1

#define	SPI1_BGR_REG_SPI1_GATING_OFFSET 0

#define	SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK 0x00000001

#define	SPI1_BGR_REG_SPI1_GATING_MASK 0b0

#define	SPI1_BGR_REG_SPI1_GATING_PASS 0b1

#define	SPI2_CLK_REG 0x00000f10

#define	SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31

#define	SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

#define	SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define	SPI2_CLK_REG_FACTOR_N_OFFSET 8

#define	SPI2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPI2_CLK_REG_FACTOR_M_OFFSET 0

#define	SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPI2_BGR_REG 0x00000f14

#define	SPI2_BGR_REG_SPI2_RST_OFFSET 16

#define	SPI2_BGR_REG_SPI2_RST_CLEAR_MASK 0x00010000

#define	SPI2_BGR_REG_SPI2_RST_ASSERT 0b0

#define	SPI2_BGR_REG_SPI2_RST_DE_ASSERT 0b1

#define	SPI2_BGR_REG_SPI2_GATING_OFFSET 0

#define	SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK 0x00000001

#define	SPI2_BGR_REG_SPI2_GATING_MASK 0b0

#define	SPI2_BGR_REG_SPI2_GATING_PASS 0b1

#define	SPIF_CLK_REG 0x00000f18

#define	SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31

#define	SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b101

#define	SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b110

#define	SPIF_CLK_REG_FACTOR_N_OFFSET 8

#define	SPIF_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPIF_CLK_REG_FACTOR_M_OFFSET 0

#define	SPIF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPIF_BGR_REG 0x00000f1c

#define	SPIF_BGR_REG_SPIF_RST_OFFSET 16

#define	SPIF_BGR_REG_SPIF_RST_CLEAR_MASK 0x00010000

#define	SPIF_BGR_REG_SPIF_RST_ASSERT 0b0

#define	SPIF_BGR_REG_SPIF_RST_DE_ASSERT 0b1

#define	SPIF_BGR_REG_SPIF_GATING_OFFSET 0

#define	SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK 0x00000001

#define	SPIF_BGR_REG_SPIF_GATING_MASK 0b0

#define	SPIF_BGR_REG_SPIF_GATING_PASS 0b1

#define	SPI3_CLK_REG 0x00000f20

#define	SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31

#define	SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPI3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

#define	SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define	SPI3_CLK_REG_FACTOR_N_OFFSET 8

#define	SPI3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPI3_CLK_REG_FACTOR_M_OFFSET 0

#define	SPI3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPI3_BGR_REG 0x00000f24

#define	SPI3_BGR_REG_SPI3_RST_OFFSET 16

#define	SPI3_BGR_REG_SPI3_RST_CLEAR_MASK 0x00010000

#define	SPI3_BGR_REG_SPI3_RST_ASSERT 0b0

#define	SPI3_BGR_REG_SPI3_RST_DE_ASSERT 0b1

#define	SPI3_BGR_REG_SPI3_GATING_OFFSET 0

#define	SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK 0x00000001

#define	SPI3_BGR_REG_SPI3_GATING_MASK 0b0

#define	SPI3_BGR_REG_SPI3_GATING_PASS 0b1

#define	SPI4_CLK_REG 0x00000f28

#define	SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET 31

#define	SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK 0x80000000

#define	SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON 0b1

#define	SPI4_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	SPI4_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

#define	SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

#define	SPI4_CLK_REG_FACTOR_N_OFFSET 8

#define	SPI4_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	SPI4_CLK_REG_FACTOR_M_OFFSET 0

#define	SPI4_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SPI4_BGR_REG 0x00000f2c

#define	SPI4_BGR_REG_SPI4_RST_OFFSET 16

#define	SPI4_BGR_REG_SPI4_RST_CLEAR_MASK 0x00010000

#define	SPI4_BGR_REG_SPI4_RST_ASSERT 0b0

#define	SPI4_BGR_REG_SPI4_RST_DE_ASSERT 0b1

#define	SPI4_BGR_REG_SPI4_GATING_OFFSET 0

#define	SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK 0x00000001

#define	SPI4_BGR_REG_SPI4_GATING_MASK 0b0

#define	SPI4_BGR_REG_SPI4_GATING_PASS 0b1

#define	GPADC0_CLK_REG 0x00000fc0

#define	GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET 31

#define	GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK 0x80000000

#define	GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON 0b1

#define	GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	GPADC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

#define	GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define	GPADC0_CLK_REG_FACTOR_M_OFFSET 0

#define	GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GPADC0_BGR_REG 0x00000fc4

#define	GPADC0_BGR_REG_GPADC0_RST_OFFSET 16

#define	GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK 0x00010000

#define	GPADC0_BGR_REG_GPADC0_RST_ASSERT 0b0

#define	GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT 0b1

#define	GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0

#define	GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK 0x00000001

#define	GPADC0_BGR_REG_GPADC0_GATING_MASK 0b0

#define	GPADC0_BGR_REG_GPADC0_GATING_PASS 0b1

#define	GPADC1_CLK_REG 0x00000fc8

#define	GPADC1_CLK_REG_GPADC1_CLK_GATING_OFFSET 31

#define	GPADC1_CLK_REG_GPADC1_CLK_GATING_CLEAR_MASK 0x80000000

#define	GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_ON 0b1

#define	GPADC1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GPADC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	GPADC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	GPADC1_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

#define	GPADC1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define	GPADC1_CLK_REG_FACTOR_M_OFFSET 0

#define	GPADC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GPADC1_BGR_REG 0x00000fcc

#define	GPADC1_BGR_REG_GPADC1_RST_OFFSET 16

#define	GPADC1_BGR_REG_GPADC1_RST_CLEAR_MASK 0x00010000

#define	GPADC1_BGR_REG_GPADC1_RST_ASSERT 0b0

#define	GPADC1_BGR_REG_GPADC1_RST_DE_ASSERT 0b1

#define	GPADC1_BGR_REG_GPADC1_GATING_OFFSET 0

#define	GPADC1_BGR_REG_GPADC1_GATING_CLEAR_MASK 0x00000001

#define	GPADC1_BGR_REG_GPADC1_GATING_MASK 0b0

#define	GPADC1_BGR_REG_GPADC1_GATING_PASS 0b1

#define	GPADC2_CLK_REG 0x00000fd0

#define	GPADC2_CLK_REG_GPADC2_CLK_GATING_OFFSET 31

#define	GPADC2_CLK_REG_GPADC2_CLK_GATING_CLEAR_MASK 0x80000000

#define	GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_ON 0b1

#define	GPADC2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GPADC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	GPADC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	GPADC2_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

#define	GPADC2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define	GPADC2_CLK_REG_FACTOR_M_OFFSET 0

#define	GPADC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GPADC2_BGR_REG 0x00000fd4

#define	GPADC2_BGR_REG_GPADC2_RST_OFFSET 16

#define	GPADC2_BGR_REG_GPADC2_RST_CLEAR_MASK 0x00010000

#define	GPADC2_BGR_REG_GPADC2_RST_ASSERT 0b0

#define	GPADC2_BGR_REG_GPADC2_RST_DE_ASSERT 0b1

#define	GPADC2_BGR_REG_GPADC2_GATING_OFFSET 0

#define	GPADC2_BGR_REG_GPADC2_GATING_CLEAR_MASK 0x00000001

#define	GPADC2_BGR_REG_GPADC2_GATING_MASK 0b0

#define	GPADC2_BGR_REG_GPADC2_GATING_PASS 0b1

#define	GPADC3_CLK_REG 0x00000fd8

#define	GPADC3_CLK_REG_GPADC3_CLK_GATING_OFFSET 31

#define	GPADC3_CLK_REG_GPADC3_CLK_GATING_CLEAR_MASK 0x80000000

#define	GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_ON 0b1

#define	GPADC3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GPADC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	GPADC3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	GPADC3_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

#define	GPADC3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

#define	GPADC3_CLK_REG_FACTOR_M_OFFSET 0

#define	GPADC3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GPADC3_BGR_REG 0x00000fdc

#define	GPADC3_BGR_REG_GPADC3_RST_OFFSET 16

#define	GPADC3_BGR_REG_GPADC3_RST_CLEAR_MASK 0x00010000

#define	GPADC3_BGR_REG_GPADC3_RST_ASSERT 0b0

#define	GPADC3_BGR_REG_GPADC3_RST_DE_ASSERT 0b1

#define	GPADC3_BGR_REG_GPADC3_GATING_OFFSET 0

#define	GPADC3_BGR_REG_GPADC3_GATING_CLEAR_MASK 0x00000001

#define	GPADC3_BGR_REG_GPADC3_GATING_MASK 0b0

#define	GPADC3_BGR_REG_GPADC3_GATING_PASS 0b1

#define	THS_BGR_REG 0x00000fe4

#define	THS_BGR_REG_THS_RST_OFFSET 16

#define	THS_BGR_REG_THS_RST_CLEAR_MASK 0x00010000

#define	THS_BGR_REG_THS_RST_ASSERT 0b0

#define	THS_BGR_REG_THS_RST_DE_ASSERT 0b1

#define	THS_BGR_REG_THS_GATING_OFFSET 0

#define	THS_BGR_REG_THS_GATING_CLEAR_MASK 0x00000001

#define	THS_BGR_REG_THS_GATING_MASK 0b0

#define	THS_BGR_REG_THS_GATING_PASS 0b1

#define	IRRX0_CLK_REG 0x00001000

#define	IRRX0_CLK_REG_IRRX0_CLK_GATING_OFFSET 31

#define	IRRX0_CLK_REG_IRRX0_CLK_GATING_CLEAR_MASK 0x80000000

#define	IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_ON 0b1

#define	IRRX0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	IRRX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	IRRX0_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define	IRRX0_CLK_REG_CLK_SRC_SEL_HOSC 0b1

#define	IRRX0_CLK_REG_FACTOR_M_OFFSET 0

#define	IRRX0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	IRRX0_BGR_REG 0x00001004

#define	IRRX0_BGR_REG_IRRX0_RST_OFFSET 16

#define	IRRX0_BGR_REG_IRRX0_RST_CLEAR_MASK 0x00010000

#define	IRRX0_BGR_REG_IRRX0_RST_ASSERT 0b0

#define	IRRX0_BGR_REG_IRRX0_RST_DE_ASSERT 0b1

#define	IRRX0_BGR_REG_IRRX0_GATING_OFFSET 0

#define	IRRX0_BGR_REG_IRRX0_GATING_CLEAR_MASK 0x00000001

#define	IRRX0_BGR_REG_IRRX0_GATING_MASK 0b0

#define	IRRX0_BGR_REG_IRRX0_GATING_PASS 0b1

#define	IRTX_CLK_REG 0x00001008

#define	IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31

#define	IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK 0x80000000

#define	IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0b0

#define	IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0b1

#define	IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b1

#define	IRTX_CLK_REG_FACTOR_M_OFFSET 0

#define	IRTX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	IRTX_BGR_REG 0x0000100c

#define	IRTX_BGR_REG_IRTX_RST_OFFSET 16

#define	IRTX_BGR_REG_IRTX_RST_CLEAR_MASK 0x00010000

#define	IRTX_BGR_REG_IRTX_RST_ASSERT 0b0

#define	IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0b1

#define	IRTX_BGR_REG_IRTX_GATING_OFFSET 0

#define	IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK 0x00000001

#define	IRTX_BGR_REG_IRTX_GATING_MASK 0b0

#define	IRTX_BGR_REG_IRTX_GATING_PASS 0b1

#define	LRADC_BGR_REG 0x00001024

#define	LRADC_BGR_REG_LRADC_RST_OFFSET 16

#define	LRADC_BGR_REG_LRADC_RST_CLEAR_MASK 0x00010000

#define	LRADC_BGR_REG_LRADC_RST_ASSERT 0b0

#define	LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0b1

#define	LRADC_BGR_REG_LRADC_GATING_OFFSET 0

#define	LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK 0x00000001

#define	LRADC_BGR_REG_LRADC_GATING_MASK 0b0

#define	LRADC_BGR_REG_LRADC_GATING_PASS 0b1

#define	TPADC_24M_CLK_REG 0x00001030

#define	TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_OFFSET 31

#define	TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLEAR_MASK 0x80000000

#define	TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_OFF 0b0

#define	TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_ON 0b1

#define	TPADC_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	TPADC_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	TPADC_24M_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	TPADC_24M_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b1

#define	TPADC_24M_CLK_REG_FACTOR_M_OFFSET 0

#define	TPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	TPADC_BGR_REG 0x00001034

#define	TPADC_BGR_REG_TPADC_RST_OFFSET 16

#define	TPADC_BGR_REG_TPADC_RST_CLEAR_MASK 0x00010000

#define	TPADC_BGR_REG_TPADC_RST_ASSERT 0b0

#define	TPADC_BGR_REG_TPADC_RST_DE_ASSERT 0b1

#define	TPADC_BGR_REG_TPADC_GATING_OFFSET 0

#define	TPADC_BGR_REG_TPADC_GATING_CLEAR_MASK 0x00000001

#define	TPADC_BGR_REG_TPADC_GATING_MASK 0b0

#define	TPADC_BGR_REG_TPADC_GATING_PASS 0b1

#define	LBC_CLK_REG 0x00001040

#define	LBC_CLK_REG_LBC_CLK_GATING_OFFSET 31

#define	LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK 0x80000000

#define	LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF 0b0

#define	LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON 0b1

#define	LBC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	LBC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

#define	LBC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011

#define	LBC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100

#define	LBC_CLK_REG_FACTOR_N_OFFSET 8

#define	LBC_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	LBC_CLK_REG_FACTOR_M_OFFSET 0

#define	LBC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	LBC_NSI_AHB_CLK_REG 0x00001048

#define	LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_OFFSET 31

#define	LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLEAR_MASK 0x80000000

#define	LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_OFF 0b0

#define	LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_ON 0b1

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b01

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b10

#define	LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11

#define	LBC_NSI_AHB_CLK_REG_FACTOR_M_OFFSET 0

#define	LBC_NSI_AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	LBC_BGR_REG 0x0000104c

#define	LBC_BGR_REG_LBC_RST_OFFSET 16

#define	LBC_BGR_REG_LBC_RST_CLEAR_MASK 0x00010000

#define	LBC_BGR_REG_LBC_RST_ASSERT 0b0

#define	LBC_BGR_REG_LBC_RST_DE_ASSERT 0b1

#define	LBC_BGR_REG_LBC_GATING_OFFSET 0

#define	LBC_BGR_REG_LBC_GATING_CLEAR_MASK 0x00000001

#define	LBC_BGR_REG_LBC_GATING_MASK 0b0

#define	LBC_BGR_REG_LBC_GATING_PASS 0b1

#define	IRRX1_CLK_REG 0x00001100

#define	IRRX1_CLK_REG_IRRX1_CLK_GATING_OFFSET 31

#define	IRRX1_CLK_REG_IRRX1_CLK_GATING_CLEAR_MASK 0x80000000

#define	IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_ON 0b1

#define	IRRX1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	IRRX1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	IRRX1_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define	IRRX1_CLK_REG_CLK_SRC_SEL_HOSC 0b1

#define	IRRX1_CLK_REG_FACTOR_M_OFFSET 0

#define	IRRX1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	IRRX1_BGR_REG 0x00001104

#define	IRRX1_BGR_REG_IRRX1_RST_OFFSET 16

#define	IRRX1_BGR_REG_IRRX1_RST_CLEAR_MASK 0x00010000

#define	IRRX1_BGR_REG_IRRX1_RST_ASSERT 0b0

#define	IRRX1_BGR_REG_IRRX1_RST_DE_ASSERT 0b1

#define	IRRX1_BGR_REG_IRRX1_GATING_OFFSET 0

#define	IRRX1_BGR_REG_IRRX1_GATING_CLEAR_MASK 0x00000001

#define	IRRX1_BGR_REG_IRRX1_GATING_MASK 0b0

#define	IRRX1_BGR_REG_IRRX1_GATING_PASS 0b1

#define	IRRX2_CLK_REG 0x00001108

#define	IRRX2_CLK_REG_IRRX2_CLK_GATING_OFFSET 31

#define	IRRX2_CLK_REG_IRRX2_CLK_GATING_CLEAR_MASK 0x80000000

#define	IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_OFF 0b0

#define	IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_ON 0b1

#define	IRRX2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	IRRX2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	IRRX2_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define	IRRX2_CLK_REG_CLK_SRC_SEL_HOSC 0b1

#define	IRRX2_CLK_REG_FACTOR_M_OFFSET 0

#define	IRRX2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	IRRX2_BGR_REG 0x0000110c

#define	IRRX2_BGR_REG_IRRX2_RST_OFFSET 16

#define	IRRX2_BGR_REG_IRRX2_RST_CLEAR_MASK 0x00010000

#define	IRRX2_BGR_REG_IRRX2_RST_ASSERT 0b0

#define	IRRX2_BGR_REG_IRRX2_RST_DE_ASSERT 0b1

#define	IRRX2_BGR_REG_IRRX2_GATING_OFFSET 0

#define	IRRX2_BGR_REG_IRRX2_GATING_CLEAR_MASK 0x00000001

#define	IRRX2_BGR_REG_IRRX2_GATING_MASK 0b0

#define	IRRX2_BGR_REG_IRRX2_GATING_PASS 0b1

#define	IRRX3_CLK_REG 0x00001110

#define	IRRX3_CLK_REG_IRRX3_CLK_GATING_OFFSET 31

#define	IRRX3_CLK_REG_IRRX3_CLK_GATING_CLEAR_MASK 0x80000000

#define	IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_OFF 0b0

#define	IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_ON 0b1

#define	IRRX3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	IRRX3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	IRRX3_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define	IRRX3_CLK_REG_CLK_SRC_SEL_HOSC 0b1

#define	IRRX3_CLK_REG_FACTOR_M_OFFSET 0

#define	IRRX3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	IRRX3_BGR_REG 0x00001114

#define	IRRX3_BGR_REG_IRRX3_RST_OFFSET 16

#define	IRRX3_BGR_REG_IRRX3_RST_CLEAR_MASK 0x00010000

#define	IRRX3_BGR_REG_IRRX3_RST_ASSERT 0b0

#define	IRRX3_BGR_REG_IRRX3_RST_DE_ASSERT 0b1

#define	IRRX3_BGR_REG_IRRX3_GATING_OFFSET 0

#define	IRRX3_BGR_REG_IRRX3_GATING_CLEAR_MASK 0x00000001

#define	IRRX3_BGR_REG_IRRX3_GATING_MASK 0b0

#define	IRRX3_BGR_REG_IRRX3_GATING_PASS 0b1

#define	I2SPCM0_CLK_REG 0x00001200

#define	I2SPCM0_CLK_REG_SCLK_GATING_OFFSET 31

#define	I2SPCM0_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

#define	I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

#define	I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

#define	I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define	I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

#define	I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define	I2SPCM0_CLK_REG_FACTOR_M_OFFSET 0

#define	I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	I2SPCM0_BGR_REG 0x0000120c

#define	I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET 16

#define	I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK 0x00010000

#define	I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT 0b0

#define	I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT 0b1

#define	I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET 0

#define	I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK 0x00000001

#define	I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK 0b0

#define	I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS 0b1

#define	I2SPCM1_CLK_REG 0x00001210

#define	I2SPCM1_CLK_REG_SCLK_GATING_OFFSET 31

#define	I2SPCM1_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

#define	I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

#define	I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

#define	I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define	I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

#define	I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define	I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0

#define	I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	I2SPCM1_BGR_REG 0x0000121c

#define	I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16

#define	I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK 0x00010000

#define	I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT 0b0

#define	I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT 0b1

#define	I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0

#define	I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK 0x00000001

#define	I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK 0b0

#define	I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS 0b1

#define	I2SPCM2_CLK_REG 0x00001220

#define	I2SPCM2_CLK_REG_SCLK_GATING_OFFSET 31

#define	I2SPCM2_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

#define	I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

#define	I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

#define	I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define	I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

#define	I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define	I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0

#define	I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	I2SPCM2_BGR_REG 0x0000122c

#define	I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16

#define	I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK 0x00010000

#define	I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT 0b0

#define	I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT 0b1

#define	I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0

#define	I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK 0x00000001

#define	I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK 0b0

#define	I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS 0b1

#define	I2SPCM3_CLK_REG 0x00001230

#define	I2SPCM3_CLK_REG_SCLK_GATING_OFFSET 31

#define	I2SPCM3_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

#define	I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

#define	I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

#define	I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

#define	I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

#define	I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

#define	I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0

#define	I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	I2SPCM3_BGR_REG 0x0000123c

#define	I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16

#define	I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK 0x00010000

#define	I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT 0b0

#define	I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT 0b1

#define	I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0

#define	I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK 0x00000001

#define	I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK 0b0

#define	I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS 0b1

#define	OWA_TX_CLK_REG 0x00001280

#define	OWA_TX_CLK_REG_OWA_TX_CLK_GATING_OFFSET 31

#define	OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLEAR_MASK 0x80000000

#define	OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_OFF 0b0

#define	OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_ON 0b1

#define	OWA_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	OWA_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

#define	OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

#define	OWA_TX_CLK_REG_FACTOR_M_OFFSET 0

#define	OWA_TX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	OWA_RX_CLK_REG 0x00001284

#define	OWA_RX_CLK_REG_OWA_RX_CLK_GATING_OFFSET 31

#define	OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLEAR_MASK 0x80000000

#define	OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_OFF 0b0

#define	OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_ON 0b1

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b000

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b010

#define	OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b011

#define	OWA_RX_CLK_REG_FACTOR_M_OFFSET 0

#define	OWA_RX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	OWA_BGR_REG 0x0000128c

#define	OWA_BGR_REG_OWA_RST_OFFSET 16

#define	OWA_BGR_REG_OWA_RST_CLEAR_MASK 0x00010000

#define	OWA_BGR_REG_OWA_RST_ASSERT 0b0

#define	OWA_BGR_REG_OWA_RST_DE_ASSERT 0b1

#define	OWA_BGR_REG_OWA_GATING_OFFSET 0

#define	OWA_BGR_REG_OWA_GATING_CLEAR_MASK 0x00000001

#define	OWA_BGR_REG_OWA_GATING_MASK 0b0

#define	OWA_BGR_REG_OWA_GATING_PASS 0b1

#define	DMIC_CLK_REG 0x000012c0

#define	DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31

#define	DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK 0x80000000

#define	DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0

#define	DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1

#define	DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

#define	DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

#define	DMIC_CLK_REG_FACTOR_M_OFFSET 0

#define	DMIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	DMIC_BGR_REG 0x000012cc

#define	DMIC_BGR_REG_DMIC_RST_OFFSET 16

#define	DMIC_BGR_REG_DMIC_RST_CLEAR_MASK 0x00010000

#define	DMIC_BGR_REG_DMIC_RST_ASSERT 0b0

#define	DMIC_BGR_REG_DMIC_RST_DE_ASSERT 0b1

#define	DMIC_BGR_REG_DMIC_GATING_OFFSET 0

#define	DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK 0x00000001

#define	DMIC_BGR_REG_DMIC_GATING_MASK 0b0

#define	DMIC_BGR_REG_DMIC_GATING_PASS 0b1

#define	AUDIO_CODEC_DAC_1X_CLK_REG 0x000012e0

#define	AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_OFFSET 31

#define	AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

#define	AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

#define	AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

#define	AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

#define	AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

#define	AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_OFFSET 0

#define	AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	AUDIO_CODEC_BGR_REG 0x000012ec

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET 16

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK 0x00010000

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT 0b0

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT 0b1

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET 0

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK 0x00000001

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK 0b0

#define	AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS 0b1

#define	USB0_CLK_REG 0x00001300

#define	USB0_CLK_REG_USB0_CLKEN_OFFSET 31

#define	USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000

#define	USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0

#define	USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1

#define	USB0_CLK_REG_USBPHY0_RSTN_OFFSET 30

#define	USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK 0x40000000

#define	USB0_CLK_REG_USBPHY0_RSTN_ASSERT 0b0

#define	USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT 0b1

#define	USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24

#define	USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000

#define	USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00

#define	USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01

#define	USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K 0b10

#define	USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC 0b11

#define	USB0_BGR_REG 0x00001304

#define	USB0_BGR_REG_USB20_0_DEVICE_RST_OFFSET 24

#define	USB0_BGR_REG_USB20_0_DEVICE_RST_CLEAR_MASK 0x01000000

#define	USB0_BGR_REG_USB20_0_DEVICE_RST_ASSERT 0b0

#define	USB0_BGR_REG_USB20_0_DEVICE_RST_DE_ASSERT 0b1

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_RST_OFFSET 20

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_RST_CLEAR_MASK 0x00100000

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_RST_ASSERT 0b0

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_RST_DE_ASSERT 0b1

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_RST_OFFSET 16

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_RST_CLEAR_MASK 0x00010000

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_RST_ASSERT 0b0

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_RST_DE_ASSERT 0b1

#define	USB0_BGR_REG_USB20_0_DEVICE_GATING_OFFSET 8

#define	USB0_BGR_REG_USB20_0_DEVICE_GATING_CLEAR_MASK 0x00000100

#define	USB0_BGR_REG_USB20_0_DEVICE_GATING_MASK 0b0

#define	USB0_BGR_REG_USB20_0_DEVICE_GATING_PASS 0b1

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_OFFSET 4

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_CLEAR_MASK 0x00000010

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_MASK 0b0

#define	USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_PASS 0b1

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_OFFSET 0

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_CLEAR_MASK 0x00000001

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_MASK 0b0

#define	USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_PASS 0b1

#define	USB1_CLK_REG 0x00001308

#define	USB1_CLK_REG_USB1_CLKEN_OFFSET 31

#define	USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000

#define	USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0

#define	USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1

#define	USB1_CLK_REG_USBPHY1_RSTN_OFFSET 30

#define	USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK 0x40000000

#define	USB1_CLK_REG_USBPHY1_RSTN_ASSERT 0b0

#define	USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT 0b1

#define	USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24

#define	USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000

#define	USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00

#define	USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01

#define	USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K 0b10

#define	USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC 0b11

#define	USB1_BGR_REG 0x0000130c

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_RST_OFFSET 20

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_RST_CLEAR_MASK 0x00100000

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_RST_ASSERT 0b0

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_RST_DE_ASSERT 0b1

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_RST_OFFSET 16

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_RST_CLEAR_MASK 0x00010000

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_RST_ASSERT 0b0

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_RST_DE_ASSERT 0b1

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_OFFSET 4

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_CLEAR_MASK 0x00000010

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_MASK 0b0

#define	USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_PASS 0b1

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_OFFSET 0

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_CLEAR_MASK 0x00000001

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_MASK 0b0

#define	USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_PASS 0b1

#define	USB2_U2_REF_CLK_REG 0x00001348

#define	USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31

#define	USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK 0x80000000

#define	USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF 0b0

#define	USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON 0b1

#define	USB2_SUSPEND_CLK_REG 0x00001350

#define	USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31

#define	USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000

#define	USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0

#define	USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1

#define	USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

#define	USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_HOSC 0b1

#define	USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0

#define	USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	USB2_MF_CLK_REG 0x00001354

#define	USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31

#define	USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK 0x80000000

#define	USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0

#define	USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1

#define	USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b01

#define	USB2_MF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b10

#define	USB2_MF_CLK_REG_FACTOR_M_OFFSET 0

#define	USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	USB2_BGR_REG 0x0000135c

#define	USB2_BGR_REG_USB30_RST_OFFSET 16

#define	USB2_BGR_REG_USB30_RST_CLEAR_MASK 0x00010000

#define	USB2_BGR_REG_USB30_RST_ASSERT 0b0

#define	USB2_BGR_REG_USB30_RST_DE_ASSERT 0b1

#define	USB2_BGR_REG_USB30_GATING_OFFSET 0

#define	USB2_BGR_REG_USB30_GATING_CLEAR_MASK 0x00000001

#define	USB2_BGR_REG_USB30_GATING_MASK 0b0

#define	USB2_BGR_REG_USB30_GATING_PASS 0b1

#define	PCIE_AUX_CLK_REG 0x00001380

#define	PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET 31

#define	PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK 0x80000000

#define	PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF 0b0

#define	PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON 0b1

#define	PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0b1

#define	PCIE_AUX_CLK_REG_FACTOR_M_OFFSET 0

#define	PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	PCIE_SLV_CLK_REG 0x00001384

#define	PCIE_SLV_CLK_REG_PCIE_CLK_GATING_OFFSET 31

#define	PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLEAR_MASK 0x80000000

#define	PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_OFF 0b0

#define	PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_ON 0b1

#define	PCIE_SLV_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	PCIE_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b0

#define	PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

#define	PCIE_SLV_CLK_REG_FACTOR_M_OFFSET 0

#define	PCIE_SLV_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	PCIE_BGR_REG 0x0000138c

#define	PCIE_BGR_REG_PCIE_RST_OFFSET 17

#define	PCIE_BGR_REG_PCIE_RST_CLEAR_MASK 0x00020000

#define	PCIE_BGR_REG_PCIE_RST_ASSERT 0b0

#define	PCIE_BGR_REG_PCIE_RST_DE_ASSERT 0b1

#define	PCIE_BGR_REG_PCIE_PWRUP_RST_OFFSET 16

#define	PCIE_BGR_REG_PCIE_PWRUP_RST_CLEAR_MASK 0x00010000

#define	PCIE_BGR_REG_PCIE_PWRUP_RST_ASSERT 0b0

#define	PCIE_BGR_REG_PCIE_PWRUP_RST_DE_ASSERT 0b1

#define	SERDES_PHY_CFG_CLK_REG 0x000013c0

#define	SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET 31

#define	SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK 0x80000000

#define	SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1

#define	SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

#define	SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

#define	SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0

#define	SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SERDES_PHY_REF_CLK_REG 0x000013c4

#define	SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_OFFSET 31

#define	SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000

#define	SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1

#define	SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1

#define	SERDES_PHY_REF_CLK_REG_FACTOR_M_OFFSET 0

#define	SERDES_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	SERDES_BGR_REG 0x000013cc

#define	SERDES_BGR_REG_SERDES_NOPPU_RST_OFFSET 17

#define	SERDES_BGR_REG_SERDES_NOPPU_RST_CLEAR_MASK 0x00020000

#define	SERDES_BGR_REG_SERDES_NOPPU_RST_ASSERT 0b0

#define	SERDES_BGR_REG_SERDES_NOPPU_RST_DE_ASSERT 0b1

#define	SERDES_BGR_REG_SERDES_RST_OFFSET 16

#define	SERDES_BGR_REG_SERDES_RST_CLEAR_MASK 0x00010000

#define	SERDES_BGR_REG_SERDES_RST_ASSERT 0b0

#define	SERDES_BGR_REG_SERDES_RST_DE_ASSERT 0b1

#define	SERDES_AXI_CLK_REG 0x000013e0

#define	SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_OFFSET 31

#define	SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLEAR_MASK 0x80000000

#define	SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_OFF 0b0

#define	SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_ON 0b1

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_HOSC 0b00

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b01

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b10

#define	SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b11

#define	SERDES_AXI_CLK_REG_FACTOR_M_OFFSET 0

#define	SERDES_AXI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GMAC0_PHY_CLK_REG 0x00001400

#define	GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31

#define	GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK 0x80000000

#define	GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1

#define	GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0

#define	GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GMAC0_PTP_CLK_REG 0x00001404

#define	GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_OFFSET 31

#define	GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLEAR_MASK 0x80000000

#define	GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_ON 0b1

#define	GMAC0_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GMAC0_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	GMAC0_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	GMAC0_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

#define	GMAC0_PTP_CLK_REG_FACTOR_M_OFFSET 0

#define	GMAC0_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GMAC0_BGR_REG 0x0000140c

#define	GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17

#define	GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK 0x00020000

#define	GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT 0b0

#define	GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT 0b1

#define	GMAC0_BGR_REG_GMAC0_RST_OFFSET 16

#define	GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK 0x00010000

#define	GMAC0_BGR_REG_GMAC0_RST_ASSERT 0b0

#define	GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT 0b1

#define	GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0

#define	GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK 0x00000001

#define	GMAC0_BGR_REG_GMAC0_GATING_MASK 0b0

#define	GMAC0_BGR_REG_GMAC0_GATING_PASS 0b1

#define	GMAC1_PHY_CLK_REG 0x00001410

#define	GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31

#define	GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK 0x80000000

#define	GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1

#define	GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0

#define	GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GMAC1_PTP_CLK_REG 0x00001414

#define	GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_OFFSET 31

#define	GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLEAR_MASK 0x80000000

#define	GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_OFF 0b0

#define	GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_ON 0b1

#define	GMAC1_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	GMAC1_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	GMAC1_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	GMAC1_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

#define	GMAC1_PTP_CLK_REG_FACTOR_M_OFFSET 0

#define	GMAC1_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	GMAC1_BGR_REG 0x0000141c

#define	GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17

#define	GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK 0x00020000

#define	GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT 0b0

#define	GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT 0b1

#define	GMAC1_BGR_REG_GMAC1_RST_OFFSET 16

#define	GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK 0x00010000

#define	GMAC1_BGR_REG_GMAC1_RST_ASSERT 0b0

#define	GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT 0b1

#define	GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0

#define	GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK 0x00000001

#define	GMAC1_BGR_REG_GMAC1_GATING_MASKS 0b0

#define	GMAC1_BGR_REG_GMAC1_GATING_PASS 0b1

#define	VO0_TCONLCD0_CLK_REG 0x00001500

#define	VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31

#define	VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000

#define	VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0b1

#define	VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b000

#define	VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001

#define	VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b010

#define	VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0

#define	VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	VO0_TCONLCD0_BGR_REG 0x00001504

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK 0x00010000

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0b0

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0b1

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK 0x00000001

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK 0b0

#define	VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS 0b1

#define	LVDS0_BGR_REG 0x00001544

#define	LVDS0_BGR_REG_LVDS0_RST_OFFSET 16

#define	LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK 0x00010000

#define	LVDS0_BGR_REG_LVDS0_RST_ASSERT 0b0

#define	LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT 0b1

#define	DSI0_CLK_REG 0x00001580

#define	DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31

#define	DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK 0x80000000

#define	DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0b1

#define	DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	DSI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

#define	DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010

#define	DSI0_CLK_REG_FACTOR_M_OFFSET 0

#define	DSI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	DSI0_BGR_REG 0x00001584

#define	DSI0_BGR_REG_DSI0_RST_OFFSET 16

#define	DSI0_BGR_REG_DSI0_RST_CLEAR_MASK 0x00010000

#define	DSI0_BGR_REG_DSI0_RST_ASSERT 0b0

#define	DSI0_BGR_REG_DSI0_RST_DE_ASSERT 0b1

#define	DSI0_BGR_REG_DSI0_GATING_OFFSET 0

#define	DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK 0x00000001

#define	DSI0_BGR_REG_DSI0_GATING_MASK 0b0

#define	DSI0_BGR_REG_DSI0_GATING_PASS 0b1

#define	VO0_COMBPHY0_CLK_REG 0x000015c0

#define	VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_OFFSET 31

#define	VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLEAR_MASK 0x80000000

#define	VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0b1

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b010

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b011

#define	VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b100

#define	VO0_COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0

#define	VO0_COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	DPSS_BGR_REG 0x000016c4

#define	DPSS_BGR_REG_DPSS_RST_OFFSET 16

#define	DPSS_BGR_REG_DPSS_RST_CLEAR_MASK 0x00010000

#define	DPSS_BGR_REG_DPSS_RST_ASSERT 0b0

#define	DPSS_BGR_REG_DPSS_RST_DE_ASSERT 0b1

#define	DPSS_BGR_REG_DPSS_GATING_OFFSET 0

#define	DPSS_BGR_REG_DPSS_GATING_CLEAR_MASK 0x00000001

#define	DPSS_BGR_REG_DPSS_GATING_MASK 0b0

#define	DPSS_BGR_REG_DPSS_GATING_PASS 0b1

#define	VIDEO_OUT0_BGR_REG 0x000016e4

#define	VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16

#define	VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK 0x00010000

#define	VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT 0b0

#define	VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT 0b1

#define	LEDC_CLK_REG 0x00001700

#define	LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31

#define	LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000

#define	LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0

#define	LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1

#define	LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

#define	LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0b0

#define	LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1

#define	LEDC_CLK_REG_FACTOR_M_OFFSET 0

#define	LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	LEDC_BGR_REG 0x00001704

#define	LEDC_BGR_REG_LEDC_RST_OFFSET 16

#define	LEDC_BGR_REG_LEDC_RST_CLEAR_MASK 0x00010000

#define	LEDC_BGR_REG_LEDC_RST_ASSERT 0b0

#define	LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0b1

#define	LEDC_BGR_REG_LEDC_GATING_OFFSET 0

#define	LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK 0x00000001

#define	LEDC_BGR_REG_LEDC_GATING_MASK 0b0

#define	LEDC_BGR_REG_LEDC_GATING_PASS 0b1

#define	CSI_MASTER0_CLK_REG 0x00001800

#define	CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31

#define	CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000

#define	CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define	CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

#define	CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8

#define	CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0

#define	CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CSI_MASTER1_CLK_REG 0x00001804

#define	CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31

#define	CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000

#define	CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define	CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

#define	CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8

#define	CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0

#define	CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CSI_MASTER2_CLK_REG 0x00001808

#define	CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31

#define	CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000

#define	CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define	CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

#define	CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8

#define	CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0

#define	CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CSI_MASTER3_CLK_REG 0x0000180c

#define	CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31

#define	CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK 0x80000000

#define	CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON 0b1

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define	CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

#define	CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8

#define	CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

#define	CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0

#define	CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CSI_CLK_REG 0x00001840

#define	CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31

#define	CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000

#define	CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0

#define	CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1

#define	CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

#define	CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

#define	CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

#define	CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

#define	CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b101

#define	CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b110

#define	CSI_CLK_REG_CLK_SRC_SEL_VEPLL 0b111

#define	CSI_CLK_REG_FACTOR_M_OFFSET 0

#define	CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	CSI_BGR_REG 0x00001844

#define	CSI_BGR_REG_CSI_RST_OFFSET 16

#define	CSI_BGR_REG_CSI_RST_CLEAR_MASK 0x00010000

#define	CSI_BGR_REG_CSI_RST_ASSERT 0b0

#define	CSI_BGR_REG_CSI_RST_DE_ASSERT 0b1

#define	CSI_BGR_REG_CSI_GATING_OFFSET 0

#define	CSI_BGR_REG_CSI_GATING_CLEAR_MASK 0x00000001

#define	CSI_BGR_REG_CSI_GATING_MASK 0b0

#define	CSI_BGR_REG_CSI_GATING_PASS 0b1

#define	ISP_CLK_REG 0x00001860

#define	ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31

#define	ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000

#define	ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0

#define	ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1

#define	ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24

#define	ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

#define	ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000

#define	ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

#define	ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b010

#define	ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011

#define	ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b100

#define	ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101

#define	ISP_CLK_REG_CLK_SRC_SEL_VEPLL 0b110

#define	ISP_CLK_REG_CLK_SRC_SEL_NPUPLL 0b111

#define	ISP_CLK_REG_FACTOR_M_OFFSET 0

#define	ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define	ISP_BGR_REG 0x00001864

#define	ISP_BGR_REG_ISP_RST_OFFSET 16

#define	ISP_BGR_REG_ISP_RST_CLEAR_MASK 0x00010000

#define	ISP_BGR_REG_ISP_RST_ASSERT 0b0

#define	ISP_BGR_REG_ISP_RST_DE_ASSERT 0b1

#define	ISP_BGR_REG_ISP_GATING_OFFSET 0

#define	ISP_BGR_REG_ISP_GATING_CLEAR_MASK 0x00000001

#define	ISP_BGR_REG_ISP_GATING_MASK 0b0

#define	ISP_BGR_REG_ISP_GATING_PASS 0b1

#define	PERI0PLL_GATE_EN_REG 0x00001908

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_OFFSET 31

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0

#define	PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG 0x0000190c

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_OFFSET 31

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK 0x08000000

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK 0x04000000

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000800

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000400

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0

#define	PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1

#define	VIDEOPLL_GATE_EN_REG 0x00001910

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00200000

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_OFFSET 20

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_CLEAR_MASK 0x00100000

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_DISABLE 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_ENABLE 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00020000

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00010000

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000020

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_OFFSET 4

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_CLEAR_MASK 0x00000010

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_AUTO 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_NO_AUTO 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000002

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000001

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0

#define	VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

#define	PERI0PLL_GATE_STAT_REG 0x00001988

#define	PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 11

#define	PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK 0x00000800

#define	PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 10

#define	PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK 0x00000400

#define	PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 9

#define	PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK 0x00000200

#define	PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 8

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK 0x00000100

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 7

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK 0x00000080

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 6

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000040

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 5

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK 0x00000020

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 4

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000010

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 3

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK 0x00000008

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 2

#define	PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK 0x00000004

#define	PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 1

#define	PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK 0x00000002

#define	PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1

#define	PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 0

#define	PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK 0x00000001

#define	PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0

#define	PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG 0x0000198c

#define	PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 9

#define	PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK 0x00000200

#define	PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 8

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK 0x00000100

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 7

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK 0x00000080

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 6

#define	PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK 0x00000040

#define	PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 5

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000020

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 4

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK 0x00000010

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 3

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000008

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 2

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK 0x00000004

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 1

#define	PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK 0x00000002

#define	PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1

#define	PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 0

#define	PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK 0x00000001

#define	PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0

#define	PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1

#define	VIDEOPLL_GATE_STAT_REG 0x00001998

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_OFFSET 17

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_CLEAR_MASK 0x00020000

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_DISABLE 0b0

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_ENABLE 0b1

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_OFFSET 16

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_CLEAR_MASK 0x00010000

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_DISABLE 0b0

#define	VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_ENABLE 0b1

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_OFFSET 1

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_CLEAR_MASK 0x00000002

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_DISABLE 0b0

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_ENABLE 0b1

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_OFFSET 0

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_CLEAR_MASK 0x00000001

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_DISABLE 0b0

#define	VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_ENABLE 0b1

#define	CLK24M_GATE_EN_REG 0x00001a00

#define	CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3

#define	CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK 0x00000008

#define	CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0b0

#define	CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0b1

#define	CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_OFFSET 0

#define	CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_CLEAR_MASK 0x00000001

#define	CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_DISABLE 0b0

#define	CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_ENABLE 0b1

#define	PERI1_FOCPU_EN_REG 0x00001a10

#define	PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_OFFSET 0

#define	PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_CLEAR_MASK 0x00000001

#define	PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_DISABLE 0b0

#define	PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_ENABLE 0b1

#define	CM_VI_CFG_REG 0x00001b00

#define	CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16

#define	CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK 0x00030000

#define	CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF 0b01

#define	CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON 0b10

#define	CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0

#define	CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE 0b0

#define	CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE 0b1

#define	CM_VE_CFG_REG 0x00001b10

#define	CM_VE_CFG_REG_CM_VE_STATUS_OFFSET 16

#define	CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK 0x00030000

#define	CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF 0b01

#define	CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON 0b10

#define	CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET 0

#define	CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE 0b0

#define	CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE 0b1

#define	CM_NPU_CFG_REG 0x00001b1c

#define	CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16

#define	CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK 0x00030000

#define	CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF 0b01

#define	CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON 0b10

#define	CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0

#define	CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE 0b0

#define	CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE 0b1

#define	CM_SERDES_CFG_REG 0x00001b28

#define	CM_SERDES_CFG_REG_CM_SERDES_STATUS_OFFSET 16

#define	CM_SERDES_CFG_REG_CM_SERDES_STATUS_CLEAR_MASK 0x00030000

#define	CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_OFF 0b01

#define	CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_ON 0b10

#define	CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_OFFSET 0

#define	CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_DISABLE 0b0

#define	CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_ENABLE 0b1

#define	CM_VO_CFG_REG 0x00001b34

#define	CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16

#define	CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK 0x00030000

#define	CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF 0b01

#define	CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON 0b10

#define	CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0

#define	CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE 0b0

#define	CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE 0b1

#define	CM_RV_CFG_REG 0x00001b40

#define	CM_RV_CFG_REG_CM_RV_STATUS_OFFSET 16

#define	CM_RV_CFG_REG_CM_RV_STATUS_CLEAR_MASK 0x00030000

#define	CM_RV_CFG_REG_CM_RV_STATUS_POWER_OFF 0b01

#define	CM_RV_CFG_REG_CM_RV_STATUS_POWER_ON 0b10

#define	CM_RV_CFG_REG_CM_RV_MODULE_MODE_OFFSET 0

#define	CM_RV_CFG_REG_CM_RV_MODULE_MODE_CLEAR_MASK 0x00000001

#define	CM_RV_CFG_REG_CM_RV_MODULE_MODE_DISABLE 0b0

#define	CM_RV_CFG_REG_CM_RV_MODULE_MODE_ENABLE 0b1

#define	CCU_SEC_SWITCH_REG 0x00001f00

#define	CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2

#define	CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004

#define	CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0

#define	CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1

#define	CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1

#define	CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002

#define	CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0

#define	CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1

#define	CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0

#define	CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001

#define	CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0

#define	CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1

#define	SYSDAP_REQ_CTRL_REG 0x00001f10

#define	SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0

#define	SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK 0x00000001

#define	PLL_CFG0_REG 0x00001f20

#define	PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0

#define	PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff

#define	PLL_CFG1_REG 0x00001f24

#define	PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0

#define	PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff

#define	PLL_CFG2_REG 0x00001f28

#define	PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0

#define	PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff

#define	PLL_LOCK_DBG_CTRL_REG 0x00001f2c

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x00f00000

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL 0b0000

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0b0001

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL 0b0010

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL 0b0011

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0100

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0101

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL 0b0110

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0111

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0b1000

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b1001

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL 0b1010

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL 0b1011

#define	PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_USBPLL 0b1100

#define	CCU_FAN_GATE_REG 0x00001f30

#define	CCU_FAN_GATE_REG_CLK50M_EN_OFFSET 4

#define	CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK 0x00000010

#define	CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3

#define	CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008

#define	CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2

#define	CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004

#define	CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1

#define	CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002

#define	CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0

#define	CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001

#define	CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1

#define	CLK27M_FAN_REG 0x00001f34

#define	CLK27M_FAN_REG_CLK27M_EN_OFFSET 31

#define	CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000

#define	CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0

#define	CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1

#define	CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24

#define	CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000

#define	CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000

#define	CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001

#define	CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8

#define	CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00

#define	CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0

#define	CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f

#define	CLK_FAN_REG 0x00001f38

#define	CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31

#define	CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000

#define	CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0

#define	CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1

#define	CLK_FAN_REG_PCLK_DIV1_OFFSET 5

#define	CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0

#define	CLK_FAN_REG_PCLK_DIV_OFFSET 0

#define	CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f

#define	CCU_FAN_REG 0x00001f3c

#define	CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23

#define	CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK 0x00800000

#define	CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22

#define	CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK 0x00400000

#define	CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21

#define	CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK 0x00200000

#define	CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0b0

#define	CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0b1

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK 0x000001c0

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2 0b001

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO 0b011

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0b101

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0b110

#define	CCU_FAN_REG_CLK_FANOUT2_SEL_CLK50M_FROM_PERI0_150M_3 0b111

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK 0x00000038

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2 0b001

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO 0b011

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0b101

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0b110

#define	CCU_FAN_REG_CLK_FANOUT1_SEL_CLK50M_FROM_PERI0_150M_3 0b111

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK 0x00000007

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2 0b001

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 0b010

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO 0b011

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 0b100

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0b101

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0b110

#define	CCU_FAN_REG_CLK_FANOUT0_SEL_CLK50M_FROM_PERI0_150M_3 0b111

#define	BUS_CLK_DBG_REG 0x00001f50

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK 0x00000007

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK 0b000

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK 0b001

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK 0b010

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK 0b011

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK 0b100

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK 0b101

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR_CLK 0b110

#define	BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_1_B0 0b111

#define	CCU_VERSION_REG 0x00001ff0

#define	CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16

#define	CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK 0xffff0000

#define	CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0

#define	CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK 0x0000ffff

#define	CCU_REG_PLL_C0_CPUX (SUNXI_CPU_PLL_CFG_BASE + 0x4)

#define	CCU_REG_PLL_C0_DSU (SUNXI_CPU_PLL_CFG_BASE + 0x8)

#define	CCU_REG_DSU_CLK (SUNXI_CPU_PLL_CFG_BASE + 0x4c)

#define	CCU_APB_CFG_GREG (SUNXI_CCU_BASE + APB0_CLK_REG)

#define	CCU_APB1_CFG_GREG (SUNXI_CCU_BASE + APB1_CLK_REG)

#define	CCU_MBUS_CFG_REG (SUNXI_CCU_BASE + MBUS_CLK_REG)

#define	CCU_NSI_CLK_GREG (SUNXI_CCU_BASE + NSI_CLK_REG)

#define	CCU_NSI_BGR_REG (SUNXI_CCU_BASE + NSI_BGR_REG)

#define	CCU_CE_CLK_REG (SUNXI_CCU_BASE + CE_CLK_REG)

#define	CCU_CE_BGR_REG (SUNXI_CCU_BASE + CE_BGR_REG)

#define	CCU_DMA_BGR_REG (SUNXI_CCU_BASE + DMA0_BGR_REG)

#define	CCU_MBUS_MST_CLK_GATING_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

#define	CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG)

#define	CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG)

#define	CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG)

#define	CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_BGR_REG)

#define	CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_BGR_REG)

#define	CE_CLK_SRC_MASK (0x1)

#define	CE_CLK_SRC_SEL_BIT CE_CLK_REG_CLK_SRC_SEL_OFFSET

#define	CE_CLK_SRC CE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define	CE_CLK_DIV_RATION_M_BIT CE_CLK_REG_FACTOR_M_OFFSET

#define	CE_CLK_DIV_RATION_M_MASK CE_CLK_REG_FACTOR_M_CLEAR_MASK

#define	CE_CLK_DIV_RATION_M (2)

#define	CE_SCLK_ONOFF_BIT (31)

#define	CE_SCLK_ON (1)

#define	CE_GATING_BASE CCU_CE_BGR_REG

#define	CE_GATING_PASS (1)

#define	CE_GATING_BIT (0)

#define	CE_RST_REG_BASE CCU_CE_BGR_REG

#define	CE_RST_BIT CE_BGR_REG_CE_RST_OFFSET

#define	CE_DEASSERT (1)

#define	CE_SYS_GATING_BIT CE_BGR_REG_CE_GATING_MASK

#define	CE_SYS_RST_BIT CE_BGR_REG_CE_SYS_RST_OFFSET

#define	CCU_GPADC_CLK_REG (SUNXI_CCU_BASE + GPADC1_CLK_REG)

#define	CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC1_BGR_REG)

#define	CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + LRADC_BGR_REG)

#define	APB0_CLK_REG_FACTOR_N_OFFSET 8

#define	APB0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00000300

Macro Definition Documentation

◆ AHB_CLK_REG

#define AHB_CLK_REG 0x00000500

◆ AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK32K

#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

◆ AHB_CLK_REG_CLK_SRC_SEL_HOSC

#define AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

◆ AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ AHB_CLK_REG_FACTOR_M_OFFSET

#define AHB_CLK_REG_FACTOR_M_OFFSET 0

◆ AHB_GATE_EN_REG

#define AHB_GATE_EN_REG 0x000005c0

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK 0x10000000

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00002000

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 13

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00004000

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 14

◆ AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00001000

◆ AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_MCU_SYS_AHB_GATE_SW_CFG_OFFSET 12

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00008000

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 15

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0b0

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0b1

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000020

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00020000

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET 17

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000040

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00040000

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET 18

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00080000

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET 19

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00400000

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET 22

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000010

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET 4

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET 16

◆ AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000800

◆ AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_SYS_AHB_GATE_SW_CFG_OFFSET 11

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET 1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE 0b0

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE 0b1

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3

◆ APB0_CLK_REG

#define APB0_CLK_REG 0x00000510

◆ APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

◆ APB0_CLK_REG_CLK_SRC_SEL_HOSC

#define APB0_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ APB0_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

◆ APB0_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ APB0_CLK_REG_FACTOR_M_OFFSET

#define APB0_CLK_REG_FACTOR_M_OFFSET 0

◆ APB0_CLK_REG_FACTOR_N_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00000300

◆ APB0_CLK_REG_FACTOR_N_OFFSET

#define APB0_CLK_REG_FACTOR_N_OFFSET 8

◆ APB1_CLK_REG

#define APB1_CLK_REG 0x00000518

◆ APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

◆ APB1_CLK_REG_CLK_SRC_SEL_HOSC

#define APB1_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ APB1_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b11

◆ APB1_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ APB1_CLK_REG_FACTOR_M_OFFSET

#define APB1_CLK_REG_FACTOR_M_OFFSET 0

◆ APB_UART_CLK_REG

#define APB_UART_CLK_REG 0x00000538

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

◆ APB_UART_CLK_REG_CLK_SRC_SEL_HOSC

#define APB_UART_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS 0b100

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0b011

◆ APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ APB_UART_CLK_REG_FACTOR_M_OFFSET

#define APB_UART_CLK_REG_FACTOR_M_OFFSET 0

◆ AUDIO_CODEC_BGR_REG

#define AUDIO_CODEC_BGR_REG 0x000012ec

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK 0x00000001

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK 0b0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET 0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS 0b1

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT 0b0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK 0x00010000

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT 0b1

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET 16

◆ AUDIO_CODEC_DAC_1X_CLK_REG

#define AUDIO_CODEC_DAC_1X_CLK_REG 0x000012e0

◆ AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

◆ AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

◆ AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIO_CODEC_DAC_1X_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_OFFSET

#define AUDIO_CODEC_DAC_1X_CLK_REG_FACTOR_M_OFFSET 0

◆ AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLEAR_MASK

#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

◆ AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

◆ AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

◆ AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_OFFSET

#define AUDIO_CODEC_DAC_1X_CLK_REG_SCLK_GATING_OFFSET 31

◆ BUS_CLK_DBG_REG

#define BUS_CLK_DBG_REG 0x00001f50

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_1_B0

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_1_B0 0b111

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_AHB_CLOCK 0b000

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB0_CLOCK 0b001

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB1_CLOCK 0b010

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_APB_UART_CLOCK 0b011

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_CLEAR_MASK 0x00000007

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR_CLK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_DDR_CLK 0b110

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_MBUS_CLOCK 0b100

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_NSI_CLOCK 0b101

◆ BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET

#define BUS_CLK_DBG_REG_BUS_CLK_DBG_SEL_OFFSET 0

◆ CCU_APB1_CFG_GREG

#define CCU_APB1_CFG_GREG (SUNXI_CCU_BASE + APB1_CLK_REG)

◆ CCU_APB_CFG_GREG

#define CCU_APB_CFG_GREG (SUNXI_CCU_BASE + APB0_CLK_REG)

◆ CCU_CE_BGR_REG

#define CCU_CE_BGR_REG (SUNXI_CCU_BASE + CE_BGR_REG)

◆ CCU_CE_CLK_REG

#define CCU_CE_CLK_REG (SUNXI_CCU_BASE + CE_CLK_REG)

◆ CCU_DMA_BGR_REG

#define CCU_DMA_BGR_REG (SUNXI_CCU_BASE + DMA0_BGR_REG)

◆ CCU_FAN_GATE_REG

#define CCU_FAN_GATE_REG 0x00001f30

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_GATE_REG_CLK12M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_GATE_REG_CLK16M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_GATE_REG_CLK24M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_GATE_REG_CLK25M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK50M_EN_CLEAR_MASK 0x00000010

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK50M_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_GATE_REG_CLK50M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK50M_EN_OFFSET 4

◆ CCU_FAN_REG

#define CCU_FAN_REG 0x00001f3c

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK 0x00200000

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK 0x00000007

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2 0b001

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 0b010

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO 0b011

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 0b100

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0b101

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK50M_FROM_PERI0_150M_3 0b111

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0b110

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK 0x00400000

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK 0x00000038

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2 0b001

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 0b010

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO 0b011

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 0b100

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0b101

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK50M_FROM_PERI0_150M_3 0b111

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0b110

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK 0x00800000

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0b0

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0b1

◆ CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK 0x000001c0

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2 0b001

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 0b010

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO 0b011

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 0b100

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0b101

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0b000

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK50M_FROM_PERI0_150M_3

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK50M_FROM_PERI0_150M_3 0b111

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0b110

◆ CCU_GPADC_BGR_REG

#define CCU_GPADC_BGR_REG (SUNXI_CCU_BASE + GPADC1_BGR_REG)

◆ CCU_GPADC_CLK_REG

#define CCU_GPADC_CLK_REG (SUNXI_CCU_BASE + GPADC1_CLK_REG)

◆ CCU_LRADC_BGR_REG

#define CCU_LRADC_BGR_REG (SUNXI_CCU_BASE + LRADC_BGR_REG)

◆ CCU_MBUS_CFG_REG

#define CCU_MBUS_CFG_REG (SUNXI_CCU_BASE + MBUS_CLK_REG)

◆ CCU_MBUS_MST_CLK_GATING_REG

#define CCU_MBUS_MST_CLK_GATING_REG (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

◆ CCU_NSI_BGR_REG

#define CCU_NSI_BGR_REG (SUNXI_CCU_BASE + NSI_BGR_REG)

◆ CCU_NSI_CLK_GREG

#define CCU_NSI_CLK_GREG (SUNXI_CCU_BASE + NSI_CLK_REG)

◆ CCU_REG_DSU_CLK

#define CCU_REG_DSU_CLK (SUNXI_CPU_PLL_CFG_BASE + 0x4c)

◆ CCU_REG_PLL_C0_CPUX

#define CCU_REG_PLL_C0_CPUX (SUNXI_CPU_PLL_CFG_BASE + 0x4)

◆ CCU_REG_PLL_C0_DSU

#define CCU_REG_PLL_C0_DSU (SUNXI_CPU_PLL_CFG_BASE + 0x8)

◆ CCU_SDMMC0_CLK_REG

#define CCU_SDMMC0_CLK_REG (SUNXI_CCU_BASE + SMHC0_CLK_REG)

◆ CCU_SDMMC1_CLK_REG

#define CCU_SDMMC1_CLK_REG (SUNXI_CCU_BASE + SMHC1_CLK_REG)

◆ CCU_SDMMC2_CLK_REG

#define CCU_SDMMC2_CLK_REG (SUNXI_CCU_BASE + SMHC2_CLK_REG)

◆ CCU_SEC_SWITCH_REG

#define CCU_SEC_SWITCH_REG 0x00001f00

◆ CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002

◆ CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0b1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0b0

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0b1

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0b0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001

◆ CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0b1

◆ CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0b0

◆ CCU_SMHC0_BGR_REG

#define CCU_SMHC0_BGR_REG (SUNXI_CCU_BASE + SMHC0_BGR_REG)

◆ CCU_UART_BGR_REG

#define CCU_UART_BGR_REG (SUNXI_CCU_BASE + UART0_BGR_REG)

◆ CCU_VERSION_REG

#define CCU_VERSION_REG 0x00001ff0

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK 0xffff0000

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16

◆ CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK 0x0000ffff

◆ CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0

◆ CE_BGR_REG

#define CE_BGR_REG 0x00000ac4

◆ CE_BGR_REG_CE_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_GATING_CLEAR_MASK 0x00000001

◆ CE_BGR_REG_CE_GATING_MASK

#define CE_BGR_REG_CE_GATING_MASK 0b0

◆ CE_BGR_REG_CE_GATING_OFFSET

#define CE_BGR_REG_CE_GATING_OFFSET 0

◆ CE_BGR_REG_CE_GATING_SECURE_DEBUG

#define CE_BGR_REG_CE_GATING_SECURE_DEBUG 0b1

◆ CE_BGR_REG_CE_RST_ASSERT

#define CE_BGR_REG_CE_RST_ASSERT 0b0

◆ CE_BGR_REG_CE_RST_CLEAR_MASK

#define CE_BGR_REG_CE_RST_CLEAR_MASK 0x00010000

◆ CE_BGR_REG_CE_RST_OFFSET

#define CE_BGR_REG_CE_RST_OFFSET 16

◆ CE_BGR_REG_CE_RST_SECURE_DEBUG

#define CE_BGR_REG_CE_RST_SECURE_DEBUG 0b1

◆ CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK 0x00000002

◆ CE_BGR_REG_CE_SYS_GATING_MASK

#define CE_BGR_REG_CE_SYS_GATING_MASK 0b0

◆ CE_BGR_REG_CE_SYS_GATING_OFFSET

#define CE_BGR_REG_CE_SYS_GATING_OFFSET 1

◆ CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG

#define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG 0b1

◆ CE_BGR_REG_CE_SYS_RST_ASSERT

#define CE_BGR_REG_CE_SYS_RST_ASSERT 0b0

◆ CE_BGR_REG_CE_SYS_RST_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK 0x00020000

◆ CE_BGR_REG_CE_SYS_RST_OFFSET

#define CE_BGR_REG_CE_SYS_RST_OFFSET 17

◆ CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG

#define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG 0b1

◆ CE_CLK_DIV_RATION_M

#define CE_CLK_DIV_RATION_M (2)

◆ CE_CLK_DIV_RATION_M_BIT

#define CE_CLK_DIV_RATION_M_BIT CE_CLK_REG_FACTOR_M_OFFSET

◆ CE_CLK_DIV_RATION_M_MASK

#define CE_CLK_DIV_RATION_M_MASK CE_CLK_REG_FACTOR_M_CLEAR_MASK

◆ CE_CLK_REG

#define CE_CLK_REG 0x00000ac0

◆ CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK

#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK 0x80000000

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CE_CLK_REG_CE_CLK_GATING_OFFSET

#define CE_CLK_REG_CE_CLK_GATING_OFFSET 31

◆ CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG

#define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG 0b1

◆ CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CE_CLK_REG_CLK_SRC_SEL_HOSC

#define CE_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ CE_CLK_REG_CLK_SRC_SEL_OFFSET

#define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ CE_CLK_REG_FACTOR_M_CLEAR_MASK

#define CE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CE_CLK_REG_FACTOR_M_OFFSET

#define CE_CLK_REG_FACTOR_M_OFFSET 0

◆ CE_CLK_SRC

#define CE_CLK_SRC CE_CLK_REG_CLK_SRC_SEL_PERI0_400M

◆ CE_CLK_SRC_MASK

#define CE_CLK_SRC_MASK (0x1)

◆ CE_CLK_SRC_SEL_BIT

#define CE_CLK_SRC_SEL_BIT CE_CLK_REG_CLK_SRC_SEL_OFFSET

◆ CE_DEASSERT

#define CE_DEASSERT (1)

◆ CE_GATING_BASE

#define CE_GATING_BASE CCU_CE_BGR_REG

◆ CE_GATING_BIT

#define CE_GATING_BIT (0)

◆ CE_GATING_PASS

#define CE_GATING_PASS (1)

◆ CE_RST_BIT

#define CE_RST_BIT CE_BGR_REG_CE_RST_OFFSET

◆ CE_RST_REG_BASE

#define CE_RST_REG_BASE CCU_CE_BGR_REG

◆ CE_SCLK_ON

#define CE_SCLK_ON (1)

◆ CE_SCLK_ONOFF_BIT

#define CE_SCLK_ONOFF_BIT (31)

◆ CE_SYS_GATING_BIT

#define CE_SYS_GATING_BIT CE_BGR_REG_CE_GATING_MASK

◆ CE_SYS_RST_BIT

#define CE_SYS_RST_BIT CE_BGR_REG_CE_SYS_RST_OFFSET

◆ CLK24M_GATE_EN_REG

#define CLK24M_GATE_EN_REG 0x00001a00

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK 0x00000008

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0b0

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0b1

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3

◆ CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_CLEAR_MASK 0x00000001

◆ CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_DISABLE 0b0

◆ CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_ENABLE 0b1

◆ CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_USB20_24M_GATE_EN_OFFSET 0

◆ CLK27M_FAN_REG

#define CLK27M_FAN_REG 0x00001f34

◆ CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f

◆ CLK27M_FAN_REG_CLK27M_DIV0_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0

◆ CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00

◆ CLK27M_FAN_REG_CLK27M_DIV1_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8

◆ CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0b0

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0b1

◆ CLK27M_FAN_REG_CLK27M_EN_OFFSET

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X 0b000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X 0b001

◆ CLK_FAN_REG

#define CLK_FAN_REG 0x00001f38

◆ CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0

◆ CLK_FAN_REG_PCLK_DIV1_OFFSET

#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5

◆ CLK_FAN_REG_PCLK_DIV_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f

◆ CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0b0

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0b1

◆ CLK_FAN_REG_PCLK_DIV_EN_OFFSET

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31

◆ CLK_FAN_REG_PCLK_DIV_OFFSET

#define CLK_FAN_REG_PCLK_DIV_OFFSET 0

◆ CM_NPU_CFG_REG

#define CM_NPU_CFG_REG 0x00001b1c

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE 0b0

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE 0b1

◆ CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET

#define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK

#define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK 0x00030000

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET

#define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF 0b01

◆ CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON

#define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON 0b10

◆ CM_RV_CFG_REG

#define CM_RV_CFG_REG 0x00001b40

◆ CM_RV_CFG_REG_CM_RV_MODULE_MODE_CLEAR_MASK

#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_RV_CFG_REG_CM_RV_MODULE_MODE_DISABLE

#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_DISABLE 0b0

◆ CM_RV_CFG_REG_CM_RV_MODULE_MODE_ENABLE

#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_ENABLE 0b1

◆ CM_RV_CFG_REG_CM_RV_MODULE_MODE_OFFSET

#define CM_RV_CFG_REG_CM_RV_MODULE_MODE_OFFSET 0

◆ CM_RV_CFG_REG_CM_RV_STATUS_CLEAR_MASK

#define CM_RV_CFG_REG_CM_RV_STATUS_CLEAR_MASK 0x00030000

◆ CM_RV_CFG_REG_CM_RV_STATUS_OFFSET

#define CM_RV_CFG_REG_CM_RV_STATUS_OFFSET 16

◆ CM_RV_CFG_REG_CM_RV_STATUS_POWER_OFF

#define CM_RV_CFG_REG_CM_RV_STATUS_POWER_OFF 0b01

◆ CM_RV_CFG_REG_CM_RV_STATUS_POWER_ON

#define CM_RV_CFG_REG_CM_RV_STATUS_POWER_ON 0b10

◆ CM_SERDES_CFG_REG

#define CM_SERDES_CFG_REG 0x00001b28

◆ CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_CLEAR_MASK

#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_DISABLE

#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_DISABLE 0b0

◆ CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_ENABLE

#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_ENABLE 0b1

◆ CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_OFFSET

#define CM_SERDES_CFG_REG_CM_SERDES_MODULE_MODE_OFFSET 0

◆ CM_SERDES_CFG_REG_CM_SERDES_STATUS_CLEAR_MASK

#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_CLEAR_MASK 0x00030000

◆ CM_SERDES_CFG_REG_CM_SERDES_STATUS_OFFSET

#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_OFFSET 16

◆ CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_OFF

#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_OFF 0b01

◆ CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_ON

#define CM_SERDES_CFG_REG_CM_SERDES_STATUS_POWER_ON 0b10

◆ CM_VE_CFG_REG

#define CM_VE_CFG_REG 0x00001b10

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_DISABLE 0b0

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_ENABLE 0b1

◆ CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET

#define CM_VE_CFG_REG_CM_VE_MODULE_MODE_OFFSET 0

◆ CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK

#define CM_VE_CFG_REG_CM_VE_STATUS_CLEAR_MASK 0x00030000

◆ CM_VE_CFG_REG_CM_VE_STATUS_OFFSET

#define CM_VE_CFG_REG_CM_VE_STATUS_OFFSET 16

◆ CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF

#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_OFF 0b01

◆ CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON

#define CM_VE_CFG_REG_CM_VE_STATUS_POWER_ON 0b10

◆ CM_VI_CFG_REG

#define CM_VI_CFG_REG 0x00001b00

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE 0b0

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE 0b1

◆ CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET

#define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0

◆ CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK

#define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK 0x00030000

◆ CM_VI_CFG_REG_CM_VI_STATUS_OFFSET

#define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16

◆ CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF 0b01

◆ CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON

#define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON 0b10

◆ CM_VO_CFG_REG

#define CM_VO_CFG_REG 0x00001b34

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK 0x00000001

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE 0b0

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE 0b1

◆ CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET

#define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0

◆ CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK

#define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK 0x00030000

◆ CM_VO_CFG_REG_CM_VO_STATUS_OFFSET

#define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16

◆ CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF 0b01

◆ CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON

#define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON 0b10

◆ CSI_BGR_REG

#define CSI_BGR_REG 0x00001844

◆ CSI_BGR_REG_CSI_GATING_CLEAR_MASK

#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK 0x00000001

◆ CSI_BGR_REG_CSI_GATING_MASK

#define CSI_BGR_REG_CSI_GATING_MASK 0b0

◆ CSI_BGR_REG_CSI_GATING_OFFSET

#define CSI_BGR_REG_CSI_GATING_OFFSET 0

◆ CSI_BGR_REG_CSI_GATING_PASS

#define CSI_BGR_REG_CSI_GATING_PASS 0b1

◆ CSI_BGR_REG_CSI_RST_ASSERT

#define CSI_BGR_REG_CSI_RST_ASSERT 0b0

◆ CSI_BGR_REG_CSI_RST_CLEAR_MASK

#define CSI_BGR_REG_CSI_RST_CLEAR_MASK 0x00010000

◆ CSI_BGR_REG_CSI_RST_DE_ASSERT

#define CSI_BGR_REG_CSI_RST_DE_ASSERT 0b1

◆ CSI_BGR_REG_CSI_RST_OFFSET

#define CSI_BGR_REG_CSI_RST_OFFSET 16

◆ CSI_CLK_REG

#define CSI_CLK_REG 0x00001840

◆ CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CSI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

◆ CSI_CLK_REG_CLK_SRC_SEL_VEPLL

#define CSI_CLK_REG_CLK_SRC_SEL_VEPLL 0b111

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b110

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b101

◆ CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0b1

◆ CSI_CLK_REG_CSI_CLK_GATING_OFFSET

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31

◆ CSI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CSI_CLK_REG_FACTOR_M_OFFSET

#define CSI_CLK_REG_FACTOR_M_OFFSET 0

◆ CSI_MASTER0_CLK_REG

#define CSI_MASTER0_CLK_REG 0x00001800

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0b1

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31

◆ CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0

◆ CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8

◆ CSI_MASTER1_CLK_REG

#define CSI_MASTER1_CLK_REG 0x00001804

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0b1

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31

◆ CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0

◆ CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8

◆ CSI_MASTER2_CLK_REG

#define CSI_MASTER2_CLK_REG 0x00001808

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0b1

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31

◆ CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0

◆ CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8

◆ CSI_MASTER3_CLK_REG

#define CSI_MASTER3_CLK_REG 0x0000180c

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b100

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b011

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b010

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK 0x80000000

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF 0b0

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON 0b1

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31

◆ CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0

◆ CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8

◆ DBGSYS_BGR_REG

#define DBGSYS_BGR_REG 0x000007a4

◆ DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK 0x00000001

◆ DBGSYS_BGR_REG_DBGSYS_GATING_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0b0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_PASS

#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0b0

◆ DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK 0x00010000

◆ DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16

◆ DE0_BGR_REG

#define DE0_BGR_REG 0x00000a04

◆ DE0_BGR_REG_DE0_GATING_CLEAR_MASK

#define DE0_BGR_REG_DE0_GATING_CLEAR_MASK 0x00000001

◆ DE0_BGR_REG_DE0_GATING_MASK

#define DE0_BGR_REG_DE0_GATING_MASK 0b0

◆ DE0_BGR_REG_DE0_GATING_OFFSET

#define DE0_BGR_REG_DE0_GATING_OFFSET 0

◆ DE0_BGR_REG_DE0_GATING_PASS

#define DE0_BGR_REG_DE0_GATING_PASS 0b1

◆ DE0_BGR_REG_DE0_RST_ASSERT

#define DE0_BGR_REG_DE0_RST_ASSERT 0b0

◆ DE0_BGR_REG_DE0_RST_CLEAR_MASK

#define DE0_BGR_REG_DE0_RST_CLEAR_MASK 0x00010000

◆ DE0_BGR_REG_DE0_RST_DE_ASSERT

#define DE0_BGR_REG_DE0_RST_DE_ASSERT 0b1

◆ DE0_BGR_REG_DE0_RST_OFFSET

#define DE0_BGR_REG_DE0_RST_OFFSET 16

◆ DE0_CLK_REG

#define DE0_CLK_REG 0x00000a00

◆ DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ DE0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

◆ DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK

#define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK 0x80000000

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON

#define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON 0b1

◆ DE0_CLK_REG_DE0_CLK_GATING_OFFSET

#define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31

◆ DE0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ DE0_CLK_REG_FACTOR_M_OFFSET

#define DE0_CLK_REG_FACTOR_M_OFFSET 0

◆ DE_SYS_BGR_REG

#define DE_SYS_BGR_REG 0x00000a74

◆ DE_SYS_BGR_REG_DE_SYS_RST_ASSERT

#define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT 0b0

◆ DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK

#define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK 0x00010000

◆ DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT

#define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT 0b1

◆ DE_SYS_BGR_REG_DE_SYS_RST_OFFSET

#define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16

◆ DMA0_BGR_REG

#define DMA0_BGR_REG 0x00000704

◆ DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK

#define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK 0x00000001

◆ DMA0_BGR_REG_DMA0_GATING_MASK

#define DMA0_BGR_REG_DMA0_GATING_MASK 0b0

◆ DMA0_BGR_REG_DMA0_GATING_OFFSET

#define DMA0_BGR_REG_DMA0_GATING_OFFSET 0

◆ DMA0_BGR_REG_DMA0_GATING_PASS

#define DMA0_BGR_REG_DMA0_GATING_PASS 0b1

◆ DMA0_BGR_REG_DMA0_RST_ASSERT

#define DMA0_BGR_REG_DMA0_RST_ASSERT 0b0

◆ DMA0_BGR_REG_DMA0_RST_CLEAR_MASK

#define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK 0x00010000

◆ DMA0_BGR_REG_DMA0_RST_DE_ASSERT

#define DMA0_BGR_REG_DMA0_RST_DE_ASSERT 0b1

◆ DMA0_BGR_REG_DMA0_RST_OFFSET

#define DMA0_BGR_REG_DMA0_RST_OFFSET 16

◆ DMA1_BGR_REG

#define DMA1_BGR_REG 0x0000070c

◆ DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK

#define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK 0x00000001

◆ DMA1_BGR_REG_DMA1_GATING_MASK

#define DMA1_BGR_REG_DMA1_GATING_MASK 0b0

◆ DMA1_BGR_REG_DMA1_GATING_OFFSET

#define DMA1_BGR_REG_DMA1_GATING_OFFSET 0

◆ DMA1_BGR_REG_DMA1_GATING_PASS

#define DMA1_BGR_REG_DMA1_GATING_PASS 0b1

◆ DMA1_BGR_REG_DMA1_RST_ASSERT

#define DMA1_BGR_REG_DMA1_RST_ASSERT 0b0

◆ DMA1_BGR_REG_DMA1_RST_CLEAR_MASK

#define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK 0x00010000

◆ DMA1_BGR_REG_DMA1_RST_DE_ASSERT

#define DMA1_BGR_REG_DMA1_RST_DE_ASSERT 0b1

◆ DMA1_BGR_REG_DMA1_RST_OFFSET

#define DMA1_BGR_REG_DMA1_RST_OFFSET 16

◆ DMIC_BGR_REG

#define DMIC_BGR_REG 0x000012cc

◆ DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK

#define DMIC_BGR_REG_DMIC_GATING_CLEAR_MASK 0x00000001

◆ DMIC_BGR_REG_DMIC_GATING_MASK

#define DMIC_BGR_REG_DMIC_GATING_MASK 0b0

◆ DMIC_BGR_REG_DMIC_GATING_OFFSET

#define DMIC_BGR_REG_DMIC_GATING_OFFSET 0

◆ DMIC_BGR_REG_DMIC_GATING_PASS

#define DMIC_BGR_REG_DMIC_GATING_PASS 0b1

◆ DMIC_BGR_REG_DMIC_RST_ASSERT

#define DMIC_BGR_REG_DMIC_RST_ASSERT 0b0

◆ DMIC_BGR_REG_DMIC_RST_CLEAR_MASK

#define DMIC_BGR_REG_DMIC_RST_CLEAR_MASK 0x00010000

◆ DMIC_BGR_REG_DMIC_RST_DE_ASSERT

#define DMIC_BGR_REG_DMIC_RST_DE_ASSERT 0b1

◆ DMIC_BGR_REG_DMIC_RST_OFFSET

#define DMIC_BGR_REG_DMIC_RST_OFFSET 16

◆ DMIC_CLK_REG

#define DMIC_CLK_REG 0x000012c0

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

◆ DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define DMIC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

◆ DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DMIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ DMIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define DMIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLEAR_MASK 0x80000000

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_OFF 0b0

◆ DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON

#define DMIC_CLK_REG_DMIC_CLK_GATING_CLOCK_IS_ON 0b1

◆ DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET

#define DMIC_CLK_REG_DMIC_CLK_GATING_OFFSET 31

◆ DMIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define DMIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ DMIC_CLK_REG_FACTOR_M_OFFSET

#define DMIC_CLK_REG_FACTOR_M_OFFSET 0

◆ DPSS_BGR_REG

#define DPSS_BGR_REG 0x000016c4

◆ DPSS_BGR_REG_DPSS_GATING_CLEAR_MASK

#define DPSS_BGR_REG_DPSS_GATING_CLEAR_MASK 0x00000001

◆ DPSS_BGR_REG_DPSS_GATING_MASK

#define DPSS_BGR_REG_DPSS_GATING_MASK 0b0

◆ DPSS_BGR_REG_DPSS_GATING_OFFSET

#define DPSS_BGR_REG_DPSS_GATING_OFFSET 0

◆ DPSS_BGR_REG_DPSS_GATING_PASS

#define DPSS_BGR_REG_DPSS_GATING_PASS 0b1

◆ DPSS_BGR_REG_DPSS_RST_ASSERT

#define DPSS_BGR_REG_DPSS_RST_ASSERT 0b0

◆ DPSS_BGR_REG_DPSS_RST_CLEAR_MASK

#define DPSS_BGR_REG_DPSS_RST_CLEAR_MASK 0x00010000

◆ DPSS_BGR_REG_DPSS_RST_DE_ASSERT

#define DPSS_BGR_REG_DPSS_RST_DE_ASSERT 0b1

◆ DPSS_BGR_REG_DPSS_RST_OFFSET

#define DPSS_BGR_REG_DPSS_RST_OFFSET 16

◆ DRAM_BGR_REG

#define DRAM_BGR_REG 0x00000c0c

◆ DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK 0x00000001

◆ DRAM_BGR_REG_DRAM_GATING_MASK

#define DRAM_BGR_REG_DRAM_GATING_MASK 0b0

◆ DRAM_BGR_REG_DRAM_GATING_OFFSET

#define DRAM_BGR_REG_DRAM_GATING_OFFSET 0

◆ DRAM_BGR_REG_DRAM_GATING_PASS

#define DRAM_BGR_REG_DRAM_GATING_PASS 0b1

◆ DRAM_BGR_REG_DRAM_RST_ASSERT

#define DRAM_BGR_REG_DRAM_RST_ASSERT 0b0

◆ DRAM_BGR_REG_DRAM_RST_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK 0x00010000

◆ DRAM_BGR_REG_DRAM_RST_DE_ASSERT

#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT 0b1

◆ DRAM_BGR_REG_DRAM_RST_OFFSET

#define DRAM_BGR_REG_DRAM_RST_OFFSET 16

◆ DRAM_CLK_REG

#define DRAM_CLK_REG 0x00000c00

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK 0x80000000

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0b0

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0b1

◆ DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31

◆ DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK 0x07000000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL

#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0b000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_HOSC

#define DRAM_CLK_REG_DRAM_CLK_SEL_HOSC 0b101

◆ DRAM_CLK_REG_DRAM_CLK_SEL_NPUPLL

#define DRAM_CLK_REG_DRAM_CLK_SEL_NPUPLL 0b100

◆ DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M 0b011

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M 0b010

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_800M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_800M 0b001

◆ DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK 0x0000001f

◆ DRAM_CLK_REG_DRAM_DIV1_OFFSET

#define DRAM_CLK_REG_DRAM_DIV1_OFFSET 0

◆ DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK 0x08000000

◆ DRAM_CLK_REG_DRAM_UPD_INVALID

#define DRAM_CLK_REG_DRAM_UPD_INVALID 0b0

◆ DRAM_CLK_REG_DRAM_UPD_OFFSET

#define DRAM_CLK_REG_DRAM_UPD_OFFSET 27

◆ DRAM_CLK_REG_DRAM_UPD_VALID

#define DRAM_CLK_REG_DRAM_UPD_VALID 0b1

◆ DSI0_BGR_REG

#define DSI0_BGR_REG 0x00001584

◆ DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK

#define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK 0x00000001

◆ DSI0_BGR_REG_DSI0_GATING_MASK

#define DSI0_BGR_REG_DSI0_GATING_MASK 0b0

◆ DSI0_BGR_REG_DSI0_GATING_OFFSET

#define DSI0_BGR_REG_DSI0_GATING_OFFSET 0

◆ DSI0_BGR_REG_DSI0_GATING_PASS

#define DSI0_BGR_REG_DSI0_GATING_PASS 0b1

◆ DSI0_BGR_REG_DSI0_RST_ASSERT

#define DSI0_BGR_REG_DSI0_RST_ASSERT 0b0

◆ DSI0_BGR_REG_DSI0_RST_CLEAR_MASK

#define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK 0x00010000

◆ DSI0_BGR_REG_DSI0_RST_DE_ASSERT

#define DSI0_BGR_REG_DSI0_RST_DE_ASSERT 0b1

◆ DSI0_BGR_REG_DSI0_RST_OFFSET

#define DSI0_BGR_REG_DSI0_RST_OFFSET 16

◆ DSI0_CLK_REG

#define DSI0_CLK_REG 0x00001580

◆ DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ DSI0_CLK_REG_CLK_SRC_SEL_HOSC

#define DSI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ DSI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0b010

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b001

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK 0x80000000

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0b1

◆ DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET

#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31

◆ DSI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ DSI0_CLK_REG_FACTOR_M_OFFSET

#define DSI0_CLK_REG_FACTOR_M_OFFSET 0

◆ G2D_BGR_REG

#define G2D_BGR_REG 0x00000a44

◆ G2D_BGR_REG_G2D_GATING_CLEAR_MASK

#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK 0x00000001

◆ G2D_BGR_REG_G2D_GATING_MASK

#define G2D_BGR_REG_G2D_GATING_MASK 0b0

◆ G2D_BGR_REG_G2D_GATING_OFFSET

#define G2D_BGR_REG_G2D_GATING_OFFSET 0

◆ G2D_BGR_REG_G2D_GATING_PASS

#define G2D_BGR_REG_G2D_GATING_PASS 0b1

◆ G2D_BGR_REG_G2D_RST_ASSERT

#define G2D_BGR_REG_G2D_RST_ASSERT 0b0

◆ G2D_BGR_REG_G2D_RST_CLEAR_MASK

#define G2D_BGR_REG_G2D_RST_CLEAR_MASK 0x00010000

◆ G2D_BGR_REG_G2D_RST_DE_ASSERT

#define G2D_BGR_REG_G2D_RST_DE_ASSERT 0b1

◆ G2D_BGR_REG_G2D_RST_OFFSET

#define G2D_BGR_REG_G2D_RST_OFFSET 16

◆ G2D_CLK_REG

#define G2D_CLK_REG 0x00000a40

◆ G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ G2D_CLK_REG_CLK_SRC_SEL_OFFSET

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

◆ G2D_CLK_REG_FACTOR_M_CLEAR_MASK

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ G2D_CLK_REG_FACTOR_M_OFFSET

#define G2D_CLK_REG_FACTOR_M_OFFSET 0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0b0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0b1

◆ G2D_CLK_REG_G2D_CLK_GATING_OFFSET

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31

◆ GIC_CLK_REG

#define GIC_CLK_REG 0x00000560

◆ GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ GIC_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define GIC_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b010

◆ GIC_CLK_REG_CLK_SRC_SEL_CLK32K

#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0b001

◆ GIC_CLK_REG_CLK_SRC_SEL_HOSC

#define GIC_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ GIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

◆ GIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GIC_CLK_REG_FACTOR_M_OFFSET

#define GIC_CLK_REG_FACTOR_M_OFFSET 0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK

#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK 0x80000000

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0b1

◆ GIC_CLK_REG_GIC_CLK_GATING_OFFSET

#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31

◆ GMAC0_BGR_REG

#define GMAC0_BGR_REG 0x0000140c

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT

#define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT 0b0

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK 0x00020000

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT

#define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT 0b1

◆ GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET

#define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17

◆ GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK 0x00000001

◆ GMAC0_BGR_REG_GMAC0_GATING_MASK

#define GMAC0_BGR_REG_GMAC0_GATING_MASK 0b0

◆ GMAC0_BGR_REG_GMAC0_GATING_OFFSET

#define GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0

◆ GMAC0_BGR_REG_GMAC0_GATING_PASS

#define GMAC0_BGR_REG_GMAC0_GATING_PASS 0b1

◆ GMAC0_BGR_REG_GMAC0_RST_ASSERT

#define GMAC0_BGR_REG_GMAC0_RST_ASSERT 0b0

◆ GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK

#define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK 0x00010000

◆ GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT

#define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT 0b1

◆ GMAC0_BGR_REG_GMAC0_RST_OFFSET

#define GMAC0_BGR_REG_GMAC0_RST_OFFSET 16

◆ GMAC0_PHY_CLK_REG

#define GMAC0_PHY_CLK_REG 0x00001400

◆ GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET

#define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK 0x80000000

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON 0b1

◆ GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET

#define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31

◆ GMAC0_PTP_CLK_REG

#define GMAC0_PTP_CLK_REG 0x00001404

◆ GMAC0_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ GMAC0_PTP_CLK_REG_CLK_SRC_SEL_HOSC

#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ GMAC0_PTP_CLK_REG_CLK_SRC_SEL_OFFSET

#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GMAC0_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define GMAC0_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

◆ GMAC0_PTP_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC0_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GMAC0_PTP_CLK_REG_FACTOR_M_OFFSET

#define GMAC0_PTP_CLK_REG_FACTOR_M_OFFSET 0

◆ GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLEAR_MASK

#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLEAR_MASK 0x80000000

◆ GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_OFF

#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_ON

#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_CLOCK_IS_ON 0b1

◆ GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_OFFSET

#define GMAC0_PTP_CLK_REG_GMAC0_PTP_CLK_GATING_OFFSET 31

◆ GMAC1_BGR_REG

#define GMAC1_BGR_REG 0x0000141c

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT

#define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT 0b0

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK 0x00020000

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT

#define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT 0b1

◆ GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET

#define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17

◆ GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK 0x00000001

◆ GMAC1_BGR_REG_GMAC1_GATING_MASKS

#define GMAC1_BGR_REG_GMAC1_GATING_MASKS 0b0

◆ GMAC1_BGR_REG_GMAC1_GATING_OFFSET

#define GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0

◆ GMAC1_BGR_REG_GMAC1_GATING_PASS

#define GMAC1_BGR_REG_GMAC1_GATING_PASS 0b1

◆ GMAC1_BGR_REG_GMAC1_RST_ASSERT

#define GMAC1_BGR_REG_GMAC1_RST_ASSERT 0b0

◆ GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK

#define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK 0x00010000

◆ GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT

#define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT 0b1

◆ GMAC1_BGR_REG_GMAC1_RST_OFFSET

#define GMAC1_BGR_REG_GMAC1_RST_OFFSET 16

◆ GMAC1_PHY_CLK_REG

#define GMAC1_PHY_CLK_REG 0x00001410

◆ GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET

#define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK 0x80000000

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON 0b1

◆ GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET

#define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31

◆ GMAC1_PTP_CLK_REG

#define GMAC1_PTP_CLK_REG 0x00001414

◆ GMAC1_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ GMAC1_PTP_CLK_REG_CLK_SRC_SEL_HOSC

#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ GMAC1_PTP_CLK_REG_CLK_SRC_SEL_OFFSET

#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GMAC1_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define GMAC1_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

◆ GMAC1_PTP_CLK_REG_FACTOR_M_CLEAR_MASK

#define GMAC1_PTP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GMAC1_PTP_CLK_REG_FACTOR_M_OFFSET

#define GMAC1_PTP_CLK_REG_FACTOR_M_OFFSET 0

◆ GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLEAR_MASK

#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLEAR_MASK 0x80000000

◆ GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_OFF

#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_ON

#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_CLOCK_IS_ON 0b1

◆ GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_OFFSET

#define GMAC1_PTP_CLK_REG_GMAC1_PTP_CLK_GATING_OFFSET 31

◆ GPADC0_BGR_REG

#define GPADC0_BGR_REG 0x00000fc4

◆ GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK

#define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK 0x00000001

◆ GPADC0_BGR_REG_GPADC0_GATING_MASK

#define GPADC0_BGR_REG_GPADC0_GATING_MASK 0b0

◆ GPADC0_BGR_REG_GPADC0_GATING_OFFSET

#define GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0

◆ GPADC0_BGR_REG_GPADC0_GATING_PASS

#define GPADC0_BGR_REG_GPADC0_GATING_PASS 0b1

◆ GPADC0_BGR_REG_GPADC0_RST_ASSERT

#define GPADC0_BGR_REG_GPADC0_RST_ASSERT 0b0

◆ GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK

#define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK 0x00010000

◆ GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT

#define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT 0b1

◆ GPADC0_BGR_REG_GPADC0_RST_OFFSET

#define GPADC0_BGR_REG_GPADC0_RST_OFFSET 16

◆ GPADC0_CLK_REG

#define GPADC0_CLK_REG 0x00000fc0

◆ GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M

#define GPADC0_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

◆ GPADC0_CLK_REG_CLK_SRC_SEL_HOSC

#define GPADC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GPADC0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

◆ GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GPADC0_CLK_REG_FACTOR_M_OFFSET

#define GPADC0_CLK_REG_FACTOR_M_OFFSET 0

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLEAR_MASK 0x80000000

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_CLOCK_IS_ON 0b1

◆ GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET

#define GPADC0_CLK_REG_GPADC0_CLK_GATING_OFFSET 31

◆ GPADC1_BGR_REG

#define GPADC1_BGR_REG 0x00000fcc

◆ GPADC1_BGR_REG_GPADC1_GATING_CLEAR_MASK

#define GPADC1_BGR_REG_GPADC1_GATING_CLEAR_MASK 0x00000001

◆ GPADC1_BGR_REG_GPADC1_GATING_MASK

#define GPADC1_BGR_REG_GPADC1_GATING_MASK 0b0

◆ GPADC1_BGR_REG_GPADC1_GATING_OFFSET

#define GPADC1_BGR_REG_GPADC1_GATING_OFFSET 0

◆ GPADC1_BGR_REG_GPADC1_GATING_PASS

#define GPADC1_BGR_REG_GPADC1_GATING_PASS 0b1

◆ GPADC1_BGR_REG_GPADC1_RST_ASSERT

#define GPADC1_BGR_REG_GPADC1_RST_ASSERT 0b0

◆ GPADC1_BGR_REG_GPADC1_RST_CLEAR_MASK

#define GPADC1_BGR_REG_GPADC1_RST_CLEAR_MASK 0x00010000

◆ GPADC1_BGR_REG_GPADC1_RST_DE_ASSERT

#define GPADC1_BGR_REG_GPADC1_RST_DE_ASSERT 0b1

◆ GPADC1_BGR_REG_GPADC1_RST_OFFSET

#define GPADC1_BGR_REG_GPADC1_RST_OFFSET 16

◆ GPADC1_CLK_REG

#define GPADC1_CLK_REG 0x00000fc8

◆ GPADC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ GPADC1_CLK_REG_CLK_SRC_SEL_CLK48M

#define GPADC1_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

◆ GPADC1_CLK_REG_CLK_SRC_SEL_HOSC

#define GPADC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ GPADC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GPADC1_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GPADC1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

◆ GPADC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GPADC1_CLK_REG_FACTOR_M_OFFSET

#define GPADC1_CLK_REG_FACTOR_M_OFFSET 0

◆ GPADC1_CLK_REG_GPADC1_CLK_GATING_CLEAR_MASK

#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLEAR_MASK 0x80000000

◆ GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_OFF

#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_ON

#define GPADC1_CLK_REG_GPADC1_CLK_GATING_CLOCK_IS_ON 0b1

◆ GPADC1_CLK_REG_GPADC1_CLK_GATING_OFFSET

#define GPADC1_CLK_REG_GPADC1_CLK_GATING_OFFSET 31

◆ GPADC2_BGR_REG

#define GPADC2_BGR_REG 0x00000fd4

◆ GPADC2_BGR_REG_GPADC2_GATING_CLEAR_MASK

#define GPADC2_BGR_REG_GPADC2_GATING_CLEAR_MASK 0x00000001

◆ GPADC2_BGR_REG_GPADC2_GATING_MASK

#define GPADC2_BGR_REG_GPADC2_GATING_MASK 0b0

◆ GPADC2_BGR_REG_GPADC2_GATING_OFFSET

#define GPADC2_BGR_REG_GPADC2_GATING_OFFSET 0

◆ GPADC2_BGR_REG_GPADC2_GATING_PASS

#define GPADC2_BGR_REG_GPADC2_GATING_PASS 0b1

◆ GPADC2_BGR_REG_GPADC2_RST_ASSERT

#define GPADC2_BGR_REG_GPADC2_RST_ASSERT 0b0

◆ GPADC2_BGR_REG_GPADC2_RST_CLEAR_MASK

#define GPADC2_BGR_REG_GPADC2_RST_CLEAR_MASK 0x00010000

◆ GPADC2_BGR_REG_GPADC2_RST_DE_ASSERT

#define GPADC2_BGR_REG_GPADC2_RST_DE_ASSERT 0b1

◆ GPADC2_BGR_REG_GPADC2_RST_OFFSET

#define GPADC2_BGR_REG_GPADC2_RST_OFFSET 16

◆ GPADC2_CLK_REG

#define GPADC2_CLK_REG 0x00000fd0

◆ GPADC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ GPADC2_CLK_REG_CLK_SRC_SEL_CLK48M

#define GPADC2_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

◆ GPADC2_CLK_REG_CLK_SRC_SEL_HOSC

#define GPADC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ GPADC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GPADC2_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GPADC2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

◆ GPADC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GPADC2_CLK_REG_FACTOR_M_OFFSET

#define GPADC2_CLK_REG_FACTOR_M_OFFSET 0

◆ GPADC2_CLK_REG_GPADC2_CLK_GATING_CLEAR_MASK

#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLEAR_MASK 0x80000000

◆ GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_OFF

#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_ON

#define GPADC2_CLK_REG_GPADC2_CLK_GATING_CLOCK_IS_ON 0b1

◆ GPADC2_CLK_REG_GPADC2_CLK_GATING_OFFSET

#define GPADC2_CLK_REG_GPADC2_CLK_GATING_OFFSET 31

◆ GPADC3_BGR_REG

#define GPADC3_BGR_REG 0x00000fdc

◆ GPADC3_BGR_REG_GPADC3_GATING_CLEAR_MASK

#define GPADC3_BGR_REG_GPADC3_GATING_CLEAR_MASK 0x00000001

◆ GPADC3_BGR_REG_GPADC3_GATING_MASK

#define GPADC3_BGR_REG_GPADC3_GATING_MASK 0b0

◆ GPADC3_BGR_REG_GPADC3_GATING_OFFSET

#define GPADC3_BGR_REG_GPADC3_GATING_OFFSET 0

◆ GPADC3_BGR_REG_GPADC3_GATING_PASS

#define GPADC3_BGR_REG_GPADC3_GATING_PASS 0b1

◆ GPADC3_BGR_REG_GPADC3_RST_ASSERT

#define GPADC3_BGR_REG_GPADC3_RST_ASSERT 0b0

◆ GPADC3_BGR_REG_GPADC3_RST_CLEAR_MASK

#define GPADC3_BGR_REG_GPADC3_RST_CLEAR_MASK 0x00010000

◆ GPADC3_BGR_REG_GPADC3_RST_DE_ASSERT

#define GPADC3_BGR_REG_GPADC3_RST_DE_ASSERT 0b1

◆ GPADC3_BGR_REG_GPADC3_RST_OFFSET

#define GPADC3_BGR_REG_GPADC3_RST_OFFSET 16

◆ GPADC3_CLK_REG

#define GPADC3_CLK_REG 0x00000fd8

◆ GPADC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPADC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ GPADC3_CLK_REG_CLK_SRC_SEL_CLK48M

#define GPADC3_CLK_REG_CLK_SRC_SEL_CLK48M 0b001

◆ GPADC3_CLK_REG_CLK_SRC_SEL_HOSC

#define GPADC3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ GPADC3_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPADC3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ GPADC3_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GPADC3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

◆ GPADC3_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ GPADC3_CLK_REG_FACTOR_M_OFFSET

#define GPADC3_CLK_REG_FACTOR_M_OFFSET 0

◆ GPADC3_CLK_REG_GPADC3_CLK_GATING_CLEAR_MASK

#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLEAR_MASK 0x80000000

◆ GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_OFF

#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_OFF 0b0

◆ GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_ON

#define GPADC3_CLK_REG_GPADC3_CLK_GATING_CLOCK_IS_ON 0b1

◆ GPADC3_CLK_REG_GPADC3_CLK_GATING_OFFSET

#define GPADC3_CLK_REG_GPADC3_CLK_GATING_OFFSET 31

◆ I2SPCM0_BGR_REG

#define I2SPCM0_BGR_REG 0x0000120c

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_CLEAR_MASK 0x00000001

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_MASK 0b0

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_OFFSET 0

◆ I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS

#define I2SPCM0_BGR_REG_I2SPCM0_GATING_PASS 0b1

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT

#define I2SPCM0_BGR_REG_I2SPCM0_RST_ASSERT 0b0

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK

#define I2SPCM0_BGR_REG_I2SPCM0_RST_CLEAR_MASK 0x00010000

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT

#define I2SPCM0_BGR_REG_I2SPCM0_RST_DE_ASSERT 0b1

◆ I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET

#define I2SPCM0_BGR_REG_I2SPCM0_RST_OFFSET 16

◆ I2SPCM0_CLK_REG

#define I2SPCM0_CLK_REG 0x00001200

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

◆ I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ I2SPCM0_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM0_CLK_REG_FACTOR_M_OFFSET 0

◆ I2SPCM0_CLK_REG_SCLK_GATING_CLEAR_MASK

#define I2SPCM0_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

◆ I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

◆ I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define I2SPCM0_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

◆ I2SPCM0_CLK_REG_SCLK_GATING_OFFSET

#define I2SPCM0_CLK_REG_SCLK_GATING_OFFSET 31

◆ I2SPCM1_BGR_REG

#define I2SPCM1_BGR_REG 0x0000121c

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK 0x00000001

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK 0b0

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0

◆ I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS

#define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS 0b1

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT

#define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT 0b0

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK

#define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK 0x00010000

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT

#define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT 0b1

◆ I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET

#define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16

◆ I2SPCM1_CLK_REG

#define I2SPCM1_CLK_REG 0x00001210

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

◆ I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ I2SPCM1_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0

◆ I2SPCM1_CLK_REG_SCLK_GATING_CLEAR_MASK

#define I2SPCM1_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

◆ I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

◆ I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define I2SPCM1_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

◆ I2SPCM1_CLK_REG_SCLK_GATING_OFFSET

#define I2SPCM1_CLK_REG_SCLK_GATING_OFFSET 31

◆ I2SPCM2_BGR_REG

#define I2SPCM2_BGR_REG 0x0000122c

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK 0x00000001

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK 0b0

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0

◆ I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS

#define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS 0b1

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT

#define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT 0b0

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK

#define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK 0x00010000

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT

#define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT 0b1

◆ I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET

#define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16

◆ I2SPCM2_CLK_REG

#define I2SPCM2_CLK_REG 0x00001220

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

◆ I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ I2SPCM2_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0

◆ I2SPCM2_CLK_REG_SCLK_GATING_CLEAR_MASK

#define I2SPCM2_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

◆ I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

◆ I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define I2SPCM2_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

◆ I2SPCM2_CLK_REG_SCLK_GATING_OFFSET

#define I2SPCM2_CLK_REG_SCLK_GATING_OFFSET 31

◆ I2SPCM3_BGR_REG

#define I2SPCM3_BGR_REG 0x0000123c

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK 0x00000001

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK 0b0

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0

◆ I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS

#define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS 0b1

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT

#define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT 0b0

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK

#define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK 0x00010000

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT

#define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT 0b1

◆ I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET

#define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16

◆ I2SPCM3_CLK_REG

#define I2SPCM3_CLK_REG 0x00001230

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b000

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b001

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b010

◆ I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ I2SPCM3_CLK_REG_FACTOR_M_OFFSET

#define I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0

◆ I2SPCM3_CLK_REG_SCLK_GATING_CLEAR_MASK

#define I2SPCM3_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000

◆ I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0b0

◆ I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define I2SPCM3_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0b1

◆ I2SPCM3_CLK_REG_SCLK_GATING_OFFSET

#define I2SPCM3_CLK_REG_SCLK_GATING_OFFSET 31

◆ IOMMU_BGR_REG

#define IOMMU_BGR_REG 0x0000058c

◆ IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK

#define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK 0x00000001

◆ IOMMU_BGR_REG_IOMMU_GATING_MASK

#define IOMMU_BGR_REG_IOMMU_GATING_MASK 0b0

◆ IOMMU_BGR_REG_IOMMU_GATING_OFFSET

#define IOMMU_BGR_REG_IOMMU_GATING_OFFSET 0

◆ IOMMU_BGR_REG_IOMMU_GATING_PASS

#define IOMMU_BGR_REG_IOMMU_GATING_PASS 0b1

◆ IRRX0_BGR_REG

#define IRRX0_BGR_REG 0x00001004

◆ IRRX0_BGR_REG_IRRX0_GATING_CLEAR_MASK

#define IRRX0_BGR_REG_IRRX0_GATING_CLEAR_MASK 0x00000001

◆ IRRX0_BGR_REG_IRRX0_GATING_MASK

#define IRRX0_BGR_REG_IRRX0_GATING_MASK 0b0

◆ IRRX0_BGR_REG_IRRX0_GATING_OFFSET

#define IRRX0_BGR_REG_IRRX0_GATING_OFFSET 0

◆ IRRX0_BGR_REG_IRRX0_GATING_PASS

#define IRRX0_BGR_REG_IRRX0_GATING_PASS 0b1

◆ IRRX0_BGR_REG_IRRX0_RST_ASSERT

#define IRRX0_BGR_REG_IRRX0_RST_ASSERT 0b0

◆ IRRX0_BGR_REG_IRRX0_RST_CLEAR_MASK

#define IRRX0_BGR_REG_IRRX0_RST_CLEAR_MASK 0x00010000

◆ IRRX0_BGR_REG_IRRX0_RST_DE_ASSERT

#define IRRX0_BGR_REG_IRRX0_RST_DE_ASSERT 0b1

◆ IRRX0_BGR_REG_IRRX0_RST_OFFSET

#define IRRX0_BGR_REG_IRRX0_RST_OFFSET 16

◆ IRRX0_CLK_REG

#define IRRX0_CLK_REG 0x00001000

◆ IRRX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ IRRX0_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX0_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

◆ IRRX0_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX0_CLK_REG_CLK_SRC_SEL_HOSC 0b1

◆ IRRX0_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ IRRX0_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ IRRX0_CLK_REG_FACTOR_M_OFFSET

#define IRRX0_CLK_REG_FACTOR_M_OFFSET 0

◆ IRRX0_CLK_REG_IRRX0_CLK_GATING_CLEAR_MASK

#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLEAR_MASK 0x80000000

◆ IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_OFF

#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_ON

#define IRRX0_CLK_REG_IRRX0_CLK_GATING_CLOCK_IS_ON 0b1

◆ IRRX0_CLK_REG_IRRX0_CLK_GATING_OFFSET

#define IRRX0_CLK_REG_IRRX0_CLK_GATING_OFFSET 31

◆ IRRX1_BGR_REG

#define IRRX1_BGR_REG 0x00001104

◆ IRRX1_BGR_REG_IRRX1_GATING_CLEAR_MASK

#define IRRX1_BGR_REG_IRRX1_GATING_CLEAR_MASK 0x00000001

◆ IRRX1_BGR_REG_IRRX1_GATING_MASK

#define IRRX1_BGR_REG_IRRX1_GATING_MASK 0b0

◆ IRRX1_BGR_REG_IRRX1_GATING_OFFSET

#define IRRX1_BGR_REG_IRRX1_GATING_OFFSET 0

◆ IRRX1_BGR_REG_IRRX1_GATING_PASS

#define IRRX1_BGR_REG_IRRX1_GATING_PASS 0b1

◆ IRRX1_BGR_REG_IRRX1_RST_ASSERT

#define IRRX1_BGR_REG_IRRX1_RST_ASSERT 0b0

◆ IRRX1_BGR_REG_IRRX1_RST_CLEAR_MASK

#define IRRX1_BGR_REG_IRRX1_RST_CLEAR_MASK 0x00010000

◆ IRRX1_BGR_REG_IRRX1_RST_DE_ASSERT

#define IRRX1_BGR_REG_IRRX1_RST_DE_ASSERT 0b1

◆ IRRX1_BGR_REG_IRRX1_RST_OFFSET

#define IRRX1_BGR_REG_IRRX1_RST_OFFSET 16

◆ IRRX1_CLK_REG

#define IRRX1_CLK_REG 0x00001100

◆ IRRX1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ IRRX1_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX1_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

◆ IRRX1_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX1_CLK_REG_CLK_SRC_SEL_HOSC 0b1

◆ IRRX1_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ IRRX1_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ IRRX1_CLK_REG_FACTOR_M_OFFSET

#define IRRX1_CLK_REG_FACTOR_M_OFFSET 0

◆ IRRX1_CLK_REG_IRRX1_CLK_GATING_CLEAR_MASK

#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLEAR_MASK 0x80000000

◆ IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_OFF

#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_ON

#define IRRX1_CLK_REG_IRRX1_CLK_GATING_CLOCK_IS_ON 0b1

◆ IRRX1_CLK_REG_IRRX1_CLK_GATING_OFFSET

#define IRRX1_CLK_REG_IRRX1_CLK_GATING_OFFSET 31

◆ IRRX2_BGR_REG

#define IRRX2_BGR_REG 0x0000110c

◆ IRRX2_BGR_REG_IRRX2_GATING_CLEAR_MASK

#define IRRX2_BGR_REG_IRRX2_GATING_CLEAR_MASK 0x00000001

◆ IRRX2_BGR_REG_IRRX2_GATING_MASK

#define IRRX2_BGR_REG_IRRX2_GATING_MASK 0b0

◆ IRRX2_BGR_REG_IRRX2_GATING_OFFSET

#define IRRX2_BGR_REG_IRRX2_GATING_OFFSET 0

◆ IRRX2_BGR_REG_IRRX2_GATING_PASS

#define IRRX2_BGR_REG_IRRX2_GATING_PASS 0b1

◆ IRRX2_BGR_REG_IRRX2_RST_ASSERT

#define IRRX2_BGR_REG_IRRX2_RST_ASSERT 0b0

◆ IRRX2_BGR_REG_IRRX2_RST_CLEAR_MASK

#define IRRX2_BGR_REG_IRRX2_RST_CLEAR_MASK 0x00010000

◆ IRRX2_BGR_REG_IRRX2_RST_DE_ASSERT

#define IRRX2_BGR_REG_IRRX2_RST_DE_ASSERT 0b1

◆ IRRX2_BGR_REG_IRRX2_RST_OFFSET

#define IRRX2_BGR_REG_IRRX2_RST_OFFSET 16

◆ IRRX2_CLK_REG

#define IRRX2_CLK_REG 0x00001108

◆ IRRX2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ IRRX2_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX2_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

◆ IRRX2_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX2_CLK_REG_CLK_SRC_SEL_HOSC 0b1

◆ IRRX2_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ IRRX2_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ IRRX2_CLK_REG_FACTOR_M_OFFSET

#define IRRX2_CLK_REG_FACTOR_M_OFFSET 0

◆ IRRX2_CLK_REG_IRRX2_CLK_GATING_CLEAR_MASK

#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLEAR_MASK 0x80000000

◆ IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_OFF

#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_OFF 0b0

◆ IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_ON

#define IRRX2_CLK_REG_IRRX2_CLK_GATING_CLOCK_IS_ON 0b1

◆ IRRX2_CLK_REG_IRRX2_CLK_GATING_OFFSET

#define IRRX2_CLK_REG_IRRX2_CLK_GATING_OFFSET 31

◆ IRRX3_BGR_REG

#define IRRX3_BGR_REG 0x00001114

◆ IRRX3_BGR_REG_IRRX3_GATING_CLEAR_MASK

#define IRRX3_BGR_REG_IRRX3_GATING_CLEAR_MASK 0x00000001

◆ IRRX3_BGR_REG_IRRX3_GATING_MASK

#define IRRX3_BGR_REG_IRRX3_GATING_MASK 0b0

◆ IRRX3_BGR_REG_IRRX3_GATING_OFFSET

#define IRRX3_BGR_REG_IRRX3_GATING_OFFSET 0

◆ IRRX3_BGR_REG_IRRX3_GATING_PASS

#define IRRX3_BGR_REG_IRRX3_GATING_PASS 0b1

◆ IRRX3_BGR_REG_IRRX3_RST_ASSERT

#define IRRX3_BGR_REG_IRRX3_RST_ASSERT 0b0

◆ IRRX3_BGR_REG_IRRX3_RST_CLEAR_MASK

#define IRRX3_BGR_REG_IRRX3_RST_CLEAR_MASK 0x00010000

◆ IRRX3_BGR_REG_IRRX3_RST_DE_ASSERT

#define IRRX3_BGR_REG_IRRX3_RST_DE_ASSERT 0b1

◆ IRRX3_BGR_REG_IRRX3_RST_OFFSET

#define IRRX3_BGR_REG_IRRX3_RST_OFFSET 16

◆ IRRX3_CLK_REG

#define IRRX3_CLK_REG 0x00001110

◆ IRRX3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ IRRX3_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX3_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

◆ IRRX3_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX3_CLK_REG_CLK_SRC_SEL_HOSC 0b1

◆ IRRX3_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ IRRX3_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ IRRX3_CLK_REG_FACTOR_M_OFFSET

#define IRRX3_CLK_REG_FACTOR_M_OFFSET 0

◆ IRRX3_CLK_REG_IRRX3_CLK_GATING_CLEAR_MASK

#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLEAR_MASK 0x80000000

◆ IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_OFF

#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_OFF 0b0

◆ IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_ON

#define IRRX3_CLK_REG_IRRX3_CLK_GATING_CLOCK_IS_ON 0b1

◆ IRRX3_CLK_REG_IRRX3_CLK_GATING_OFFSET

#define IRRX3_CLK_REG_IRRX3_CLK_GATING_OFFSET 31

◆ IRTX_BGR_REG

#define IRTX_BGR_REG 0x0000100c

◆ IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK 0x00000001

◆ IRTX_BGR_REG_IRTX_GATING_MASK

#define IRTX_BGR_REG_IRTX_GATING_MASK 0b0

◆ IRTX_BGR_REG_IRTX_GATING_OFFSET

#define IRTX_BGR_REG_IRTX_GATING_OFFSET 0

◆ IRTX_BGR_REG_IRTX_GATING_PASS

#define IRTX_BGR_REG_IRTX_GATING_PASS 0b1

◆ IRTX_BGR_REG_IRTX_RST_ASSERT

#define IRTX_BGR_REG_IRTX_RST_ASSERT 0b0

◆ IRTX_BGR_REG_IRTX_RST_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK 0x00010000

◆ IRTX_BGR_REG_IRTX_RST_DE_ASSERT

#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0b1

◆ IRTX_BGR_REG_IRTX_RST_OFFSET

#define IRTX_BGR_REG_IRTX_RST_OFFSET 16

◆ IRTX_CLK_REG

#define IRTX_CLK_REG 0x00001008

◆ IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ IRTX_CLK_REG_CLK_SRC_SEL_HOSC

#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ IRTX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b1

◆ IRTX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ IRTX_CLK_REG_FACTOR_M_OFFSET

#define IRTX_CLK_REG_FACTOR_M_OFFSET 0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK 0x80000000

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0b0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0b1

◆ IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET

#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31

◆ ISP_BGR_REG

#define ISP_BGR_REG 0x00001864

◆ ISP_BGR_REG_ISP_GATING_CLEAR_MASK

#define ISP_BGR_REG_ISP_GATING_CLEAR_MASK 0x00000001

◆ ISP_BGR_REG_ISP_GATING_MASK

#define ISP_BGR_REG_ISP_GATING_MASK 0b0

◆ ISP_BGR_REG_ISP_GATING_OFFSET

#define ISP_BGR_REG_ISP_GATING_OFFSET 0

◆ ISP_BGR_REG_ISP_GATING_PASS

#define ISP_BGR_REG_ISP_GATING_PASS 0b1

◆ ISP_BGR_REG_ISP_RST_ASSERT

#define ISP_BGR_REG_ISP_RST_ASSERT 0b0

◆ ISP_BGR_REG_ISP_RST_CLEAR_MASK

#define ISP_BGR_REG_ISP_RST_CLEAR_MASK 0x00010000

◆ ISP_BGR_REG_ISP_RST_DE_ASSERT

#define ISP_BGR_REG_ISP_RST_DE_ASSERT 0b1

◆ ISP_BGR_REG_ISP_RST_OFFSET

#define ISP_BGR_REG_ISP_RST_OFFSET 16

◆ ISP_CLK_REG

#define ISP_CLK_REG 0x00001860

◆ ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ ISP_CLK_REG_CLK_SRC_SEL_NPUPLL

#define ISP_CLK_REG_CLK_SRC_SEL_NPUPLL 0b111

◆ ISP_CLK_REG_CLK_SRC_SEL_OFFSET

#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b000

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ ISP_CLK_REG_CLK_SRC_SEL_VEPLL

#define ISP_CLK_REG_CLK_SRC_SEL_VEPLL 0b110

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b010

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b101

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b100

◆ ISP_CLK_REG_FACTOR_M_CLEAR_MASK

#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ ISP_CLK_REG_FACTOR_M_OFFSET

#define ISP_CLK_REG_FACTOR_M_OFFSET 0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK

#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0b0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0b1

◆ ISP_CLK_REG_ISP_CLK_GATING_OFFSET

#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31

◆ ITS0_BGR_REG

#define ITS0_BGR_REG 0x00000574

◆ ITS0_BGR_REG_ITS0_ACLK_GATING_CLEAR_MASK

#define ITS0_BGR_REG_ITS0_ACLK_GATING_CLEAR_MASK 0x00000002

◆ ITS0_BGR_REG_ITS0_ACLK_GATING_MASK

#define ITS0_BGR_REG_ITS0_ACLK_GATING_MASK 0b0

◆ ITS0_BGR_REG_ITS0_ACLK_GATING_OFFSET

#define ITS0_BGR_REG_ITS0_ACLK_GATING_OFFSET 1

◆ ITS0_BGR_REG_ITS0_ACLK_GATING_PASS

#define ITS0_BGR_REG_ITS0_ACLK_GATING_PASS 0b1

◆ ITS0_BGR_REG_ITS0_HCLK_GATING_CLEAR_MASK

#define ITS0_BGR_REG_ITS0_HCLK_GATING_CLEAR_MASK 0x00000001

◆ ITS0_BGR_REG_ITS0_HCLK_GATING_MASK

#define ITS0_BGR_REG_ITS0_HCLK_GATING_MASK 0b0

◆ ITS0_BGR_REG_ITS0_HCLK_GATING_OFFSET

#define ITS0_BGR_REG_ITS0_HCLK_GATING_OFFSET 0

◆ ITS0_BGR_REG_ITS0_HCLK_GATING_PASS

#define ITS0_BGR_REG_ITS0_HCLK_GATING_PASS 0b1

◆ ITS0_BGR_REG_ITS0_RST_ASSERT

#define ITS0_BGR_REG_ITS0_RST_ASSERT 0b0

◆ ITS0_BGR_REG_ITS0_RST_CLEAR_MASK

#define ITS0_BGR_REG_ITS0_RST_CLEAR_MASK 0x00010000

◆ ITS0_BGR_REG_ITS0_RST_DE_ASSERT

#define ITS0_BGR_REG_ITS0_RST_DE_ASSERT 0b1

◆ ITS0_BGR_REG_ITS0_RST_OFFSET

#define ITS0_BGR_REG_ITS0_RST_OFFSET 16

◆ LBC_BGR_REG

#define LBC_BGR_REG 0x0000104c

◆ LBC_BGR_REG_LBC_GATING_CLEAR_MASK

#define LBC_BGR_REG_LBC_GATING_CLEAR_MASK 0x00000001

◆ LBC_BGR_REG_LBC_GATING_MASK

#define LBC_BGR_REG_LBC_GATING_MASK 0b0

◆ LBC_BGR_REG_LBC_GATING_OFFSET

#define LBC_BGR_REG_LBC_GATING_OFFSET 0

◆ LBC_BGR_REG_LBC_GATING_PASS

#define LBC_BGR_REG_LBC_GATING_PASS 0b1

◆ LBC_BGR_REG_LBC_RST_ASSERT

#define LBC_BGR_REG_LBC_RST_ASSERT 0b0

◆ LBC_BGR_REG_LBC_RST_CLEAR_MASK

#define LBC_BGR_REG_LBC_RST_CLEAR_MASK 0x00010000

◆ LBC_BGR_REG_LBC_RST_DE_ASSERT

#define LBC_BGR_REG_LBC_RST_DE_ASSERT 0b1

◆ LBC_BGR_REG_LBC_RST_OFFSET

#define LBC_BGR_REG_LBC_RST_OFFSET 16

◆ LBC_CLK_REG

#define LBC_CLK_REG 0x00001040

◆ LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ LBC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LBC_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ LBC_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ LBC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define LBC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b000

◆ LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b011

◆ LBC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define LBC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b100

◆ LBC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LBC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ LBC_CLK_REG_FACTOR_M_OFFSET

#define LBC_CLK_REG_FACTOR_M_OFFSET 0

◆ LBC_CLK_REG_FACTOR_N_CLEAR_MASK

#define LBC_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ LBC_CLK_REG_FACTOR_N_OFFSET

#define LBC_CLK_REG_FACTOR_N_OFFSET 8

◆ LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK

#define LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK 0x80000000

◆ LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF

#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF 0b0

◆ LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON

#define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON 0b1

◆ LBC_CLK_REG_LBC_CLK_GATING_OFFSET

#define LBC_CLK_REG_LBC_CLK_GATING_OFFSET 31

◆ LBC_NSI_AHB_CLK_REG

#define LBC_NSI_AHB_CLK_REG 0x00001048

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_HOSC

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b10

◆ LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define LBC_NSI_AHB_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b01

◆ LBC_NSI_AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define LBC_NSI_AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ LBC_NSI_AHB_CLK_REG_FACTOR_M_OFFSET

#define LBC_NSI_AHB_CLK_REG_FACTOR_M_OFFSET 0

◆ LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLEAR_MASK

#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLEAR_MASK 0x80000000

◆ LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_OFF

#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_OFF 0b0

◆ LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_ON

#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_CLOCK_IS_ON 0b1

◆ LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_OFFSET

#define LBC_NSI_AHB_CLK_REG_LBC_NSI_AHB_CLK_GATING_OFFSET 31

◆ LEDC_BGR_REG

#define LEDC_BGR_REG 0x00001704

◆ LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK 0x00000001

◆ LEDC_BGR_REG_LEDC_GATING_MASK

#define LEDC_BGR_REG_LEDC_GATING_MASK 0b0

◆ LEDC_BGR_REG_LEDC_GATING_OFFSET

#define LEDC_BGR_REG_LEDC_GATING_OFFSET 0

◆ LEDC_BGR_REG_LEDC_GATING_PASS

#define LEDC_BGR_REG_LEDC_GATING_PASS 0b1

◆ LEDC_BGR_REG_LEDC_RST_ASSERT

#define LEDC_BGR_REG_LEDC_RST_ASSERT 0b0

◆ LEDC_BGR_REG_LEDC_RST_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK 0x00010000

◆ LEDC_BGR_REG_LEDC_RST_DE_ASSERT

#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0b1

◆ LEDC_BGR_REG_LEDC_RST_OFFSET

#define LEDC_BGR_REG_LEDC_RST_OFFSET 16

◆ LEDC_CLK_REG

#define LEDC_CLK_REG 0x00001700

◆ LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ LEDC_CLK_REG_CLK_SRC_SEL_HOSC

#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ LEDC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1

◆ LEDC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ LEDC_CLK_REG_FACTOR_M_OFFSET

#define LEDC_CLK_REG_FACTOR_M_OFFSET 0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0b0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0b1

◆ LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET

#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31

◆ LRADC_BGR_REG

#define LRADC_BGR_REG 0x00001024

◆ LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK 0x00000001

◆ LRADC_BGR_REG_LRADC_GATING_MASK

#define LRADC_BGR_REG_LRADC_GATING_MASK 0b0

◆ LRADC_BGR_REG_LRADC_GATING_OFFSET

#define LRADC_BGR_REG_LRADC_GATING_OFFSET 0

◆ LRADC_BGR_REG_LRADC_GATING_PASS

#define LRADC_BGR_REG_LRADC_GATING_PASS 0b1

◆ LRADC_BGR_REG_LRADC_RST_ASSERT

#define LRADC_BGR_REG_LRADC_RST_ASSERT 0b0

◆ LRADC_BGR_REG_LRADC_RST_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK 0x00010000

◆ LRADC_BGR_REG_LRADC_RST_DE_ASSERT

#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0b1

◆ LRADC_BGR_REG_LRADC_RST_OFFSET

#define LRADC_BGR_REG_LRADC_RST_OFFSET 16

◆ LVDS0_BGR_REG

#define LVDS0_BGR_REG 0x00001544

◆ LVDS0_BGR_REG_LVDS0_RST_ASSERT

#define LVDS0_BGR_REG_LVDS0_RST_ASSERT 0b0

◆ LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK

#define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK 0x00010000

◆ LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT

#define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT 0b1

◆ LVDS0_BGR_REG_LVDS0_RST_OFFSET

#define LVDS0_BGR_REG_LVDS0_RST_OFFSET 16

◆ MBUS_CLK_REG

#define MBUS_CLK_REG 0x00000588

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK 0x80000000

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF 0b0

◆ MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON

#define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON 0b1

◆ MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31

◆ MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK 0x07000000

◆ MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL

#define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL 0b100

◆ MBUS_CLK_REG_MBUS_CLK_SEL_HOSC

#define MBUS_CLK_REG_MBUS_CLK_SEL_HOSC 0b000

◆ MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL

#define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL 0b101

◆ MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET

#define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M 0b011

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M 0b010

◆ MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS

#define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M_BUS 0b001

◆ MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK 0x10000000

◆ MBUS_CLK_REG_MBUS_DFS_EN_DISABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE 0b0

◆ MBUS_CLK_REG_MBUS_DFS_EN_ENABLE

#define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE 0b1

◆ MBUS_CLK_REG_MBUS_DFS_EN_OFFSET

#define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28

◆ MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK 0x0000001f

◆ MBUS_CLK_REG_MBUS_DIV1_OFFSET

#define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0

◆ MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK 0x08000000

◆ MBUS_CLK_REG_MBUS_UPD_INVALID

#define MBUS_CLK_REG_MBUS_UPD_INVALID 0b0

◆ MBUS_CLK_REG_MBUS_UPD_OFFSET

#define MBUS_CLK_REG_MBUS_UPD_OFFSET 27

◆ MBUS_CLK_REG_MBUS_UPD_VALID

#define MBUS_CLK_REG_MBUS_UPD_VALID 0b1

◆ MBUS_GATE_EN_REG

#define MBUS_GATE_EN_REG 0x000005e0

◆ MBUS_GATE_EN_REG_CAN_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_CAN_MCLK_EN_CLEAR_MASK 0x00020000

◆ MBUS_GATE_EN_REG_CAN_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_CAN_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_CAN_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_CAN_MCLK_EN_OFFSET 17

◆ MBUS_GATE_EN_REG_CAN_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_CAN_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_CE_MCLK_EN_CLEAR_MASK 0x00000004

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_CE_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_CE_MCLK_EN_OFFSET 2

◆ MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG

#define MBUS_GATE_EN_REG_CE_MCLK_EN_SECURE_DEBUG 0b1

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_CLEAR_MASK 0x00000100

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_OFFSET 8

◆ MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_CSI_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_CLEAR_MASK 0x00000001

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_OFFSET 0

◆ MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_DMA0_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_CLEAR_MASK 0x00000008

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_OFFSET 3

◆ MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_DMA1_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_CLEAR_MASK 0x00000800

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_OFFSET 11

◆ MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_GMAC0_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_CLEAR_MASK 0x00001000

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_OFFSET 12

◆ MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_GMAC1_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_CLEAR_MASK 0x00000200

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_OFFSET 9

◆ MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_ISP_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_NAND0_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_CLEAR_MASK 0x00000020

◆ MBUS_GATE_EN_REG_NAND0_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_NAND0_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_OFFSET 5

◆ MBUS_GATE_EN_REG_NAND0_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_NAND0_MCLK_EN_PASS 0b1

◆ MBUS_GATE_EN_REG_VE_MCLK_EN_CLEAR_MASK

#define MBUS_GATE_EN_REG_VE_MCLK_EN_CLEAR_MASK 0x00000002

◆ MBUS_GATE_EN_REG_VE_MCLK_EN_MASK

#define MBUS_GATE_EN_REG_VE_MCLK_EN_MASK 0b0

◆ MBUS_GATE_EN_REG_VE_MCLK_EN_OFFSET

#define MBUS_GATE_EN_REG_VE_MCLK_EN_OFFSET 1

◆ MBUS_GATE_EN_REG_VE_MCLK_EN_PASS

#define MBUS_GATE_EN_REG_VE_MCLK_EN_PASS 0b1

◆ MBUS_MAT_CLK_GATING_REG

#define MBUS_MAT_CLK_GATING_REG 0x000005e4

◆ MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00080000

◆ MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CAN_MBUS_GATE_SW_CFG_OFFSET 19

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00040000

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET 18

◆ MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_CLEAR_MASK 0x04000000

◆ MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_GMAC0_MBUS_GATE_SW_CFG_OFFSET 26

◆ MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_CLEAR_MASK 0x08000000

◆ MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_GMAC1_MBUS_GATE_SW_CFG_OFFSET 27

◆ MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00200000

◆ MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_MCU_SYS_MBUS_GATE_SW_CFG_OFFSET 21

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00400000

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 22

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK 0x01000000

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 24

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00020000

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET 17

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 20

◆ MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00800000

◆ MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_DISABLE 0b0

◆ MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_ENABLE 0b1

◆ MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VO_SYS_MBUS_GATE_SW_CFG_OFFSET 23

◆ MSGBOX0_BGR_REG

#define MSGBOX0_BGR_REG 0x00000744

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK 0b0

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0

◆ MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS

#define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS 0b1

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT

#define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT 0b0

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK

#define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK 0x00010000

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT

#define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT 0b1

◆ MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET

#define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16

◆ MSGBOX_CORE0_BGR_REG

#define MSGBOX_CORE0_BGR_REG 0x0000074c

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_CLEAR_MASK

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_MASK

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_MASK 0b0

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_OFFSET

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_OFFSET 0

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_PASS

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_GATING_PASS 0b1

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_ASSERT

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_ASSERT 0b0

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_CLEAR_MASK

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_CLEAR_MASK 0x00010000

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_DE_ASSERT

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_DE_ASSERT 0b1

◆ MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_OFFSET

#define MSGBOX_CORE0_BGR_REG_MSGBOX_CORE0_RST_OFFSET 16

◆ MSGBOX_CORE1_BGR_REG

#define MSGBOX_CORE1_BGR_REG 0x00000754

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_CLEAR_MASK

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_MASK

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_MASK 0b0

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_OFFSET

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_OFFSET 0

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_PASS

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_GATING_PASS 0b1

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_ASSERT

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_ASSERT 0b0

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_CLEAR_MASK

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_CLEAR_MASK 0x00010000

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_DE_ASSERT

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_DE_ASSERT 0b1

◆ MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_OFFSET

#define MSGBOX_CORE1_BGR_REG_MSGBOX_CORE1_RST_OFFSET 16

◆ MSGBOX_CORE2_BGR_REG

#define MSGBOX_CORE2_BGR_REG 0x0000075c

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_CLEAR_MASK

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_MASK

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_MASK 0b0

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_OFFSET

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_OFFSET 0

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_PASS

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_GATING_PASS 0b1

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_ASSERT

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_ASSERT 0b0

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_CLEAR_MASK

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_CLEAR_MASK 0x00010000

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_DE_ASSERT

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_DE_ASSERT 0b1

◆ MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_OFFSET

#define MSGBOX_CORE2_BGR_REG_MSGBOX_CORE2_RST_OFFSET 16

◆ MSGBOX_CORE3_BGR_REG

#define MSGBOX_CORE3_BGR_REG 0x00000764

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_CLEAR_MASK

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_MASK

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_MASK 0b0

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_OFFSET

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_OFFSET 0

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_PASS

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_GATING_PASS 0b1

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_ASSERT

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_ASSERT 0b0

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_CLEAR_MASK

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_CLEAR_MASK 0x00010000

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_DE_ASSERT

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_DE_ASSERT 0b1

◆ MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_OFFSET

#define MSGBOX_CORE3_BGR_REG_MSGBOX_CORE3_RST_OFFSET 16

◆ MSGBOX_RV_BGR_REG

#define MSGBOX_RV_BGR_REG 0x0000076c

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_CLEAR_MASK

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_CLEAR_MASK 0x00000001

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_MASK

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_MASK 0b0

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_OFFSET

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_OFFSET 0

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_PASS

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_GATING_PASS 0b1

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_ASSERT

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_ASSERT 0b0

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_CLEAR_MASK

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_CLEAR_MASK 0x00010000

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_DE_ASSERT

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_DE_ASSERT 0b1

◆ MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_OFFSET

#define MSGBOX_RV_BGR_REG_MSGBOX_RV_RST_OFFSET 16

◆ NAND0_BGR_REG

#define NAND0_BGR_REG 0x00000c8c

◆ NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK

#define NAND0_BGR_REG_NAND0_GATING_CLEAR_MASK 0x00000001

◆ NAND0_BGR_REG_NAND0_GATING_MASK

#define NAND0_BGR_REG_NAND0_GATING_MASK 0b0

◆ NAND0_BGR_REG_NAND0_GATING_OFFSET

#define NAND0_BGR_REG_NAND0_GATING_OFFSET 0

◆ NAND0_BGR_REG_NAND0_GATING_PASS

#define NAND0_BGR_REG_NAND0_GATING_PASS 0b1

◆ NAND0_BGR_REG_NAND0_RST_ASSERT

#define NAND0_BGR_REG_NAND0_RST_ASSERT 0b0

◆ NAND0_BGR_REG_NAND0_RST_CLEAR_MASK

#define NAND0_BGR_REG_NAND0_RST_CLEAR_MASK 0x00010000

◆ NAND0_BGR_REG_NAND0_RST_DE_ASSERT

#define NAND0_BGR_REG_NAND0_RST_DE_ASSERT 0b1

◆ NAND0_BGR_REG_NAND0_RST_OFFSET

#define NAND0_BGR_REG_NAND0_RST_OFFSET 16

◆ NAND0_CLK1_CLK_REG

#define NAND0_CLK1_CLK_REG 0x00000c84

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

◆ NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK 0x80000000

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0b1

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31

◆ NAND0_CLK2X_CLK_REG

#define NAND0_CLK2X_CLK_REG 0x00000c80

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_HOSC

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

◆ NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK2X_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

◆ NAND0_CLK2X_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK2X_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ NAND0_CLK2X_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK2X_CLK_REG_FACTOR_M_OFFSET 0

◆ NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLEAR_MASK

#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLEAR_MASK 0x80000000

◆ NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_OFF 0b0

◆ NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_CLOCK_IS_ON 0b1

◆ NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_OFFSET

#define NAND0_CLK2X_CLK_REG_NAND0_CLK2X_CLK_GATING_OFFSET 31

◆ NPU_BGR_REG

#define NPU_BGR_REG 0x00000b04

◆ NPU_BGR_REG_NPU_AHB_RST_ASSERT

#define NPU_BGR_REG_NPU_AHB_RST_ASSERT 0b0

◆ NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK 0x00040000

◆ NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT 0b1

◆ NPU_BGR_REG_NPU_AHB_RST_OFFSET

#define NPU_BGR_REG_NPU_AHB_RST_OFFSET 18

◆ NPU_BGR_REG_NPU_AXI_RST_ASSERT

#define NPU_BGR_REG_NPU_AXI_RST_ASSERT 0b0

◆ NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK 0x00020000

◆ NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT 0b1

◆ NPU_BGR_REG_NPU_AXI_RST_OFFSET

#define NPU_BGR_REG_NPU_AXI_RST_OFFSET 17

◆ NPU_BGR_REG_NPU_CORE_RST_ASSERT

#define NPU_BGR_REG_NPU_CORE_RST_ASSERT 0b0

◆ NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK 0x00010000

◆ NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT 0b1

◆ NPU_BGR_REG_NPU_CORE_RST_OFFSET

#define NPU_BGR_REG_NPU_CORE_RST_OFFSET 16

◆ NPU_BGR_REG_NPU_GATING_CLEAR_MASK

#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK 0x00000001

◆ NPU_BGR_REG_NPU_GATING_MASK

#define NPU_BGR_REG_NPU_GATING_MASK 0b0

◆ NPU_BGR_REG_NPU_GATING_OFFSET

#define NPU_BGR_REG_NPU_GATING_OFFSET 0

◆ NPU_BGR_REG_NPU_GATING_PASS

#define NPU_BGR_REG_NPU_GATING_PASS 0b1

◆ NPU_BGR_REG_NPU_GLB_RST_ASSERT

#define NPU_BGR_REG_NPU_GLB_RST_ASSERT 0b0

◆ NPU_BGR_REG_NPU_GLB_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_GLB_RST_CLEAR_MASK 0x00080000

◆ NPU_BGR_REG_NPU_GLB_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_GLB_RST_DE_ASSERT 0b1

◆ NPU_BGR_REG_NPU_GLB_RST_OFFSET

#define NPU_BGR_REG_NPU_GLB_RST_OFFSET 19

◆ NPU_BGR_REG_NPU_TZMA_GATING_CLEAR_MASK

#define NPU_BGR_REG_NPU_TZMA_GATING_CLEAR_MASK 0x00000002

◆ NPU_BGR_REG_NPU_TZMA_GATING_MASK

#define NPU_BGR_REG_NPU_TZMA_GATING_MASK 0b0

◆ NPU_BGR_REG_NPU_TZMA_GATING_OFFSET

#define NPU_BGR_REG_NPU_TZMA_GATING_OFFSET 1

◆ NPU_BGR_REG_NPU_TZMA_GATING_PASS

#define NPU_BGR_REG_NPU_TZMA_GATING_PASS 0b1

◆ NPU_CLK_REG

#define NPU_CLK_REG 0x00000b00

◆ NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ NPU_CLK_REG_CLK_SRC_SEL_NPUPLL

#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL 0b000

◆ NPU_CLK_REG_CLK_SRC_SEL_OFFSET

#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b011

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b010

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b001

◆ NPU_CLK_REG_FACTOR_M_CLEAR_MASK

#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ NPU_CLK_REG_FACTOR_M_OFFSET

#define NPU_CLK_REG_FACTOR_M_OFFSET 0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK

#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK 0x80000000

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0b0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0b1

◆ NPU_CLK_REG_NPU_CLK_GATING_OFFSET

#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31

◆ NSI_BGR_REG

#define NSI_BGR_REG 0x00000584

◆ NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK

#define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK 0x00000001

◆ NSI_BGR_REG_NSI_CFG_GATING_MASK

#define NSI_BGR_REG_NSI_CFG_GATING_MASK 0b0

◆ NSI_BGR_REG_NSI_CFG_GATING_OFFSET

#define NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0

◆ NSI_BGR_REG_NSI_CFG_GATING_PASS

#define NSI_BGR_REG_NSI_CFG_GATING_PASS 0b1

◆ NSI_BGR_REG_NSI_CFG_RST_ASSERT

#define NSI_BGR_REG_NSI_CFG_RST_ASSERT 0b0

◆ NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK

#define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK 0x00010000

◆ NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT

#define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT 0b1

◆ NSI_BGR_REG_NSI_CFG_RST_OFFSET

#define NSI_BGR_REG_NSI_CFG_RST_OFFSET 16

◆ NSI_CLK_REG

#define NSI_CLK_REG 0x00000580

◆ NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK 0x80000000

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF 0b0

◆ NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON

#define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON 0b1

◆ NSI_CLK_REG_NSI_CLK_GATING_OFFSET

#define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31

◆ NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK

#define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK 0x07000000

◆ NSI_CLK_REG_NSI_CLK_SEL_DDRPLL

#define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL 0b001

◆ NSI_CLK_REG_NSI_CLK_SEL_HOSC

#define NSI_CLK_REG_NSI_CLK_SEL_HOSC 0b000

◆ NSI_CLK_REG_NSI_CLK_SEL_OFFSET

#define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_400M 0b101

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_480M 0b100

◆ NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS

#define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M_BUS 0b011

◆ NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL4X

#define NSI_CLK_REG_NSI_CLK_SEL_VIDEO0PLL4X 0b010

◆ NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK

#define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK 0x10000000

◆ NSI_CLK_REG_NSI_DFS_EN_DISABLE

#define NSI_CLK_REG_NSI_DFS_EN_DISABLE 0b0

◆ NSI_CLK_REG_NSI_DFS_EN_ENABLE

#define NSI_CLK_REG_NSI_DFS_EN_ENABLE 0b1

◆ NSI_CLK_REG_NSI_DFS_EN_OFFSET

#define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28

◆ NSI_CLK_REG_NSI_DIV1_CLEAR_MASK

#define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK 0x0000001f

◆ NSI_CLK_REG_NSI_DIV1_OFFSET

#define NSI_CLK_REG_NSI_DIV1_OFFSET 0

◆ NSI_CLK_REG_NSI_RST_ASSERT

#define NSI_CLK_REG_NSI_RST_ASSERT 0b0

◆ NSI_CLK_REG_NSI_RST_CLEAR_MASK

#define NSI_CLK_REG_NSI_RST_CLEAR_MASK 0x40000000

◆ NSI_CLK_REG_NSI_RST_DE_ASSERT

#define NSI_CLK_REG_NSI_RST_DE_ASSERT 0b1

◆ NSI_CLK_REG_NSI_RST_OFFSET

#define NSI_CLK_REG_NSI_RST_OFFSET 30

◆ NSI_CLK_REG_NSI_UPD_CLEAR_MASK

#define NSI_CLK_REG_NSI_UPD_CLEAR_MASK 0x08000000

◆ NSI_CLK_REG_NSI_UPD_INVALID

#define NSI_CLK_REG_NSI_UPD_INVALID 0b0

◆ NSI_CLK_REG_NSI_UPD_OFFSET

#define NSI_CLK_REG_NSI_UPD_OFFSET 27

◆ NSI_CLK_REG_NSI_UPD_VALID

#define NSI_CLK_REG_NSI_UPD_VALID 0b1

◆ OWA_BGR_REG

#define OWA_BGR_REG 0x0000128c

◆ OWA_BGR_REG_OWA_GATING_CLEAR_MASK

#define OWA_BGR_REG_OWA_GATING_CLEAR_MASK 0x00000001

◆ OWA_BGR_REG_OWA_GATING_MASK

#define OWA_BGR_REG_OWA_GATING_MASK 0b0

◆ OWA_BGR_REG_OWA_GATING_OFFSET

#define OWA_BGR_REG_OWA_GATING_OFFSET 0

◆ OWA_BGR_REG_OWA_GATING_PASS

#define OWA_BGR_REG_OWA_GATING_PASS 0b1

◆ OWA_BGR_REG_OWA_RST_ASSERT

#define OWA_BGR_REG_OWA_RST_ASSERT 0b0

◆ OWA_BGR_REG_OWA_RST_CLEAR_MASK

#define OWA_BGR_REG_OWA_RST_CLEAR_MASK 0x00010000

◆ OWA_BGR_REG_OWA_RST_DE_ASSERT

#define OWA_BGR_REG_OWA_RST_DE_ASSERT 0b1

◆ OWA_BGR_REG_OWA_RST_OFFSET

#define OWA_BGR_REG_OWA_RST_OFFSET 16

◆ OWA_RX_CLK_REG

#define OWA_RX_CLK_REG 0x00001284

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b010

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define OWA_RX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b011

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define OWA_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_OFFSET

#define OWA_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b001

◆ OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define OWA_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b000

◆ OWA_RX_CLK_REG_FACTOR_M_CLEAR_MASK

#define OWA_RX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ OWA_RX_CLK_REG_FACTOR_M_OFFSET

#define OWA_RX_CLK_REG_FACTOR_M_OFFSET 0

◆ OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLEAR_MASK

#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLEAR_MASK 0x80000000

◆ OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_OFF

#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_OFF 0b0

◆ OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_ON

#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_CLOCK_IS_ON 0b1

◆ OWA_RX_CLK_REG_OWA_RX_CLK_GATING_OFFSET

#define OWA_RX_CLK_REG_OWA_RX_CLK_GATING_OFFSET 31

◆ OWA_TX_CLK_REG

#define OWA_TX_CLK_REG 0x00001280

◆ OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b0

◆ OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X

#define OWA_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X 0b1

◆ OWA_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define OWA_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ OWA_TX_CLK_REG_CLK_SRC_SEL_OFFSET

#define OWA_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ OWA_TX_CLK_REG_FACTOR_M_CLEAR_MASK

#define OWA_TX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ OWA_TX_CLK_REG_FACTOR_M_OFFSET

#define OWA_TX_CLK_REG_FACTOR_M_OFFSET 0

◆ OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLEAR_MASK

#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLEAR_MASK 0x80000000

◆ OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_OFF

#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_OFF 0b0

◆ OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_ON

#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_CLOCK_IS_ON 0b1

◆ OWA_TX_CLK_REG_OWA_TX_CLK_GATING_OFFSET

#define OWA_TX_CLK_REG_OWA_TX_CLK_GATING_OFFSET 31

◆ PCIE_AUX_CLK_REG

#define PCIE_AUX_CLK_REG 0x00001380

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0b1

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ PCIE_AUX_CLK_REG_FACTOR_M_OFFSET

#define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET 0

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK 0x80000000

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF 0b0

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON 0b1

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET 31

◆ PCIE_BGR_REG

#define PCIE_BGR_REG 0x0000138c

◆ PCIE_BGR_REG_PCIE_PWRUP_RST_ASSERT

#define PCIE_BGR_REG_PCIE_PWRUP_RST_ASSERT 0b0

◆ PCIE_BGR_REG_PCIE_PWRUP_RST_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_PWRUP_RST_CLEAR_MASK 0x00010000

◆ PCIE_BGR_REG_PCIE_PWRUP_RST_DE_ASSERT

#define PCIE_BGR_REG_PCIE_PWRUP_RST_DE_ASSERT 0b1

◆ PCIE_BGR_REG_PCIE_PWRUP_RST_OFFSET

#define PCIE_BGR_REG_PCIE_PWRUP_RST_OFFSET 16

◆ PCIE_BGR_REG_PCIE_RST_ASSERT

#define PCIE_BGR_REG_PCIE_RST_ASSERT 0b0

◆ PCIE_BGR_REG_PCIE_RST_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK 0x00020000

◆ PCIE_BGR_REG_PCIE_RST_DE_ASSERT

#define PCIE_BGR_REG_PCIE_RST_DE_ASSERT 0b1

◆ PCIE_BGR_REG_PCIE_RST_OFFSET

#define PCIE_BGR_REG_PCIE_RST_OFFSET 17

◆ PCIE_SLV_CLK_REG

#define PCIE_SLV_CLK_REG 0x00001384

◆ PCIE_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ PCIE_SLV_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b1

◆ PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define PCIE_SLV_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b0

◆ PCIE_SLV_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIE_SLV_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ PCIE_SLV_CLK_REG_FACTOR_M_OFFSET

#define PCIE_SLV_CLK_REG_FACTOR_M_OFFSET 0

◆ PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLEAR_MASK

#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLEAR_MASK 0x80000000

◆ PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_OFF

#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_OFF 0b0

◆ PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_ON

#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_CLOCK_IS_ON 0b1

◆ PCIE_SLV_CLK_REG_PCIE_CLK_GATING_OFFSET

#define PCIE_SLV_CLK_REG_PCIE_CLK_GATING_OFFSET 31

◆ PERI0PLL_GATE_EN_REG

#define PERI0PLL_GATE_EN_REG 0x00001908

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_CPUS_GATE_EN_OFFSET 31

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0b0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0b1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27

◆ PERI0PLL_GATE_STAT_REG

#define PERI0PLL_GATE_STAT_REG 0x00001988

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK 0x00000001

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 0

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK 0x00000002

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 1

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK 0x00000004

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 2

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000010

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 4

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK 0x00000008

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 3

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000040

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 6

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK 0x00000020

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 5

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK 0x00000100

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 8

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK 0x00000080

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 7

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK 0x00000200

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 9

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK 0x00000400

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 10

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK 0x00000800

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE 0b0

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE 0b1

◆ PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET

#define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 11

◆ PERI1_FOCPU_EN_REG

#define PERI1_FOCPU_EN_REG 0x00001a10

◆ PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_CLEAR_MASK

#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_CLEAR_MASK 0x00000001

◆ PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_DISABLE

#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_DISABLE 0b0

◆ PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_ENABLE

#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_ENABLE 0b1

◆ PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_OFFSET

#define PERI1_FOCPU_EN_REG_PERI1PLL_FOCPU_EN_OFFSET 0

◆ PERI1PLL_GATE_EN_REG

#define PERI1PLL_GATE_EN_REG 0x0000190c

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_CLEAR_MASK 0x80000000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_CPUS_GATE_EN_OFFSET 31

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000400

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK 0x04000000

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000800

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK 0x08000000

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE 0b0

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE 0b1

◆ PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET

#define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27

◆ PERI1PLL_GATE_STAT_REG

#define PERI1PLL_GATE_STAT_REG 0x0000198c

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK 0x00000001

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 0

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK 0x00000002

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK 0x00000008

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 3

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK 0x00000004

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 2

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK 0x00000020

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 5

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK 0x00000010

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 4

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK 0x00000040

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 6

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK 0x00000100

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 8

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK 0x00000080

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 7

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK 0x00000200

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE 0b0

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE 0b1

◆ PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET

#define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 9

◆ PLL_AUDIO0_BIAS_REG

#define PLL_AUDIO0_BIAS_REG 0x00000270

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_AUDIO0_CTRL_REG

#define PLL_AUDIO0_CTRL_REG 0x00000260

◆ PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28

◆ PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000

◆ PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_P_OFFSET 16

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_AUDIO0_PAT0_CTRL_REG

#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_AUDIO0_PAT1_CTRL_REG

#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_AUDIO1_BIAS_REG

#define PLL_AUDIO1_BIAS_REG 0x00000290

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO1_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_AUDIO1_CTRL_REG

#define PLL_AUDIO1_CTRL_REG 0x00000280

◆ PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO1_CTRL_REG_LOCK_OFFSET 28

◆ PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO1_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_AUDIO1_CTRL_REG_PLL_P_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000

◆ PLL_AUDIO1_CTRL_REG_PLL_P_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_P_OFFSET 16

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_AUDIO1_PAT0_CTRL_REG

#define PLL_AUDIO1_PAT0_CTRL_REG 0x00000288

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_AUDIO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_AUDIO1_PAT1_CTRL_REG

#define PLL_AUDIO1_PAT1_CTRL_REG 0x0000028c

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_CFG0_REG

#define PLL_CFG0_REG 0x00001f20

◆ PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK

#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff

◆ PLL_CFG0_REG_PLL_CONFIG0_OFFSET

#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0

◆ PLL_CFG1_REG

#define PLL_CFG1_REG 0x00001f24

◆ PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK

#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff

◆ PLL_CFG1_REG_PLL_CONFIG1_OFFSET

#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0

◆ PLL_CFG2_REG

#define PLL_CFG2_REG 0x00001f28

◆ PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK

#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff

◆ PLL_CFG2_REG_PLL_CONFIG2_OFFSET

#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0

◆ PLL_DDR_BIAS_REG

#define PLL_DDR_BIAS_REG 0x00000030

◆ PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_DDR_BIAS_REG_PLL_CP_OFFSET

#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_DDR_CTRL_REG

#define PLL_DDR_CTRL_REG 0x00000020

◆ PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_DDR_CTRL_REG_LOCK_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28

◆ PLL_DDR_CTRL_REG_LOCK_UNLOCKED

#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_DDR_CTRL_REG_PLL_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_DDR_CTRL_REG_PLL_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_DDR_CTRL_REG_PLL_N_OFFSET

#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_DDR_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

◆ PLL_DDR_CTRL_REG_PLL_P0_OFFSET

#define PLL_DDR_CTRL_REG_PLL_P0_OFFSET 20

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_DDR_PAT0_CTRL_REG

#define PLL_DDR_PAT0_CTRL_REG 0x00000028

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_DDR_PAT1_CTRL_REG

#define PLL_DDR_PAT1_CTRL_REG 0x0000002c

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_LOCK_DBG_CTRL_REG

#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0b0

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0b1

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL 0b0111

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL 0b1001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x00f00000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL 0b0000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL 0b1010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0b0001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DISPLL 0b1011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0b1000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL 0b0010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL 0b0011

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_USBPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_USBPLL 0b1100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VEPLL 0b0110

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL 0b0100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL 0b0101

◆ PLL_NPU_BIAS_REG

#define PLL_NPU_BIAS_REG 0x000002b0

◆ PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_NPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_NPU_CTRL_REG

#define PLL_NPU_CTRL_REG 0x000002a0

◆ PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_NPU_CTRL_REG_LOCK_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_OFFSET 28

◆ PLL_NPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_NPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_NPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_NPU_CTRL_REG_PLL_N_OFFSET

#define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_NPU_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

◆ PLL_NPU_CTRL_REG_PLL_P0_OFFSET

#define PLL_NPU_CTRL_REG_PLL_P0_OFFSET 20

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_NPU_PAT0_CTRL_REG

#define PLL_NPU_PAT0_CTRL_REG 0x000002a8

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_NPU_PAT1_CTRL_REG

#define PLL_NPU_PAT1_CTRL_REG 0x000002ac

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_PERI0_BIAS_REG

#define PLL_PERI0_BIAS_REG 0x000000b0

◆ PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_PERI0_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_PERI0_CTRL_REG

#define PLL_PERI0_CTRL_REG 0x000000a0

◆ PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_PERI0_CTRL_REG_LOCK_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28

◆ PLL_PERI0_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_PERI0_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_PERI0_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_PERI0_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_PERI0_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000

◆ PLL_PERI0_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16

◆ PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000

◆ PLL_PERI0_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20

◆ PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c

◆ PLL_PERI0_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_PERI0_PAT0_CTRL_REG

#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_PERI0_PAT1_CTRL_REG

#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_PERI1_BIAS_REG

#define PLL_PERI1_BIAS_REG 0x000000d0

◆ PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_PERI1_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_PERI1_CTRL_REG

#define PLL_PERI1_CTRL_REG 0x000000c0

◆ PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_PERI1_CTRL_REG_LOCK_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28

◆ PLL_PERI1_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_PERI1_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_PERI1_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_PERI1_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_PERI1_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000

◆ PLL_PERI1_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16

◆ PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000

◆ PLL_PERI1_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20

◆ PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c

◆ PLL_PERI1_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_PERI1_PAT0_CTRL_REG

#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_PERI1_PAT1_CTRL_REG

#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_VE_BIAS_REG

#define PLL_VE_BIAS_REG 0x00000230

◆ PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_VE_BIAS_REG_PLL_CP_OFFSET

#define PLL_VE_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_VE_CTRL_REG

#define PLL_VE_CTRL_REG 0x00000220

◆ PLL_VE_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_VE_CTRL_REG_LOCK_OFFSET

#define PLL_VE_CTRL_REG_LOCK_OFFSET 28

◆ PLL_VE_CTRL_REG_LOCK_UNLOCKED

#define PLL_VE_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_VE_CTRL_REG_PLL_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_VE_CTRL_REG_PLL_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_VE_CTRL_REG_PLL_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_VE_CTRL_REG_PLL_N_OFFSET

#define PLL_VE_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

◆ PLL_VE_CTRL_REG_PLL_P0_OFFSET

#define PLL_VE_CTRL_REG_PLL_P0_OFFSET 20

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_VE_PAT0_CTRL_REG

#define PLL_VE_PAT0_CTRL_REG 0x00000228

◆ PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_VE_PAT1_CTRL_REG

#define PLL_VE_PAT1_CTRL_REG 0x0000022c

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_VIDEO0_BIAS_REG

#define PLL_VIDEO0_BIAS_REG 0x00000130

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_VIDEO0_CTRL_REG

#define PLL_VIDEO0_CTRL_REG 0x00000120

◆ PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28

◆ PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

◆ PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_P0_OFFSET 20

◆ PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000

◆ PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_P1_OFFSET 16

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_VIDEO0_PAT0_CTRL_REG

#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_VIDEO0_PAT1_CTRL_REG

#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PLL_VIDEO1_BIAS_REG

#define PLL_VIDEO1_BIAS_REG 0x00000150

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16

◆ PLL_VIDEO1_CTRL_REG

#define PLL_VIDEO1_CTRL_REG 0x00000140

◆ PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0b0

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29

◆ PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28

◆ PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5

◆ PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00

◆ PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27

◆ PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00700000

◆ PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_P0_OFFSET 20

◆ PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00070000

◆ PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_P1_OFFSET 16

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0b0

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0b1

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6

◆ PLL_VIDEO1_PAT0_CTRL_REG

#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0b1

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0b0

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW 0b00

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b01

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT 0b10

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT 0b11

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20

◆ PLL_VIDEO1_PAT1_CTRL_REG

#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0

◆ PWM0_BGR_REG

#define PWM0_BGR_REG 0x00000784

◆ PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK

#define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK 0x00000001

◆ PWM0_BGR_REG_PWM0_GATING_MASK

#define PWM0_BGR_REG_PWM0_GATING_MASK 0b0

◆ PWM0_BGR_REG_PWM0_GATING_OFFSET

#define PWM0_BGR_REG_PWM0_GATING_OFFSET 0

◆ PWM0_BGR_REG_PWM0_GATING_PASS

#define PWM0_BGR_REG_PWM0_GATING_PASS 0b1

◆ PWM0_BGR_REG_PWM0_RST_ASSERT

#define PWM0_BGR_REG_PWM0_RST_ASSERT 0b0

◆ PWM0_BGR_REG_PWM0_RST_CLEAR_MASK

#define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK 0x00010000

◆ PWM0_BGR_REG_PWM0_RST_DE_ASSERT

#define PWM0_BGR_REG_PWM0_RST_DE_ASSERT 0b1

◆ PWM0_BGR_REG_PWM0_RST_OFFSET

#define PWM0_BGR_REG_PWM0_RST_OFFSET 16

◆ PWM1_BGR_REG

#define PWM1_BGR_REG 0x0000078c

◆ PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK

#define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK 0x00000001

◆ PWM1_BGR_REG_PWM1_GATING_MASK

#define PWM1_BGR_REG_PWM1_GATING_MASK 0b0

◆ PWM1_BGR_REG_PWM1_GATING_OFFSET

#define PWM1_BGR_REG_PWM1_GATING_OFFSET 0

◆ PWM1_BGR_REG_PWM1_GATING_PASS

#define PWM1_BGR_REG_PWM1_GATING_PASS 0b1

◆ PWM1_BGR_REG_PWM1_RST_ASSERT

#define PWM1_BGR_REG_PWM1_RST_ASSERT 0b0

◆ PWM1_BGR_REG_PWM1_RST_CLEAR_MASK

#define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK 0x00010000

◆ PWM1_BGR_REG_PWM1_RST_DE_ASSERT

#define PWM1_BGR_REG_PWM1_RST_DE_ASSERT 0b1

◆ PWM1_BGR_REG_PWM1_RST_OFFSET

#define PWM1_BGR_REG_PWM1_RST_OFFSET 16

◆ PWM2_BGR_REG

#define PWM2_BGR_REG 0x00000794

◆ PWM2_BGR_REG_PWM2_GATING_CLEAR_MASK

#define PWM2_BGR_REG_PWM2_GATING_CLEAR_MASK 0x00000001

◆ PWM2_BGR_REG_PWM2_GATING_MASK

#define PWM2_BGR_REG_PWM2_GATING_MASK 0b0

◆ PWM2_BGR_REG_PWM2_GATING_OFFSET

#define PWM2_BGR_REG_PWM2_GATING_OFFSET 0

◆ PWM2_BGR_REG_PWM2_GATING_PASS

#define PWM2_BGR_REG_PWM2_GATING_PASS 0b1

◆ PWM2_BGR_REG_PWM2_RST_ASSERT

#define PWM2_BGR_REG_PWM2_RST_ASSERT 0b0

◆ PWM2_BGR_REG_PWM2_RST_CLEAR_MASK

#define PWM2_BGR_REG_PWM2_RST_CLEAR_MASK 0x00010000

◆ PWM2_BGR_REG_PWM2_RST_DE_ASSERT

#define PWM2_BGR_REG_PWM2_RST_DE_ASSERT 0b1

◆ PWM2_BGR_REG_PWM2_RST_OFFSET

#define PWM2_BGR_REG_PWM2_RST_OFFSET 16

◆ RV_CFG_BGR_REG

#define RV_CFG_BGR_REG 0x00000b9c

◆ RV_CFG_BGR_REG_RV_CFG_GATING_CLEAR_MASK

#define RV_CFG_BGR_REG_RV_CFG_GATING_CLEAR_MASK 0x00000001

◆ RV_CFG_BGR_REG_RV_CFG_GATING_MASK

#define RV_CFG_BGR_REG_RV_CFG_GATING_MASK 0b0

◆ RV_CFG_BGR_REG_RV_CFG_GATING_OFFSET

#define RV_CFG_BGR_REG_RV_CFG_GATING_OFFSET 0

◆ RV_CFG_BGR_REG_RV_CFG_GATING_PASS

#define RV_CFG_BGR_REG_RV_CFG_GATING_PASS 0b1

◆ RV_CFG_BGR_REG_RV_CFG_RST_ASSERT

#define RV_CFG_BGR_REG_RV_CFG_RST_ASSERT 0b0

◆ RV_CFG_BGR_REG_RV_CFG_RST_CLEAR_MASK

#define RV_CFG_BGR_REG_RV_CFG_RST_CLEAR_MASK 0x00010000

◆ RV_CFG_BGR_REG_RV_CFG_RST_DE_ASSERT

#define RV_CFG_BGR_REG_RV_CFG_RST_DE_ASSERT 0b1

◆ RV_CFG_BGR_REG_RV_CFG_RST_OFFSET

#define RV_CFG_BGR_REG_RV_CFG_RST_OFFSET 16

◆ RV_CORE_CLK_REG

#define RV_CORE_CLK_REG 0x00000b80

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_CLK32K

#define RV_CORE_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_HOSC

#define RV_CORE_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_OFFSET

#define RV_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b101

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b100

◆ RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define RV_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b011

◆ RV_CORE_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK

#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK 0x00000300

◆ RV_CORE_CLK_REG_E907_AXI_DIV_CFG_OFFSET

#define RV_CORE_CLK_REG_E907_AXI_DIV_CFG_OFFSET 8

◆ RV_CORE_CLK_REG_FACTOR_M_CLEAR_MASK

#define RV_CORE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ RV_CORE_CLK_REG_FACTOR_M_OFFSET

#define RV_CORE_CLK_REG_FACTOR_M_OFFSET 0

◆ RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLEAR_MASK

#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLEAR_MASK 0x80000000

◆ RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_OFF

#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_OFF 0b0

◆ RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_ON

#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_CLOCK_IS_ON 0b1

◆ RV_CORE_CLK_REG_RV_CORE_CLK_GATING_OFFSET

#define RV_CORE_CLK_REG_RV_CORE_CLK_GATING_OFFSET 31

◆ RV_SYS_BGR_REG

#define RV_SYS_BGR_REG 0x00000b94

◆ RV_SYS_BGR_REG_RV_CORE_RST_ASSERT

#define RV_SYS_BGR_REG_RV_CORE_RST_ASSERT 0b0

◆ RV_SYS_BGR_REG_RV_CORE_RST_CLEAR_MASK

#define RV_SYS_BGR_REG_RV_CORE_RST_CLEAR_MASK 0x00010000

◆ RV_SYS_BGR_REG_RV_CORE_RST_DE_ASSERT

#define RV_SYS_BGR_REG_RV_CORE_RST_DE_ASSERT 0b1

◆ RV_SYS_BGR_REG_RV_CORE_RST_OFFSET

#define RV_SYS_BGR_REG_RV_CORE_RST_OFFSET 16

◆ RV_SYS_BGR_REG_RV_SYS_RST_ASSERT

#define RV_SYS_BGR_REG_RV_SYS_RST_ASSERT 0b0

◆ RV_SYS_BGR_REG_RV_SYS_RST_CLEAR_MASK

#define RV_SYS_BGR_REG_RV_SYS_RST_CLEAR_MASK 0x00020000

◆ RV_SYS_BGR_REG_RV_SYS_RST_DE_ASSERT

#define RV_SYS_BGR_REG_RV_SYS_RST_DE_ASSERT 0b1

◆ RV_SYS_BGR_REG_RV_SYS_RST_OFFSET

#define RV_SYS_BGR_REG_RV_SYS_RST_OFFSET 17

◆ RV_TS_CLK_REG

#define RV_TS_CLK_REG 0x00000b88

◆ RV_TS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define RV_TS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ RV_TS_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define RV_TS_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ RV_TS_CLK_REG_CLK_SRC_SEL_CLK32K

#define RV_TS_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ RV_TS_CLK_REG_CLK_SRC_SEL_HOSC

#define RV_TS_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ RV_TS_CLK_REG_CLK_SRC_SEL_OFFSET

#define RV_TS_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ RV_TS_CLK_REG_RV_TS_CLK_GATING_CLEAR_MASK

#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLEAR_MASK 0x80000000

◆ RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_OFF

#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_OFF 0b0

◆ RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_ON

#define RV_TS_CLK_REG_RV_TS_CLK_GATING_CLOCK_IS_ON 0b1

◆ RV_TS_CLK_REG_RV_TS_CLK_GATING_OFFSET

#define RV_TS_CLK_REG_RV_TS_CLK_GATING_OFFSET 31

◆ SERDES_AXI_CLK_REG

#define SERDES_AXI_CLK_REG 0x000013e0

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_HOSC

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_OFFSET

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b11

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b10

◆ SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SERDES_AXI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b01

◆ SERDES_AXI_CLK_REG_FACTOR_M_CLEAR_MASK

#define SERDES_AXI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SERDES_AXI_CLK_REG_FACTOR_M_OFFSET

#define SERDES_AXI_CLK_REG_FACTOR_M_OFFSET 0

◆ SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLEAR_MASK

#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLEAR_MASK 0x80000000

◆ SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_OFF

#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_ON

#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_CLOCK_IS_ON 0b1

◆ SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_OFFSET

#define SERDES_AXI_CLK_REG_SERDES_AXI_CLK_GATING_OFFSET 31

◆ SERDES_BGR_REG

#define SERDES_BGR_REG 0x000013cc

◆ SERDES_BGR_REG_SERDES_NOPPU_RST_ASSERT

#define SERDES_BGR_REG_SERDES_NOPPU_RST_ASSERT 0b0

◆ SERDES_BGR_REG_SERDES_NOPPU_RST_CLEAR_MASK

#define SERDES_BGR_REG_SERDES_NOPPU_RST_CLEAR_MASK 0x00020000

◆ SERDES_BGR_REG_SERDES_NOPPU_RST_DE_ASSERT

#define SERDES_BGR_REG_SERDES_NOPPU_RST_DE_ASSERT 0b1

◆ SERDES_BGR_REG_SERDES_NOPPU_RST_OFFSET

#define SERDES_BGR_REG_SERDES_NOPPU_RST_OFFSET 17

◆ SERDES_BGR_REG_SERDES_RST_ASSERT

#define SERDES_BGR_REG_SERDES_RST_ASSERT 0b0

◆ SERDES_BGR_REG_SERDES_RST_CLEAR_MASK

#define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK 0x00010000

◆ SERDES_BGR_REG_SERDES_RST_DE_ASSERT

#define SERDES_BGR_REG_SERDES_RST_DE_ASSERT 0b1

◆ SERDES_BGR_REG_SERDES_RST_OFFSET

#define SERDES_BGR_REG_SERDES_RST_OFFSET 16

◆ SERDES_PHY_CFG_CLK_REG

#define SERDES_PHY_CFG_CLK_REG 0x000013c0

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b1

◆ SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SERDES_PHY_CFG_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b0

◆ SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET

#define SERDES_PHY_CFG_CLK_REG_FACTOR_M_OFFSET 0

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLEAR_MASK 0x80000000

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_CLOCK_IS_ON 0b1

◆ SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET

#define SERDES_PHY_CFG_CLK_REG_SERDES_PHY_CFG_CLK_GATING_OFFSET 31

◆ SERDES_PHY_REF_CLK_REG

#define SERDES_PHY_REF_CLK_REG 0x000013c4

◆ SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_HOSC

#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET

#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SERDES_PHY_REF_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b1

◆ SERDES_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK

#define SERDES_PHY_REF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SERDES_PHY_REF_CLK_REG_FACTOR_M_OFFSET

#define SERDES_PHY_REF_CLK_REG_FACTOR_M_OFFSET 0

◆ SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLEAR_MASK

#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLEAR_MASK 0x80000000

◆ SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_OFF

#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_ON

#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_CLOCK_IS_ON 0b1

◆ SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_OFFSET

#define SERDES_PHY_REF_CLK_REG_SERDES_PHY_REF_CLK_GATING_OFFSET 31

◆ SMHC0_BGR_REG

#define SMHC0_BGR_REG 0x00000d0c

◆ SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK

#define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK 0x00000001

◆ SMHC0_BGR_REG_SMHC0_GATING_MASK

#define SMHC0_BGR_REG_SMHC0_GATING_MASK 0b0

◆ SMHC0_BGR_REG_SMHC0_GATING_OFFSET

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0

◆ SMHC0_BGR_REG_SMHC0_GATING_PASS

#define SMHC0_BGR_REG_SMHC0_GATING_PASS 0b1

◆ SMHC0_BGR_REG_SMHC0_RST_ASSERT

#define SMHC0_BGR_REG_SMHC0_RST_ASSERT 0b0

◆ SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK

#define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK 0x00010000

◆ SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT

#define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT 0b1

◆ SMHC0_BGR_REG_SMHC0_RST_OFFSET

#define SMHC0_BGR_REG_SMHC0_RST_OFFSET 16

◆ SMHC0_CLK_REG

#define SMHC0_CLK_REG 0x00000d00

◆ SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

◆ SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SMHC0_CLK_REG_FACTOR_M_OFFSET

#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0

◆ SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SMHC0_CLK_REG_FACTOR_N_OFFSET

#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0b1

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31

◆ SMHC1_BGR_REG

#define SMHC1_BGR_REG 0x00000d1c

◆ SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK

#define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK 0x00000001

◆ SMHC1_BGR_REG_SMHC1_GATING_MASK

#define SMHC1_BGR_REG_SMHC1_GATING_MASK 0b0

◆ SMHC1_BGR_REG_SMHC1_GATING_OFFSET

#define SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0

◆ SMHC1_BGR_REG_SMHC1_GATING_PASS

#define SMHC1_BGR_REG_SMHC1_GATING_PASS 0b1

◆ SMHC1_BGR_REG_SMHC1_RST_ASSERT

#define SMHC1_BGR_REG_SMHC1_RST_ASSERT 0b0

◆ SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK

#define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK 0x00010000

◆ SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT

#define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT 0b1

◆ SMHC1_BGR_REG_SMHC1_RST_OFFSET

#define SMHC1_BGR_REG_SMHC1_RST_OFFSET 16

◆ SMHC1_CLK_REG

#define SMHC1_CLK_REG 0x00000d10

◆ SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b001

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b100

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b011

◆ SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SMHC1_CLK_REG_FACTOR_M_OFFSET

#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0

◆ SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SMHC1_CLK_REG_FACTOR_N_OFFSET

#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0b1

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31

◆ SMHC2_BGR_REG

#define SMHC2_BGR_REG 0x00000d2c

◆ SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK

#define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK 0x00000001

◆ SMHC2_BGR_REG_SMHC2_GATING_MASK

#define SMHC2_BGR_REG_SMHC2_GATING_MASK 0b0

◆ SMHC2_BGR_REG_SMHC2_GATING_OFFSET

#define SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0

◆ SMHC2_BGR_REG_SMHC2_GATING_PASS

#define SMHC2_BGR_REG_SMHC2_GATING_PASS 0b1

◆ SMHC2_BGR_REG_SMHC2_RST_ASSERT

#define SMHC2_BGR_REG_SMHC2_RST_ASSERT 0b0

◆ SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK

#define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK 0x00010000

◆ SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT

#define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT 0b1

◆ SMHC2_BGR_REG_SMHC2_RST_OFFSET

#define SMHC2_BGR_REG_SMHC2_RST_OFFSET 16

◆ SMHC2_CLK_REG

#define SMHC2_CLK_REG 0x00000d20

◆ SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0b010

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0b001

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0b100

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0b011

◆ SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SMHC2_CLK_REG_FACTOR_M_OFFSET

#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0

◆ SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SMHC2_CLK_REG_FACTOR_N_OFFSET

#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0b1

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31

◆ SPI0_BGR_REG

#define SPI0_BGR_REG 0x00000f04

◆ SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK

#define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK 0x00000001

◆ SPI0_BGR_REG_SPI0_GATING_MASK

#define SPI0_BGR_REG_SPI0_GATING_MASK 0b0

◆ SPI0_BGR_REG_SPI0_GATING_OFFSET

#define SPI0_BGR_REG_SPI0_GATING_OFFSET 0

◆ SPI0_BGR_REG_SPI0_GATING_PASS

#define SPI0_BGR_REG_SPI0_GATING_PASS 0b1

◆ SPI0_BGR_REG_SPI0_RST_ASSERT

#define SPI0_BGR_REG_SPI0_RST_ASSERT 0b0

◆ SPI0_BGR_REG_SPI0_RST_CLEAR_MASK

#define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK 0x00010000

◆ SPI0_BGR_REG_SPI0_RST_DE_ASSERT

#define SPI0_BGR_REG_SPI0_RST_DE_ASSERT 0b1

◆ SPI0_BGR_REG_SPI0_RST_OFFSET

#define SPI0_BGR_REG_SPI0_RST_OFFSET 16

◆ SPI0_CLK_REG

#define SPI0_CLK_REG 0x00000f00

◆ SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPI0_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPI0_CLK_REG_FACTOR_M_OFFSET

#define SPI0_CLK_REG_FACTOR_M_OFFSET 0

◆ SPI0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPI0_CLK_REG_FACTOR_N_OFFSET

#define SPI0_CLK_REG_FACTOR_N_OFFSET 8

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31

◆ SPI1_BGR_REG

#define SPI1_BGR_REG 0x00000f0c

◆ SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK

#define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK 0x00000001

◆ SPI1_BGR_REG_SPI1_GATING_MASK

#define SPI1_BGR_REG_SPI1_GATING_MASK 0b0

◆ SPI1_BGR_REG_SPI1_GATING_OFFSET

#define SPI1_BGR_REG_SPI1_GATING_OFFSET 0

◆ SPI1_BGR_REG_SPI1_GATING_PASS

#define SPI1_BGR_REG_SPI1_GATING_PASS 0b1

◆ SPI1_BGR_REG_SPI1_RST_ASSERT

#define SPI1_BGR_REG_SPI1_RST_ASSERT 0b0

◆ SPI1_BGR_REG_SPI1_RST_CLEAR_MASK

#define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK 0x00010000

◆ SPI1_BGR_REG_SPI1_RST_DE_ASSERT

#define SPI1_BGR_REG_SPI1_RST_DE_ASSERT 0b1

◆ SPI1_BGR_REG_SPI1_RST_OFFSET

#define SPI1_BGR_REG_SPI1_RST_OFFSET 16

◆ SPI1_CLK_REG

#define SPI1_CLK_REG 0x00000f08

◆ SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPI1_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPI1_CLK_REG_FACTOR_M_OFFSET

#define SPI1_CLK_REG_FACTOR_M_OFFSET 0

◆ SPI1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPI1_CLK_REG_FACTOR_N_OFFSET

#define SPI1_CLK_REG_FACTOR_N_OFFSET 8

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31

◆ SPI2_BGR_REG

#define SPI2_BGR_REG 0x00000f14

◆ SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK

#define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK 0x00000001

◆ SPI2_BGR_REG_SPI2_GATING_MASK

#define SPI2_BGR_REG_SPI2_GATING_MASK 0b0

◆ SPI2_BGR_REG_SPI2_GATING_OFFSET

#define SPI2_BGR_REG_SPI2_GATING_OFFSET 0

◆ SPI2_BGR_REG_SPI2_GATING_PASS

#define SPI2_BGR_REG_SPI2_GATING_PASS 0b1

◆ SPI2_BGR_REG_SPI2_RST_ASSERT

#define SPI2_BGR_REG_SPI2_RST_ASSERT 0b0

◆ SPI2_BGR_REG_SPI2_RST_CLEAR_MASK

#define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK 0x00010000

◆ SPI2_BGR_REG_SPI2_RST_DE_ASSERT

#define SPI2_BGR_REG_SPI2_RST_DE_ASSERT 0b1

◆ SPI2_BGR_REG_SPI2_RST_OFFSET

#define SPI2_BGR_REG_SPI2_RST_OFFSET 16

◆ SPI2_CLK_REG

#define SPI2_CLK_REG 0x00000f10

◆ SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPI2_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPI2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPI2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPI2_CLK_REG_FACTOR_M_OFFSET

#define SPI2_CLK_REG_FACTOR_M_OFFSET 0

◆ SPI2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPI2_CLK_REG_FACTOR_N_OFFSET

#define SPI2_CLK_REG_FACTOR_N_OFFSET 8

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31

◆ SPI3_BGR_REG

#define SPI3_BGR_REG 0x00000f24

◆ SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK

#define SPI3_BGR_REG_SPI3_GATING_CLEAR_MASK 0x00000001

◆ SPI3_BGR_REG_SPI3_GATING_MASK

#define SPI3_BGR_REG_SPI3_GATING_MASK 0b0

◆ SPI3_BGR_REG_SPI3_GATING_OFFSET

#define SPI3_BGR_REG_SPI3_GATING_OFFSET 0

◆ SPI3_BGR_REG_SPI3_GATING_PASS

#define SPI3_BGR_REG_SPI3_GATING_PASS 0b1

◆ SPI3_BGR_REG_SPI3_RST_ASSERT

#define SPI3_BGR_REG_SPI3_RST_ASSERT 0b0

◆ SPI3_BGR_REG_SPI3_RST_CLEAR_MASK

#define SPI3_BGR_REG_SPI3_RST_CLEAR_MASK 0x00010000

◆ SPI3_BGR_REG_SPI3_RST_DE_ASSERT

#define SPI3_BGR_REG_SPI3_RST_DE_ASSERT 0b1

◆ SPI3_BGR_REG_SPI3_RST_OFFSET

#define SPI3_BGR_REG_SPI3_RST_OFFSET 16

◆ SPI3_CLK_REG

#define SPI3_CLK_REG 0x00000f20

◆ SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPI3_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPI3_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

◆ SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI3_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPI3_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPI3_CLK_REG_FACTOR_M_OFFSET

#define SPI3_CLK_REG_FACTOR_M_OFFSET 0

◆ SPI3_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPI3_CLK_REG_FACTOR_N_OFFSET

#define SPI3_CLK_REG_FACTOR_N_OFFSET 8

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON

#define SPI3_CLK_REG_SPI3_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET

#define SPI3_CLK_REG_SPI3_CLK_GATING_OFFSET 31

◆ SPI4_BGR_REG

#define SPI4_BGR_REG 0x00000f2c

◆ SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK

#define SPI4_BGR_REG_SPI4_GATING_CLEAR_MASK 0x00000001

◆ SPI4_BGR_REG_SPI4_GATING_MASK

#define SPI4_BGR_REG_SPI4_GATING_MASK 0b0

◆ SPI4_BGR_REG_SPI4_GATING_OFFSET

#define SPI4_BGR_REG_SPI4_GATING_OFFSET 0

◆ SPI4_BGR_REG_SPI4_GATING_PASS

#define SPI4_BGR_REG_SPI4_GATING_PASS 0b1

◆ SPI4_BGR_REG_SPI4_RST_ASSERT

#define SPI4_BGR_REG_SPI4_RST_ASSERT 0b0

◆ SPI4_BGR_REG_SPI4_RST_CLEAR_MASK

#define SPI4_BGR_REG_SPI4_RST_CLEAR_MASK 0x00010000

◆ SPI4_BGR_REG_SPI4_RST_DE_ASSERT

#define SPI4_BGR_REG_SPI4_RST_DE_ASSERT 0b1

◆ SPI4_BGR_REG_SPI4_RST_OFFSET

#define SPI4_BGR_REG_SPI4_RST_OFFSET 16

◆ SPI4_CLK_REG

#define SPI4_CLK_REG 0x00000f28

◆ SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPI4_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI4_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPI4_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI4_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b010

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_200M 0b110

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b101

◆ SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPI4_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPI4_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI4_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPI4_CLK_REG_FACTOR_M_OFFSET

#define SPI4_CLK_REG_FACTOR_M_OFFSET 0

◆ SPI4_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI4_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPI4_CLK_REG_FACTOR_N_OFFSET

#define SPI4_CLK_REG_FACTOR_N_OFFSET 8

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON

#define SPI4_CLK_REG_SPI4_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET

#define SPI4_CLK_REG_SPI4_CLK_GATING_OFFSET 31

◆ SPIF_BGR_REG

#define SPIF_BGR_REG 0x00000f1c

◆ SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK

#define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK 0x00000001

◆ SPIF_BGR_REG_SPIF_GATING_MASK

#define SPIF_BGR_REG_SPIF_GATING_MASK 0b0

◆ SPIF_BGR_REG_SPIF_GATING_OFFSET

#define SPIF_BGR_REG_SPIF_GATING_OFFSET 0

◆ SPIF_BGR_REG_SPIF_GATING_PASS

#define SPIF_BGR_REG_SPIF_GATING_PASS 0b1

◆ SPIF_BGR_REG_SPIF_RST_ASSERT

#define SPIF_BGR_REG_SPIF_RST_ASSERT 0b0

◆ SPIF_BGR_REG_SPIF_RST_CLEAR_MASK

#define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK 0x00010000

◆ SPIF_BGR_REG_SPIF_RST_DE_ASSERT

#define SPIF_BGR_REG_SPIF_RST_DE_ASSERT 0b1

◆ SPIF_BGR_REG_SPIF_RST_OFFSET

#define SPIF_BGR_REG_SPIF_RST_OFFSET 16

◆ SPIF_CLK_REG

#define SPIF_CLK_REG 0x00000f18

◆ SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ SPIF_CLK_REG_CLK_SRC_SEL_HOSC

#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ SPIF_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b110

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M 0b101

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_480M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_480M 0b100

◆ SPIF_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ SPIF_CLK_REG_FACTOR_M_OFFSET

#define SPIF_CLK_REG_FACTOR_M_OFFSET 0

◆ SPIF_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00

◆ SPIF_CLK_REG_FACTOR_N_OFFSET

#define SPIF_CLK_REG_FACTOR_N_OFFSET 8

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK 0x80000000

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0b0

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0b1

◆ SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET

#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31

◆ SPINLOCK_BGR_REG

#define SPINLOCK_BGR_REG 0x00000724

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK 0x00000001

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK 0x00010000

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16

◆ SYSDAP_BGR_REG

#define SYSDAP_BGR_REG 0x000007ac

◆ SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK 0x00000001

◆ SYSDAP_BGR_REG_SYSDAP_GATING_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0b0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG

#define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG 0b1

◆ SYSDAP_BGR_REG_SYSDAP_RST_ASSERT

#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0b0

◆ SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK 0x00010000

◆ SYSDAP_BGR_REG_SYSDAP_RST_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16

◆ SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG

#define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG 0b1

◆ SYSDAP_REQ_CTRL_REG

#define SYSDAP_REQ_CTRL_REG 0x00001f10

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK 0x00000001

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0

◆ THS_BGR_REG

#define THS_BGR_REG 0x00000fe4

◆ THS_BGR_REG_THS_GATING_CLEAR_MASK

#define THS_BGR_REG_THS_GATING_CLEAR_MASK 0x00000001

◆ THS_BGR_REG_THS_GATING_MASK

#define THS_BGR_REG_THS_GATING_MASK 0b0

◆ THS_BGR_REG_THS_GATING_OFFSET

#define THS_BGR_REG_THS_GATING_OFFSET 0

◆ THS_BGR_REG_THS_GATING_PASS

#define THS_BGR_REG_THS_GATING_PASS 0b1

◆ THS_BGR_REG_THS_RST_ASSERT

#define THS_BGR_REG_THS_RST_ASSERT 0b0

◆ THS_BGR_REG_THS_RST_CLEAR_MASK

#define THS_BGR_REG_THS_RST_CLEAR_MASK 0x00010000

◆ THS_BGR_REG_THS_RST_DE_ASSERT

#define THS_BGR_REG_THS_RST_DE_ASSERT 0b1

◆ THS_BGR_REG_THS_RST_OFFSET

#define THS_BGR_REG_THS_RST_OFFSET 16

◆ TIMER0_CLK_REG

#define TIMER0_CLK_REG 0x00000800

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER0_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER0_CLK_REG_FACTOR_M__1

#define TIMER0_CLK_REG_FACTOR_M__1 0b000

◆ TIMER0_CLK_REG_FACTOR_M__128

#define TIMER0_CLK_REG_FACTOR_M__128 0b111

◆ TIMER0_CLK_REG_FACTOR_M__16

#define TIMER0_CLK_REG_FACTOR_M__16 0b100

◆ TIMER0_CLK_REG_FACTOR_M__2

#define TIMER0_CLK_REG_FACTOR_M__2 0b001

◆ TIMER0_CLK_REG_FACTOR_M__32

#define TIMER0_CLK_REG_FACTOR_M__32 0b101

◆ TIMER0_CLK_REG_FACTOR_M__4

#define TIMER0_CLK_REG_FACTOR_M__4 0b010

◆ TIMER0_CLK_REG_FACTOR_M__64

#define TIMER0_CLK_REG_FACTOR_M__64 0b110

◆ TIMER0_CLK_REG_FACTOR_M__8

#define TIMER0_CLK_REG_FACTOR_M__8 0b011

◆ TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER0_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE 0b0

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE 0b1

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET 31

◆ TIMER0_RV_CLK_REG

#define TIMER0_RV_CLK_REG 0x00000860

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER0_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER0_RV_CLK_REG_FACTOR_M__1

#define TIMER0_RV_CLK_REG_FACTOR_M__1 0b000

◆ TIMER0_RV_CLK_REG_FACTOR_M__128

#define TIMER0_RV_CLK_REG_FACTOR_M__128 0b111

◆ TIMER0_RV_CLK_REG_FACTOR_M__16

#define TIMER0_RV_CLK_REG_FACTOR_M__16 0b100

◆ TIMER0_RV_CLK_REG_FACTOR_M__2

#define TIMER0_RV_CLK_REG_FACTOR_M__2 0b001

◆ TIMER0_RV_CLK_REG_FACTOR_M__32

#define TIMER0_RV_CLK_REG_FACTOR_M__32 0b101

◆ TIMER0_RV_CLK_REG_FACTOR_M__4

#define TIMER0_RV_CLK_REG_FACTOR_M__4 0b010

◆ TIMER0_RV_CLK_REG_FACTOR_M__64

#define TIMER0_RV_CLK_REG_FACTOR_M__64 0b110

◆ TIMER0_RV_CLK_REG_FACTOR_M__8

#define TIMER0_RV_CLK_REG_FACTOR_M__8 0b011

◆ TIMER0_RV_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER0_RV_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_RV_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_CLEAR_MASK

#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_DISABLE

#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_DISABLE 0b0

◆ TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_ENABLE

#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_ENABLE 0b1

◆ TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_OFFSET

#define TIMER0_RV_CLK_REG_TIMER0_RV_CLK_GATING_OFFSET 31

◆ TIMER1_CLK_REG

#define TIMER1_CLK_REG 0x00000804

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER1_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER1_CLK_REG_FACTOR_M__1

#define TIMER1_CLK_REG_FACTOR_M__1 0b000

◆ TIMER1_CLK_REG_FACTOR_M__128

#define TIMER1_CLK_REG_FACTOR_M__128 0b111

◆ TIMER1_CLK_REG_FACTOR_M__16

#define TIMER1_CLK_REG_FACTOR_M__16 0b100

◆ TIMER1_CLK_REG_FACTOR_M__2

#define TIMER1_CLK_REG_FACTOR_M__2 0b001

◆ TIMER1_CLK_REG_FACTOR_M__32

#define TIMER1_CLK_REG_FACTOR_M__32 0b101

◆ TIMER1_CLK_REG_FACTOR_M__4

#define TIMER1_CLK_REG_FACTOR_M__4 0b010

◆ TIMER1_CLK_REG_FACTOR_M__64

#define TIMER1_CLK_REG_FACTOR_M__64 0b110

◆ TIMER1_CLK_REG_FACTOR_M__8

#define TIMER1_CLK_REG_FACTOR_M__8 0b011

◆ TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER1_CLK_REG_FACTOR_M_OFFSET

#define TIMER1_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE 0b0

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE 0b1

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET 31

◆ TIMER1_RV_CLK_REG

#define TIMER1_RV_CLK_REG 0x00000864

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER1_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER1_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER1_RV_CLK_REG_FACTOR_M__1

#define TIMER1_RV_CLK_REG_FACTOR_M__1 0b000

◆ TIMER1_RV_CLK_REG_FACTOR_M__128

#define TIMER1_RV_CLK_REG_FACTOR_M__128 0b111

◆ TIMER1_RV_CLK_REG_FACTOR_M__16

#define TIMER1_RV_CLK_REG_FACTOR_M__16 0b100

◆ TIMER1_RV_CLK_REG_FACTOR_M__2

#define TIMER1_RV_CLK_REG_FACTOR_M__2 0b001

◆ TIMER1_RV_CLK_REG_FACTOR_M__32

#define TIMER1_RV_CLK_REG_FACTOR_M__32 0b101

◆ TIMER1_RV_CLK_REG_FACTOR_M__4

#define TIMER1_RV_CLK_REG_FACTOR_M__4 0b010

◆ TIMER1_RV_CLK_REG_FACTOR_M__64

#define TIMER1_RV_CLK_REG_FACTOR_M__64 0b110

◆ TIMER1_RV_CLK_REG_FACTOR_M__8

#define TIMER1_RV_CLK_REG_FACTOR_M__8 0b011

◆ TIMER1_RV_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER1_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER1_RV_CLK_REG_FACTOR_M_OFFSET

#define TIMER1_RV_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_CLEAR_MASK

#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_DISABLE

#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_DISABLE 0b0

◆ TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_ENABLE

#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_ENABLE 0b1

◆ TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_OFFSET

#define TIMER1_RV_CLK_REG_TIMER1_RV_CLK_GATING_OFFSET 31

◆ TIMER2_CLK_REG

#define TIMER2_CLK_REG 0x00000808

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER2_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER2_CLK_REG_FACTOR_M__1

#define TIMER2_CLK_REG_FACTOR_M__1 0b000

◆ TIMER2_CLK_REG_FACTOR_M__128

#define TIMER2_CLK_REG_FACTOR_M__128 0b111

◆ TIMER2_CLK_REG_FACTOR_M__16

#define TIMER2_CLK_REG_FACTOR_M__16 0b100

◆ TIMER2_CLK_REG_FACTOR_M__2

#define TIMER2_CLK_REG_FACTOR_M__2 0b001

◆ TIMER2_CLK_REG_FACTOR_M__32

#define TIMER2_CLK_REG_FACTOR_M__32 0b101

◆ TIMER2_CLK_REG_FACTOR_M__4

#define TIMER2_CLK_REG_FACTOR_M__4 0b010

◆ TIMER2_CLK_REG_FACTOR_M__64

#define TIMER2_CLK_REG_FACTOR_M__64 0b110

◆ TIMER2_CLK_REG_FACTOR_M__8

#define TIMER2_CLK_REG_FACTOR_M__8 0b011

◆ TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER2_CLK_REG_FACTOR_M_OFFSET

#define TIMER2_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE 0b0

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE 0b1

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET 31

◆ TIMER2_RV_CLK_REG

#define TIMER2_RV_CLK_REG 0x00000868

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER2_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER2_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER2_RV_CLK_REG_FACTOR_M__1

#define TIMER2_RV_CLK_REG_FACTOR_M__1 0b000

◆ TIMER2_RV_CLK_REG_FACTOR_M__128

#define TIMER2_RV_CLK_REG_FACTOR_M__128 0b111

◆ TIMER2_RV_CLK_REG_FACTOR_M__16

#define TIMER2_RV_CLK_REG_FACTOR_M__16 0b100

◆ TIMER2_RV_CLK_REG_FACTOR_M__2

#define TIMER2_RV_CLK_REG_FACTOR_M__2 0b001

◆ TIMER2_RV_CLK_REG_FACTOR_M__32

#define TIMER2_RV_CLK_REG_FACTOR_M__32 0b101

◆ TIMER2_RV_CLK_REG_FACTOR_M__4

#define TIMER2_RV_CLK_REG_FACTOR_M__4 0b010

◆ TIMER2_RV_CLK_REG_FACTOR_M__64

#define TIMER2_RV_CLK_REG_FACTOR_M__64 0b110

◆ TIMER2_RV_CLK_REG_FACTOR_M__8

#define TIMER2_RV_CLK_REG_FACTOR_M__8 0b011

◆ TIMER2_RV_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER2_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER2_RV_CLK_REG_FACTOR_M_OFFSET

#define TIMER2_RV_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_CLEAR_MASK

#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_DISABLE

#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_DISABLE 0b0

◆ TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_ENABLE

#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_ENABLE 0b1

◆ TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_OFFSET

#define TIMER2_RV_CLK_REG_TIMER2_RV_CLK_GATING_OFFSET 31

◆ TIMER3_CLK_REG

#define TIMER3_CLK_REG 0x0000080c

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER3_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER3_CLK_REG_FACTOR_M__1

#define TIMER3_CLK_REG_FACTOR_M__1 0b000

◆ TIMER3_CLK_REG_FACTOR_M__128

#define TIMER3_CLK_REG_FACTOR_M__128 0b111

◆ TIMER3_CLK_REG_FACTOR_M__16

#define TIMER3_CLK_REG_FACTOR_M__16 0b100

◆ TIMER3_CLK_REG_FACTOR_M__2

#define TIMER3_CLK_REG_FACTOR_M__2 0b001

◆ TIMER3_CLK_REG_FACTOR_M__32

#define TIMER3_CLK_REG_FACTOR_M__32 0b101

◆ TIMER3_CLK_REG_FACTOR_M__4

#define TIMER3_CLK_REG_FACTOR_M__4 0b010

◆ TIMER3_CLK_REG_FACTOR_M__64

#define TIMER3_CLK_REG_FACTOR_M__64 0b110

◆ TIMER3_CLK_REG_FACTOR_M__8

#define TIMER3_CLK_REG_FACTOR_M__8 0b011

◆ TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER3_CLK_REG_FACTOR_M_OFFSET

#define TIMER3_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE 0b0

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE 0b1

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET 31

◆ TIMER3_RV_CLK_REG

#define TIMER3_RV_CLK_REG 0x0000086c

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER3_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER3_RV_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER3_RV_CLK_REG_FACTOR_M__1

#define TIMER3_RV_CLK_REG_FACTOR_M__1 0b000

◆ TIMER3_RV_CLK_REG_FACTOR_M__128

#define TIMER3_RV_CLK_REG_FACTOR_M__128 0b111

◆ TIMER3_RV_CLK_REG_FACTOR_M__16

#define TIMER3_RV_CLK_REG_FACTOR_M__16 0b100

◆ TIMER3_RV_CLK_REG_FACTOR_M__2

#define TIMER3_RV_CLK_REG_FACTOR_M__2 0b001

◆ TIMER3_RV_CLK_REG_FACTOR_M__32

#define TIMER3_RV_CLK_REG_FACTOR_M__32 0b101

◆ TIMER3_RV_CLK_REG_FACTOR_M__4

#define TIMER3_RV_CLK_REG_FACTOR_M__4 0b010

◆ TIMER3_RV_CLK_REG_FACTOR_M__64

#define TIMER3_RV_CLK_REG_FACTOR_M__64 0b110

◆ TIMER3_RV_CLK_REG_FACTOR_M__8

#define TIMER3_RV_CLK_REG_FACTOR_M__8 0b011

◆ TIMER3_RV_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER3_RV_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER3_RV_CLK_REG_FACTOR_M_OFFSET

#define TIMER3_RV_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_CLEAR_MASK

#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_DISABLE

#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_DISABLE 0b0

◆ TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_ENABLE

#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_ENABLE 0b1

◆ TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_OFFSET

#define TIMER3_RV_CLK_REG_TIMER3_RV_CLK_GATING_OFFSET 31

◆ TIMER4_CLK_REG

#define TIMER4_CLK_REG 0x00000810

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER4_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER4_CLK_REG_FACTOR_M__1

#define TIMER4_CLK_REG_FACTOR_M__1 0b000

◆ TIMER4_CLK_REG_FACTOR_M__128

#define TIMER4_CLK_REG_FACTOR_M__128 0b111

◆ TIMER4_CLK_REG_FACTOR_M__16

#define TIMER4_CLK_REG_FACTOR_M__16 0b100

◆ TIMER4_CLK_REG_FACTOR_M__2

#define TIMER4_CLK_REG_FACTOR_M__2 0b001

◆ TIMER4_CLK_REG_FACTOR_M__32

#define TIMER4_CLK_REG_FACTOR_M__32 0b101

◆ TIMER4_CLK_REG_FACTOR_M__4

#define TIMER4_CLK_REG_FACTOR_M__4 0b010

◆ TIMER4_CLK_REG_FACTOR_M__64

#define TIMER4_CLK_REG_FACTOR_M__64 0b110

◆ TIMER4_CLK_REG_FACTOR_M__8

#define TIMER4_CLK_REG_FACTOR_M__8 0b011

◆ TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER4_CLK_REG_FACTOR_M_OFFSET

#define TIMER4_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE 0b0

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE 0b1

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET 31

◆ TIMER5_CLK_REG

#define TIMER5_CLK_REG 0x00000814

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER5_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER5_CLK_REG_FACTOR_M__1

#define TIMER5_CLK_REG_FACTOR_M__1 0b000

◆ TIMER5_CLK_REG_FACTOR_M__128

#define TIMER5_CLK_REG_FACTOR_M__128 0b111

◆ TIMER5_CLK_REG_FACTOR_M__16

#define TIMER5_CLK_REG_FACTOR_M__16 0b100

◆ TIMER5_CLK_REG_FACTOR_M__2

#define TIMER5_CLK_REG_FACTOR_M__2 0b001

◆ TIMER5_CLK_REG_FACTOR_M__32

#define TIMER5_CLK_REG_FACTOR_M__32 0b101

◆ TIMER5_CLK_REG_FACTOR_M__4

#define TIMER5_CLK_REG_FACTOR_M__4 0b010

◆ TIMER5_CLK_REG_FACTOR_M__64

#define TIMER5_CLK_REG_FACTOR_M__64 0b110

◆ TIMER5_CLK_REG_FACTOR_M__8

#define TIMER5_CLK_REG_FACTOR_M__8 0b011

◆ TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER5_CLK_REG_FACTOR_M_OFFSET

#define TIMER5_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE 0b0

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE 0b1

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET 31

◆ TIMER6_CLK_REG

#define TIMER6_CLK_REG 0x00000818

◆ TIMER6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER6_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER6_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER6_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER6_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER6_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER6_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER6_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER6_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER6_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER6_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER6_CLK_REG_FACTOR_M__1

#define TIMER6_CLK_REG_FACTOR_M__1 0b000

◆ TIMER6_CLK_REG_FACTOR_M__128

#define TIMER6_CLK_REG_FACTOR_M__128 0b111

◆ TIMER6_CLK_REG_FACTOR_M__16

#define TIMER6_CLK_REG_FACTOR_M__16 0b100

◆ TIMER6_CLK_REG_FACTOR_M__2

#define TIMER6_CLK_REG_FACTOR_M__2 0b001

◆ TIMER6_CLK_REG_FACTOR_M__32

#define TIMER6_CLK_REG_FACTOR_M__32 0b101

◆ TIMER6_CLK_REG_FACTOR_M__4

#define TIMER6_CLK_REG_FACTOR_M__4 0b010

◆ TIMER6_CLK_REG_FACTOR_M__64

#define TIMER6_CLK_REG_FACTOR_M__64 0b110

◆ TIMER6_CLK_REG_FACTOR_M__8

#define TIMER6_CLK_REG_FACTOR_M__8 0b011

◆ TIMER6_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER6_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER6_CLK_REG_FACTOR_M_OFFSET

#define TIMER6_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER6_CLK_REG_TIMER6_CLK_GATING_CLEAR_MASK

#define TIMER6_CLK_REG_TIMER6_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER6_CLK_REG_TIMER6_CLK_GATING_DISABLE

#define TIMER6_CLK_REG_TIMER6_CLK_GATING_DISABLE 0b0

◆ TIMER6_CLK_REG_TIMER6_CLK_GATING_ENABLE

#define TIMER6_CLK_REG_TIMER6_CLK_GATING_ENABLE 0b1

◆ TIMER6_CLK_REG_TIMER6_CLK_GATING_OFFSET

#define TIMER6_CLK_REG_TIMER6_CLK_GATING_OFFSET 31

◆ TIMER7_CLK_REG

#define TIMER7_CLK_REG 0x0000081c

◆ TIMER7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ TIMER7_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER7_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b001

◆ TIMER7_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER7_CLK_REG_CLK_SRC_SEL_CLK32K 0b010

◆ TIMER7_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER7_CLK_REG_CLK_SRC_SEL_HOSC 0b000

◆ TIMER7_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER7_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TIMER7_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER7_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b011

◆ TIMER7_CLK_REG_FACTOR_M__1

#define TIMER7_CLK_REG_FACTOR_M__1 0b000

◆ TIMER7_CLK_REG_FACTOR_M__128

#define TIMER7_CLK_REG_FACTOR_M__128 0b111

◆ TIMER7_CLK_REG_FACTOR_M__16

#define TIMER7_CLK_REG_FACTOR_M__16 0b100

◆ TIMER7_CLK_REG_FACTOR_M__2

#define TIMER7_CLK_REG_FACTOR_M__2 0b001

◆ TIMER7_CLK_REG_FACTOR_M__32

#define TIMER7_CLK_REG_FACTOR_M__32 0b101

◆ TIMER7_CLK_REG_FACTOR_M__4

#define TIMER7_CLK_REG_FACTOR_M__4 0b010

◆ TIMER7_CLK_REG_FACTOR_M__64

#define TIMER7_CLK_REG_FACTOR_M__64 0b110

◆ TIMER7_CLK_REG_FACTOR_M__8

#define TIMER7_CLK_REG_FACTOR_M__8 0b011

◆ TIMER7_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER7_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007

◆ TIMER7_CLK_REG_FACTOR_M_OFFSET

#define TIMER7_CLK_REG_FACTOR_M_OFFSET 0

◆ TIMER7_CLK_REG_TIMER7_CLK_GATING_CLEAR_MASK

#define TIMER7_CLK_REG_TIMER7_CLK_GATING_CLEAR_MASK 0x80000000

◆ TIMER7_CLK_REG_TIMER7_CLK_GATING_DISABLE

#define TIMER7_CLK_REG_TIMER7_CLK_GATING_DISABLE 0b0

◆ TIMER7_CLK_REG_TIMER7_CLK_GATING_ENABLE

#define TIMER7_CLK_REG_TIMER7_CLK_GATING_ENABLE 0b1

◆ TIMER7_CLK_REG_TIMER7_CLK_GATING_OFFSET

#define TIMER7_CLK_REG_TIMER7_CLK_GATING_OFFSET 31

◆ TIMER_BGR_REG

#define TIMER_BGR_REG 0x00000850

◆ TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK

#define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK 0x00000001

◆ TIMER_BGR_REG_TIMER_GATING_MASK

#define TIMER_BGR_REG_TIMER_GATING_MASK 0b0

◆ TIMER_BGR_REG_TIMER_GATING_OFFSET

#define TIMER_BGR_REG_TIMER_GATING_OFFSET 0

◆ TIMER_BGR_REG_TIMER_GATING_PASS

#define TIMER_BGR_REG_TIMER_GATING_PASS 0b1

◆ TIMER_BGR_REG_TIMER_RST_ASSERT

#define TIMER_BGR_REG_TIMER_RST_ASSERT 0b0

◆ TIMER_BGR_REG_TIMER_RST_CLEAR_MASK

#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK 0x00010000

◆ TIMER_BGR_REG_TIMER_RST_DE_ASSERT

#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT 0b1

◆ TIMER_BGR_REG_TIMER_RST_OFFSET

#define TIMER_BGR_REG_TIMER_RST_OFFSET 16

◆ TIMER_RV_BGR_REG

#define TIMER_RV_BGR_REG 0x00000870

◆ TIMER_RV_BGR_REG_TIMER_RV_GATING_CLEAR_MASK

#define TIMER_RV_BGR_REG_TIMER_RV_GATING_CLEAR_MASK 0x00000001

◆ TIMER_RV_BGR_REG_TIMER_RV_GATING_MASK

#define TIMER_RV_BGR_REG_TIMER_RV_GATING_MASK 0b0

◆ TIMER_RV_BGR_REG_TIMER_RV_GATING_OFFSET

#define TIMER_RV_BGR_REG_TIMER_RV_GATING_OFFSET 0

◆ TIMER_RV_BGR_REG_TIMER_RV_GATING_PASS

#define TIMER_RV_BGR_REG_TIMER_RV_GATING_PASS 0b1

◆ TIMER_RV_BGR_REG_TIMER_RV_RST_ASSERT

#define TIMER_RV_BGR_REG_TIMER_RV_RST_ASSERT 0b0

◆ TIMER_RV_BGR_REG_TIMER_RV_RST_CLEAR_MASK

#define TIMER_RV_BGR_REG_TIMER_RV_RST_CLEAR_MASK 0x00010000

◆ TIMER_RV_BGR_REG_TIMER_RV_RST_DE_ASSERT

#define TIMER_RV_BGR_REG_TIMER_RV_RST_DE_ASSERT 0b1

◆ TIMER_RV_BGR_REG_TIMER_RV_RST_OFFSET

#define TIMER_RV_BGR_REG_TIMER_RV_RST_OFFSET 16

◆ TPADC_24M_CLK_REG

#define TPADC_24M_CLK_REG 0x00001030

◆ TPADC_24M_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X

#define TPADC_24M_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X 0b1

◆ TPADC_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TPADC_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ TPADC_24M_CLK_REG_CLK_SRC_SEL_HOSC

#define TPADC_24M_CLK_REG_CLK_SRC_SEL_HOSC 0b0

◆ TPADC_24M_CLK_REG_CLK_SRC_SEL_OFFSET

#define TPADC_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK

#define TPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ TPADC_24M_CLK_REG_FACTOR_M_OFFSET

#define TPADC_24M_CLK_REG_FACTOR_M_OFFSET 0

◆ TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLEAR_MASK

#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLEAR_MASK 0x80000000

◆ TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_OFF

#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_OFF 0b0

◆ TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_ON

#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_CLOCK_IS_ON 0b1

◆ TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_OFFSET

#define TPADC_24M_CLK_REG_TPADC_24M_CLK_GATING_OFFSET 31

◆ TPADC_BGR_REG

#define TPADC_BGR_REG 0x00001034

◆ TPADC_BGR_REG_TPADC_GATING_CLEAR_MASK

#define TPADC_BGR_REG_TPADC_GATING_CLEAR_MASK 0x00000001

◆ TPADC_BGR_REG_TPADC_GATING_MASK

#define TPADC_BGR_REG_TPADC_GATING_MASK 0b0

◆ TPADC_BGR_REG_TPADC_GATING_OFFSET

#define TPADC_BGR_REG_TPADC_GATING_OFFSET 0

◆ TPADC_BGR_REG_TPADC_GATING_PASS

#define TPADC_BGR_REG_TPADC_GATING_PASS 0b1

◆ TPADC_BGR_REG_TPADC_RST_ASSERT

#define TPADC_BGR_REG_TPADC_RST_ASSERT 0b0

◆ TPADC_BGR_REG_TPADC_RST_CLEAR_MASK

#define TPADC_BGR_REG_TPADC_RST_CLEAR_MASK 0x00010000

◆ TPADC_BGR_REG_TPADC_RST_DE_ASSERT

#define TPADC_BGR_REG_TPADC_RST_DE_ASSERT 0b1

◆ TPADC_BGR_REG_TPADC_RST_OFFSET

#define TPADC_BGR_REG_TPADC_RST_OFFSET 16

◆ TRACE_CLK_REG

#define TRACE_CLK_REG 0x00000540

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0b10

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK32K

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0b01

◆ TRACE_CLK_REG_CLK_SRC_SEL_HOSC

#define TRACE_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ TRACE_CLK_REG_CLK_SRC_SEL_OFFSET

#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ TRACE_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_200M 0b11

◆ TRACE_CLK_REG_FACTOR_M_CLEAR_MASK

#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ TRACE_CLK_REG_FACTOR_M_OFFSET

#define TRACE_CLK_REG_FACTOR_M_OFFSET 0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK 0x80000000

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0b0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0b1

◆ TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET

#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31

◆ TWI0_BGR_REG

#define TWI0_BGR_REG 0x00000e80

◆ TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK

#define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK 0x00000001

◆ TWI0_BGR_REG_TWI0_GATING_MASK

#define TWI0_BGR_REG_TWI0_GATING_MASK 0b0

◆ TWI0_BGR_REG_TWI0_GATING_OFFSET

#define TWI0_BGR_REG_TWI0_GATING_OFFSET 0

◆ TWI0_BGR_REG_TWI0_GATING_PASS

#define TWI0_BGR_REG_TWI0_GATING_PASS 0b1

◆ TWI0_BGR_REG_TWI0_RST_ASSERT

#define TWI0_BGR_REG_TWI0_RST_ASSERT 0b0

◆ TWI0_BGR_REG_TWI0_RST_CLEAR_MASK

#define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK 0x00010000

◆ TWI0_BGR_REG_TWI0_RST_DE_ASSERT

#define TWI0_BGR_REG_TWI0_RST_DE_ASSERT 0b1

◆ TWI0_BGR_REG_TWI0_RST_OFFSET

#define TWI0_BGR_REG_TWI0_RST_OFFSET 16

◆ TWI1_BGR_REG

#define TWI1_BGR_REG 0x00000e84

◆ TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK

#define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK 0x00000001

◆ TWI1_BGR_REG_TWI1_GATING_MASK

#define TWI1_BGR_REG_TWI1_GATING_MASK 0b0

◆ TWI1_BGR_REG_TWI1_GATING_OFFSET

#define TWI1_BGR_REG_TWI1_GATING_OFFSET 0

◆ TWI1_BGR_REG_TWI1_GATING_PASS

#define TWI1_BGR_REG_TWI1_GATING_PASS 0b1

◆ TWI1_BGR_REG_TWI1_RST_ASSERT

#define TWI1_BGR_REG_TWI1_RST_ASSERT 0b0

◆ TWI1_BGR_REG_TWI1_RST_CLEAR_MASK

#define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK 0x00010000

◆ TWI1_BGR_REG_TWI1_RST_DE_ASSERT

#define TWI1_BGR_REG_TWI1_RST_DE_ASSERT 0b1

◆ TWI1_BGR_REG_TWI1_RST_OFFSET

#define TWI1_BGR_REG_TWI1_RST_OFFSET 16

◆ TWI2_BGR_REG

#define TWI2_BGR_REG 0x00000e88

◆ TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK

#define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK 0x00000001

◆ TWI2_BGR_REG_TWI2_GATING_MASK

#define TWI2_BGR_REG_TWI2_GATING_MASK 0b0

◆ TWI2_BGR_REG_TWI2_GATING_OFFSET

#define TWI2_BGR_REG_TWI2_GATING_OFFSET 0

◆ TWI2_BGR_REG_TWI2_GATING_PASS

#define TWI2_BGR_REG_TWI2_GATING_PASS 0b1

◆ TWI2_BGR_REG_TWI2_RST_ASSERT

#define TWI2_BGR_REG_TWI2_RST_ASSERT 0b0

◆ TWI2_BGR_REG_TWI2_RST_CLEAR_MASK

#define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK 0x00010000

◆ TWI2_BGR_REG_TWI2_RST_DE_ASSERT

#define TWI2_BGR_REG_TWI2_RST_DE_ASSERT 0b1

◆ TWI2_BGR_REG_TWI2_RST_OFFSET

#define TWI2_BGR_REG_TWI2_RST_OFFSET 16

◆ TWI3_BGR_REG

#define TWI3_BGR_REG 0x00000e8c

◆ TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK

#define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK 0x00000001

◆ TWI3_BGR_REG_TWI3_GATING_MASK

#define TWI3_BGR_REG_TWI3_GATING_MASK 0b0

◆ TWI3_BGR_REG_TWI3_GATING_OFFSET

#define TWI3_BGR_REG_TWI3_GATING_OFFSET 0

◆ TWI3_BGR_REG_TWI3_GATING_PASS

#define TWI3_BGR_REG_TWI3_GATING_PASS 0b1

◆ TWI3_BGR_REG_TWI3_RST_ASSERT

#define TWI3_BGR_REG_TWI3_RST_ASSERT 0b0

◆ TWI3_BGR_REG_TWI3_RST_CLEAR_MASK

#define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK 0x00010000

◆ TWI3_BGR_REG_TWI3_RST_DE_ASSERT

#define TWI3_BGR_REG_TWI3_RST_DE_ASSERT 0b1

◆ TWI3_BGR_REG_TWI3_RST_OFFSET

#define TWI3_BGR_REG_TWI3_RST_OFFSET 16

◆ TWI4_BGR_REG

#define TWI4_BGR_REG 0x00000e90

◆ TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK

#define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK 0x00000001

◆ TWI4_BGR_REG_TWI4_GATING_MASK

#define TWI4_BGR_REG_TWI4_GATING_MASK 0b0

◆ TWI4_BGR_REG_TWI4_GATING_OFFSET

#define TWI4_BGR_REG_TWI4_GATING_OFFSET 0

◆ TWI4_BGR_REG_TWI4_GATING_PASS

#define TWI4_BGR_REG_TWI4_GATING_PASS 0b1

◆ TWI4_BGR_REG_TWI4_RST_ASSERT

#define TWI4_BGR_REG_TWI4_RST_ASSERT 0b0

◆ TWI4_BGR_REG_TWI4_RST_CLEAR_MASK

#define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK 0x00010000

◆ TWI4_BGR_REG_TWI4_RST_DE_ASSERT

#define TWI4_BGR_REG_TWI4_RST_DE_ASSERT 0b1

◆ TWI4_BGR_REG_TWI4_RST_OFFSET

#define TWI4_BGR_REG_TWI4_RST_OFFSET 16

◆ TWI5_BGR_REG

#define TWI5_BGR_REG 0x00000e94

◆ TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK

#define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK 0x00000001

◆ TWI5_BGR_REG_TWI5_GATING_MASK

#define TWI5_BGR_REG_TWI5_GATING_MASK 0b0

◆ TWI5_BGR_REG_TWI5_GATING_OFFSET

#define TWI5_BGR_REG_TWI5_GATING_OFFSET 0

◆ TWI5_BGR_REG_TWI5_GATING_PASS

#define TWI5_BGR_REG_TWI5_GATING_PASS 0b1

◆ TWI5_BGR_REG_TWI5_RST_ASSERT

#define TWI5_BGR_REG_TWI5_RST_ASSERT 0b0

◆ TWI5_BGR_REG_TWI5_RST_CLEAR_MASK

#define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK 0x00010000

◆ TWI5_BGR_REG_TWI5_RST_DE_ASSERT

#define TWI5_BGR_REG_TWI5_RST_DE_ASSERT 0b1

◆ TWI5_BGR_REG_TWI5_RST_OFFSET

#define TWI5_BGR_REG_TWI5_RST_OFFSET 16

◆ TWI6_BGR_REG

#define TWI6_BGR_REG 0x00000e98

◆ TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK

#define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK 0x00000001

◆ TWI6_BGR_REG_TWI6_GATING_MASK

#define TWI6_BGR_REG_TWI6_GATING_MASK 0b0

◆ TWI6_BGR_REG_TWI6_GATING_OFFSET

#define TWI6_BGR_REG_TWI6_GATING_OFFSET 0

◆ TWI6_BGR_REG_TWI6_GATING_PASS

#define TWI6_BGR_REG_TWI6_GATING_PASS 0b1

◆ TWI6_BGR_REG_TWI6_RST_ASSERT

#define TWI6_BGR_REG_TWI6_RST_ASSERT 0b0

◆ TWI6_BGR_REG_TWI6_RST_CLEAR_MASK

#define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK 0x00010000

◆ TWI6_BGR_REG_TWI6_RST_DE_ASSERT

#define TWI6_BGR_REG_TWI6_RST_DE_ASSERT 0b1

◆ TWI6_BGR_REG_TWI6_RST_OFFSET

#define TWI6_BGR_REG_TWI6_RST_OFFSET 16

◆ UART0_BGR_REG

#define UART0_BGR_REG 0x00000e00

◆ UART0_BGR_REG_UART0_GATING_CLEAR_MASK

#define UART0_BGR_REG_UART0_GATING_CLEAR_MASK 0x00000001

◆ UART0_BGR_REG_UART0_GATING_MASK

#define UART0_BGR_REG_UART0_GATING_MASK 0b0

◆ UART0_BGR_REG_UART0_GATING_OFFSET

#define UART0_BGR_REG_UART0_GATING_OFFSET 0

◆ UART0_BGR_REG_UART0_GATING_PASS

#define UART0_BGR_REG_UART0_GATING_PASS 0b1

◆ UART0_BGR_REG_UART0_RST_ASSERT

#define UART0_BGR_REG_UART0_RST_ASSERT 0b0

◆ UART0_BGR_REG_UART0_RST_CLEAR_MASK

#define UART0_BGR_REG_UART0_RST_CLEAR_MASK 0x00010000

◆ UART0_BGR_REG_UART0_RST_DE_ASSERT

#define UART0_BGR_REG_UART0_RST_DE_ASSERT 0b1

◆ UART0_BGR_REG_UART0_RST_OFFSET

#define UART0_BGR_REG_UART0_RST_OFFSET 16

◆ UART10_BGR_REG

#define UART10_BGR_REG 0x00000e2c

◆ UART10_BGR_REG_UART10_GATING_CLEAR_MASK

#define UART10_BGR_REG_UART10_GATING_CLEAR_MASK 0x00000001

◆ UART10_BGR_REG_UART10_GATING_MASK

#define UART10_BGR_REG_UART10_GATING_MASK 0b0

◆ UART10_BGR_REG_UART10_GATING_OFFSET

#define UART10_BGR_REG_UART10_GATING_OFFSET 0

◆ UART10_BGR_REG_UART10_GATING_PASS

#define UART10_BGR_REG_UART10_GATING_PASS 0b1

◆ UART10_BGR_REG_UART10_RST_ASSERT

#define UART10_BGR_REG_UART10_RST_ASSERT 0b0

◆ UART10_BGR_REG_UART10_RST_CLEAR_MASK

#define UART10_BGR_REG_UART10_RST_CLEAR_MASK 0x00010000

◆ UART10_BGR_REG_UART10_RST_DE_ASSERT

#define UART10_BGR_REG_UART10_RST_DE_ASSERT 0b1

◆ UART10_BGR_REG_UART10_RST_OFFSET

#define UART10_BGR_REG_UART10_RST_OFFSET 16

◆ UART11_BGR_REG

#define UART11_BGR_REG 0x00000e30

◆ UART11_BGR_REG_UART11_GATING_CLEAR_MASK

#define UART11_BGR_REG_UART11_GATING_CLEAR_MASK 0x00000001

◆ UART11_BGR_REG_UART11_GATING_MASK

#define UART11_BGR_REG_UART11_GATING_MASK 0b0

◆ UART11_BGR_REG_UART11_GATING_OFFSET

#define UART11_BGR_REG_UART11_GATING_OFFSET 0

◆ UART11_BGR_REG_UART11_GATING_PASS

#define UART11_BGR_REG_UART11_GATING_PASS 0b1

◆ UART11_BGR_REG_UART11_RST_ASSERT

#define UART11_BGR_REG_UART11_RST_ASSERT 0b0

◆ UART11_BGR_REG_UART11_RST_CLEAR_MASK

#define UART11_BGR_REG_UART11_RST_CLEAR_MASK 0x00010000

◆ UART11_BGR_REG_UART11_RST_DE_ASSERT

#define UART11_BGR_REG_UART11_RST_DE_ASSERT 0b1

◆ UART11_BGR_REG_UART11_RST_OFFSET

#define UART11_BGR_REG_UART11_RST_OFFSET 16

◆ UART12_BGR_REG

#define UART12_BGR_REG 0x00000e34

◆ UART12_BGR_REG_UART12_GATING_CLEAR_MASK

#define UART12_BGR_REG_UART12_GATING_CLEAR_MASK 0x00000001

◆ UART12_BGR_REG_UART12_GATING_MASK

#define UART12_BGR_REG_UART12_GATING_MASK 0b0

◆ UART12_BGR_REG_UART12_GATING_OFFSET

#define UART12_BGR_REG_UART12_GATING_OFFSET 0

◆ UART12_BGR_REG_UART12_GATING_PASS

#define UART12_BGR_REG_UART12_GATING_PASS 0b1

◆ UART12_BGR_REG_UART12_RST_ASSERT

#define UART12_BGR_REG_UART12_RST_ASSERT 0b0

◆ UART12_BGR_REG_UART12_RST_CLEAR_MASK

#define UART12_BGR_REG_UART12_RST_CLEAR_MASK 0x00010000

◆ UART12_BGR_REG_UART12_RST_DE_ASSERT

#define UART12_BGR_REG_UART12_RST_DE_ASSERT 0b1

◆ UART12_BGR_REG_UART12_RST_OFFSET

#define UART12_BGR_REG_UART12_RST_OFFSET 16

◆ UART13_BGR_REG

#define UART13_BGR_REG 0x00000e38

◆ UART13_BGR_REG_UART13_GATING_CLEAR_MASK

#define UART13_BGR_REG_UART13_GATING_CLEAR_MASK 0x00000001

◆ UART13_BGR_REG_UART13_GATING_MASK

#define UART13_BGR_REG_UART13_GATING_MASK 0b0

◆ UART13_BGR_REG_UART13_GATING_OFFSET

#define UART13_BGR_REG_UART13_GATING_OFFSET 0

◆ UART13_BGR_REG_UART13_GATING_PASS

#define UART13_BGR_REG_UART13_GATING_PASS 0b1

◆ UART13_BGR_REG_UART13_RST_ASSERT

#define UART13_BGR_REG_UART13_RST_ASSERT 0b0

◆ UART13_BGR_REG_UART13_RST_CLEAR_MASK

#define UART13_BGR_REG_UART13_RST_CLEAR_MASK 0x00010000

◆ UART13_BGR_REG_UART13_RST_DE_ASSERT

#define UART13_BGR_REG_UART13_RST_DE_ASSERT 0b1

◆ UART13_BGR_REG_UART13_RST_OFFSET

#define UART13_BGR_REG_UART13_RST_OFFSET 16

◆ UART14_BGR_REG

#define UART14_BGR_REG 0x00000e3c

◆ UART14_BGR_REG_UART14_GATING_CLEAR_MASK

#define UART14_BGR_REG_UART14_GATING_CLEAR_MASK 0x00000001

◆ UART14_BGR_REG_UART14_GATING_MASK

#define UART14_BGR_REG_UART14_GATING_MASK 0b0

◆ UART14_BGR_REG_UART14_GATING_OFFSET

#define UART14_BGR_REG_UART14_GATING_OFFSET 0

◆ UART14_BGR_REG_UART14_GATING_PASS

#define UART14_BGR_REG_UART14_GATING_PASS 0b1

◆ UART14_BGR_REG_UART14_RST_ASSERT

#define UART14_BGR_REG_UART14_RST_ASSERT 0b0

◆ UART14_BGR_REG_UART14_RST_CLEAR_MASK

#define UART14_BGR_REG_UART14_RST_CLEAR_MASK 0x00010000

◆ UART14_BGR_REG_UART14_RST_DE_ASSERT

#define UART14_BGR_REG_UART14_RST_DE_ASSERT 0b1

◆ UART14_BGR_REG_UART14_RST_OFFSET

#define UART14_BGR_REG_UART14_RST_OFFSET 16

◆ UART1_BGR_REG

#define UART1_BGR_REG 0x00000e04

◆ UART1_BGR_REG_UART1_GATING_CLEAR_MASK

#define UART1_BGR_REG_UART1_GATING_CLEAR_MASK 0x00000001

◆ UART1_BGR_REG_UART1_GATING_MASK

#define UART1_BGR_REG_UART1_GATING_MASK 0b0

◆ UART1_BGR_REG_UART1_GATING_OFFSET

#define UART1_BGR_REG_UART1_GATING_OFFSET 0

◆ UART1_BGR_REG_UART1_GATING_PASS

#define UART1_BGR_REG_UART1_GATING_PASS 0b1

◆ UART1_BGR_REG_UART1_RST_ASSERT

#define UART1_BGR_REG_UART1_RST_ASSERT 0b0

◆ UART1_BGR_REG_UART1_RST_CLEAR_MASK

#define UART1_BGR_REG_UART1_RST_CLEAR_MASK 0x00010000

◆ UART1_BGR_REG_UART1_RST_DE_ASSERT

#define UART1_BGR_REG_UART1_RST_DE_ASSERT 0b1

◆ UART1_BGR_REG_UART1_RST_OFFSET

#define UART1_BGR_REG_UART1_RST_OFFSET 16

◆ UART2_BGR_REG

#define UART2_BGR_REG 0x00000e08

◆ UART2_BGR_REG_UART2_GATING_CLEAR_MASK

#define UART2_BGR_REG_UART2_GATING_CLEAR_MASK 0x00000001

◆ UART2_BGR_REG_UART2_GATING_MASK

#define UART2_BGR_REG_UART2_GATING_MASK 0b0

◆ UART2_BGR_REG_UART2_GATING_OFFSET

#define UART2_BGR_REG_UART2_GATING_OFFSET 0

◆ UART2_BGR_REG_UART2_GATING_PASS

#define UART2_BGR_REG_UART2_GATING_PASS 0b1

◆ UART2_BGR_REG_UART2_RST_ASSERT

#define UART2_BGR_REG_UART2_RST_ASSERT 0b0

◆ UART2_BGR_REG_UART2_RST_CLEAR_MASK

#define UART2_BGR_REG_UART2_RST_CLEAR_MASK 0x00010000

◆ UART2_BGR_REG_UART2_RST_DE_ASSERT

#define UART2_BGR_REG_UART2_RST_DE_ASSERT 0b1

◆ UART2_BGR_REG_UART2_RST_OFFSET

#define UART2_BGR_REG_UART2_RST_OFFSET 16

◆ UART3_BGR_REG

#define UART3_BGR_REG 0x00000e0c

◆ UART3_BGR_REG_UART3_GATING_CLEAR_MASK

#define UART3_BGR_REG_UART3_GATING_CLEAR_MASK 0x00000001

◆ UART3_BGR_REG_UART3_GATING_MASK

#define UART3_BGR_REG_UART3_GATING_MASK 0b0

◆ UART3_BGR_REG_UART3_GATING_OFFSET

#define UART3_BGR_REG_UART3_GATING_OFFSET 0

◆ UART3_BGR_REG_UART3_GATING_PASS

#define UART3_BGR_REG_UART3_GATING_PASS 0b1

◆ UART3_BGR_REG_UART3_RST_ASSERT

#define UART3_BGR_REG_UART3_RST_ASSERT 0b0

◆ UART3_BGR_REG_UART3_RST_CLEAR_MASK

#define UART3_BGR_REG_UART3_RST_CLEAR_MASK 0x00010000

◆ UART3_BGR_REG_UART3_RST_DE_ASSERT

#define UART3_BGR_REG_UART3_RST_DE_ASSERT 0b1

◆ UART3_BGR_REG_UART3_RST_OFFSET

#define UART3_BGR_REG_UART3_RST_OFFSET 16

◆ UART4_BGR_REG

#define UART4_BGR_REG 0x00000e10

◆ UART4_BGR_REG_UART4_GATING_CLEAR_MASK

#define UART4_BGR_REG_UART4_GATING_CLEAR_MASK 0x00000001

◆ UART4_BGR_REG_UART4_GATING_MASK

#define UART4_BGR_REG_UART4_GATING_MASK 0b0

◆ UART4_BGR_REG_UART4_GATING_OFFSET

#define UART4_BGR_REG_UART4_GATING_OFFSET 0

◆ UART4_BGR_REG_UART4_GATING_PASS

#define UART4_BGR_REG_UART4_GATING_PASS 0b1

◆ UART4_BGR_REG_UART4_RST_ASSERT

#define UART4_BGR_REG_UART4_RST_ASSERT 0b0

◆ UART4_BGR_REG_UART4_RST_CLEAR_MASK

#define UART4_BGR_REG_UART4_RST_CLEAR_MASK 0x00010000

◆ UART4_BGR_REG_UART4_RST_DE_ASSERT

#define UART4_BGR_REG_UART4_RST_DE_ASSERT 0b1

◆ UART4_BGR_REG_UART4_RST_OFFSET

#define UART4_BGR_REG_UART4_RST_OFFSET 16

◆ UART5_BGR_REG

#define UART5_BGR_REG 0x00000e14

◆ UART5_BGR_REG_UART5_GATING_CLEAR_MASK

#define UART5_BGR_REG_UART5_GATING_CLEAR_MASK 0x00000001

◆ UART5_BGR_REG_UART5_GATING_MASK

#define UART5_BGR_REG_UART5_GATING_MASK 0b0

◆ UART5_BGR_REG_UART5_GATING_OFFSET

#define UART5_BGR_REG_UART5_GATING_OFFSET 0

◆ UART5_BGR_REG_UART5_GATING_PASS

#define UART5_BGR_REG_UART5_GATING_PASS 0b1

◆ UART5_BGR_REG_UART5_RST_ASSERT

#define UART5_BGR_REG_UART5_RST_ASSERT 0b0

◆ UART5_BGR_REG_UART5_RST_CLEAR_MASK

#define UART5_BGR_REG_UART5_RST_CLEAR_MASK 0x00010000

◆ UART5_BGR_REG_UART5_RST_DE_ASSERT

#define UART5_BGR_REG_UART5_RST_DE_ASSERT 0b1

◆ UART5_BGR_REG_UART5_RST_OFFSET

#define UART5_BGR_REG_UART5_RST_OFFSET 16

◆ UART6_BGR_REG

#define UART6_BGR_REG 0x00000e18

◆ UART6_BGR_REG_UART6_GATING_CLEAR_MASK

#define UART6_BGR_REG_UART6_GATING_CLEAR_MASK 0x00000001

◆ UART6_BGR_REG_UART6_GATING_MASK

#define UART6_BGR_REG_UART6_GATING_MASK 0b0

◆ UART6_BGR_REG_UART6_GATING_OFFSET

#define UART6_BGR_REG_UART6_GATING_OFFSET 0

◆ UART6_BGR_REG_UART6_GATING_PASS

#define UART6_BGR_REG_UART6_GATING_PASS 0b1

◆ UART6_BGR_REG_UART6_RST_ASSERT

#define UART6_BGR_REG_UART6_RST_ASSERT 0b0

◆ UART6_BGR_REG_UART6_RST_CLEAR_MASK

#define UART6_BGR_REG_UART6_RST_CLEAR_MASK 0x00010000

◆ UART6_BGR_REG_UART6_RST_DE_ASSERT

#define UART6_BGR_REG_UART6_RST_DE_ASSERT 0b1

◆ UART6_BGR_REG_UART6_RST_OFFSET

#define UART6_BGR_REG_UART6_RST_OFFSET 16

◆ UART7_BGR_REG

#define UART7_BGR_REG 0x00000e20

◆ UART7_BGR_REG_UART7_GATING_CLEAR_MASK

#define UART7_BGR_REG_UART7_GATING_CLEAR_MASK 0x00000001

◆ UART7_BGR_REG_UART7_GATING_MASK

#define UART7_BGR_REG_UART7_GATING_MASK 0b0

◆ UART7_BGR_REG_UART7_GATING_OFFSET

#define UART7_BGR_REG_UART7_GATING_OFFSET 0

◆ UART7_BGR_REG_UART7_GATING_PASS

#define UART7_BGR_REG_UART7_GATING_PASS 0b1

◆ UART7_BGR_REG_UART7_RST_ASSERT

#define UART7_BGR_REG_UART7_RST_ASSERT 0b0

◆ UART7_BGR_REG_UART7_RST_CLEAR_MASK

#define UART7_BGR_REG_UART7_RST_CLEAR_MASK 0x00010000

◆ UART7_BGR_REG_UART7_RST_DE_ASSERT

#define UART7_BGR_REG_UART7_RST_DE_ASSERT 0b1

◆ UART7_BGR_REG_UART7_RST_OFFSET

#define UART7_BGR_REG_UART7_RST_OFFSET 16

◆ UART8_BGR_REG

#define UART8_BGR_REG 0x00000e24

◆ UART8_BGR_REG_UART8_GATING_CLEAR_MASK

#define UART8_BGR_REG_UART8_GATING_CLEAR_MASK 0x00000001

◆ UART8_BGR_REG_UART8_GATING_MASK

#define UART8_BGR_REG_UART8_GATING_MASK 0b0

◆ UART8_BGR_REG_UART8_GATING_OFFSET

#define UART8_BGR_REG_UART8_GATING_OFFSET 0

◆ UART8_BGR_REG_UART8_GATING_PASS

#define UART8_BGR_REG_UART8_GATING_PASS 0b1

◆ UART8_BGR_REG_UART8_RST_ASSERT

#define UART8_BGR_REG_UART8_RST_ASSERT 0b0

◆ UART8_BGR_REG_UART8_RST_CLEAR_MASK

#define UART8_BGR_REG_UART8_RST_CLEAR_MASK 0x00010000

◆ UART8_BGR_REG_UART8_RST_DE_ASSERT

#define UART8_BGR_REG_UART8_RST_DE_ASSERT 0b1

◆ UART8_BGR_REG_UART8_RST_OFFSET

#define UART8_BGR_REG_UART8_RST_OFFSET 16

◆ UART9_BGR_REG

#define UART9_BGR_REG 0x00000e28

◆ UART9_BGR_REG_UART9_GATING_CLEAR_MASK

#define UART9_BGR_REG_UART9_GATING_CLEAR_MASK 0x00000001

◆ UART9_BGR_REG_UART9_GATING_MASK

#define UART9_BGR_REG_UART9_GATING_MASK 0b0

◆ UART9_BGR_REG_UART9_GATING_OFFSET

#define UART9_BGR_REG_UART9_GATING_OFFSET 0

◆ UART9_BGR_REG_UART9_GATING_PASS

#define UART9_BGR_REG_UART9_GATING_PASS 0b1

◆ UART9_BGR_REG_UART9_RST_ASSERT

#define UART9_BGR_REG_UART9_RST_ASSERT 0b0

◆ UART9_BGR_REG_UART9_RST_CLEAR_MASK

#define UART9_BGR_REG_UART9_RST_CLEAR_MASK 0x00010000

◆ UART9_BGR_REG_UART9_RST_DE_ASSERT

#define UART9_BGR_REG_UART9_RST_DE_ASSERT 0b1

◆ UART9_BGR_REG_UART9_RST_OFFSET

#define UART9_BGR_REG_UART9_RST_OFFSET 16

◆ USB0_BGR_REG

#define USB0_BGR_REG 0x00001304

◆ USB0_BGR_REG_USB20_0_DEVICE_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_DEVICE_GATING_CLEAR_MASK 0x00000100

◆ USB0_BGR_REG_USB20_0_DEVICE_GATING_MASK

#define USB0_BGR_REG_USB20_0_DEVICE_GATING_MASK 0b0

◆ USB0_BGR_REG_USB20_0_DEVICE_GATING_OFFSET

#define USB0_BGR_REG_USB20_0_DEVICE_GATING_OFFSET 8

◆ USB0_BGR_REG_USB20_0_DEVICE_GATING_PASS

#define USB0_BGR_REG_USB20_0_DEVICE_GATING_PASS 0b1

◆ USB0_BGR_REG_USB20_0_DEVICE_RST_ASSERT

#define USB0_BGR_REG_USB20_0_DEVICE_RST_ASSERT 0b0

◆ USB0_BGR_REG_USB20_0_DEVICE_RST_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_DEVICE_RST_CLEAR_MASK 0x01000000

◆ USB0_BGR_REG_USB20_0_DEVICE_RST_DE_ASSERT

#define USB0_BGR_REG_USB20_0_DEVICE_RST_DE_ASSERT 0b1

◆ USB0_BGR_REG_USB20_0_DEVICE_RST_OFFSET

#define USB0_BGR_REG_USB20_0_DEVICE_RST_OFFSET 24

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_CLEAR_MASK 0x00000010

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_MASK

#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_MASK 0b0

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_OFFSET

#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_OFFSET 4

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_PASS

#define USB0_BGR_REG_USB20_0_HOST_EHCI_GATING_PASS 0b1

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_RST_ASSERT

#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_ASSERT 0b0

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_RST_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_CLEAR_MASK 0x00100000

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_RST_DE_ASSERT

#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_DE_ASSERT 0b1

◆ USB0_BGR_REG_USB20_0_HOST_EHCI_RST_OFFSET

#define USB0_BGR_REG_USB20_0_HOST_EHCI_RST_OFFSET 20

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_CLEAR_MASK 0x00000001

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_MASK

#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_MASK 0b0

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_OFFSET

#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_OFFSET 0

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_PASS

#define USB0_BGR_REG_USB20_0_HOST_OHCI_GATING_PASS 0b1

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_RST_ASSERT

#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_ASSERT 0b0

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_RST_CLEAR_MASK

#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_CLEAR_MASK 0x00010000

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_RST_DE_ASSERT

#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_DE_ASSERT 0b1

◆ USB0_BGR_REG_USB20_0_HOST_OHCI_RST_OFFSET

#define USB0_BGR_REG_USB20_0_HOST_OHCI_RST_OFFSET 16

◆ USB0_CLK_REG

#define USB0_CLK_REG 0x00001300

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_HOSC

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC 0b11

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK32K 0b10

◆ USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24

◆ USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0b0

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0b1

◆ USB0_CLK_REG_USB0_CLKEN_OFFSET

#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31

◆ USB0_CLK_REG_USBPHY0_RSTN_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT 0b0

◆ USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK

#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK 0x40000000

◆ USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT 0b1

◆ USB0_CLK_REG_USBPHY0_RSTN_OFFSET

#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET 30

◆ USB1_BGR_REG

#define USB1_BGR_REG 0x0000130c

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_CLEAR_MASK

#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_CLEAR_MASK 0x00000010

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_MASK

#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_MASK 0b0

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_OFFSET

#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_OFFSET 4

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_PASS

#define USB1_BGR_REG_USB20_1_HOST_EHCI_GATING_PASS 0b1

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_RST_ASSERT

#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_ASSERT 0b0

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_RST_CLEAR_MASK

#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_CLEAR_MASK 0x00100000

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_RST_DE_ASSERT

#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_DE_ASSERT 0b1

◆ USB1_BGR_REG_USB20_1_HOST_EHCI_RST_OFFSET

#define USB1_BGR_REG_USB20_1_HOST_EHCI_RST_OFFSET 20

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_CLEAR_MASK

#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_CLEAR_MASK 0x00000001

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_MASK

#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_MASK 0b0

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_OFFSET

#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_OFFSET 0

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_PASS

#define USB1_BGR_REG_USB20_1_HOST_OHCI_GATING_PASS 0b1

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_RST_ASSERT

#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_ASSERT 0b0

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_RST_CLEAR_MASK

#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_CLEAR_MASK 0x00010000

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_RST_DE_ASSERT

#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_DE_ASSERT 0b1

◆ USB1_BGR_REG_USB20_1_HOST_OHCI_RST_OFFSET

#define USB1_BGR_REG_USB20_1_HOST_OHCI_RST_OFFSET 16

◆ USB1_CLK_REG

#define USB1_CLK_REG 0x00001308

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0b00

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_HOSC

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_HOSC 0b01

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK16M_RC 0b11

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLK32K 0b10

◆ USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET

#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24

◆ USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0b0

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0b1

◆ USB1_CLK_REG_USB1_CLKEN_OFFSET

#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31

◆ USB1_CLK_REG_USBPHY1_RSTN_ASSERT

#define USB1_CLK_REG_USBPHY1_RSTN_ASSERT 0b0

◆ USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK

#define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK 0x40000000

◆ USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT

#define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT 0b1

◆ USB1_CLK_REG_USBPHY1_RSTN_OFFSET

#define USB1_CLK_REG_USBPHY1_RSTN_OFFSET 30

◆ USB2_BGR_REG

#define USB2_BGR_REG 0x0000135c

◆ USB2_BGR_REG_USB30_GATING_CLEAR_MASK

#define USB2_BGR_REG_USB30_GATING_CLEAR_MASK 0x00000001

◆ USB2_BGR_REG_USB30_GATING_MASK

#define USB2_BGR_REG_USB30_GATING_MASK 0b0

◆ USB2_BGR_REG_USB30_GATING_OFFSET

#define USB2_BGR_REG_USB30_GATING_OFFSET 0

◆ USB2_BGR_REG_USB30_GATING_PASS

#define USB2_BGR_REG_USB30_GATING_PASS 0b1

◆ USB2_BGR_REG_USB30_RST_ASSERT

#define USB2_BGR_REG_USB30_RST_ASSERT 0b0

◆ USB2_BGR_REG_USB30_RST_CLEAR_MASK

#define USB2_BGR_REG_USB30_RST_CLEAR_MASK 0x00010000

◆ USB2_BGR_REG_USB30_RST_DE_ASSERT

#define USB2_BGR_REG_USB30_RST_DE_ASSERT 0b1

◆ USB2_BGR_REG_USB30_RST_OFFSET

#define USB2_BGR_REG_USB30_RST_OFFSET 16

◆ USB2_MF_CLK_REG

#define USB2_MF_CLK_REG 0x00001354

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_MF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_MF_CLK_REG_CLK_SRC_SEL_HOSC 0b00

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_MF_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b01

◆ USB2_MF_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define USB2_MF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0b10

◆ USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_MF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ USB2_MF_CLK_REG_FACTOR_M_OFFSET

#define USB2_MF_CLK_REG_FACTOR_M_OFFSET 0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLEAR_MASK 0x80000000

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_OFF 0b0

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_CLOCK_IS_ON 0b1

◆ USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET

#define USB2_MF_CLK_REG_USB2_MF_CLK_GATING_OFFSET 31

◆ USB2_SUSPEND_CLK_REG

#define USB2_SUSPEND_CLK_REG 0x00001350

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K 0b0

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_HOSC

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_HOSC 0b1

◆ USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET

#define USB2_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET

#define USB2_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0b0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0b1

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31

◆ USB2_U2_REF_CLK_REG

#define USB2_U2_REF_CLK_REG 0x00001348

◆ USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK

#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK 0x80000000

◆ USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF

#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF 0b0

◆ USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON

#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON 0b1

◆ USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET

#define USB2_U2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31

◆ VE_BGR_REG

#define VE_BGR_REG 0x00000a8c

◆ VE_BGR_REG_VE_GATING_CLEAR_MASK

#define VE_BGR_REG_VE_GATING_CLEAR_MASK 0x00000001

◆ VE_BGR_REG_VE_GATING_MASK

#define VE_BGR_REG_VE_GATING_MASK 0b0

◆ VE_BGR_REG_VE_GATING_OFFSET

#define VE_BGR_REG_VE_GATING_OFFSET 0

◆ VE_BGR_REG_VE_GATING_PASS

#define VE_BGR_REG_VE_GATING_PASS 0b1

◆ VE_BGR_REG_VE_RST_ASSERT

#define VE_BGR_REG_VE_RST_ASSERT 0b0

◆ VE_BGR_REG_VE_RST_CLEAR_MASK

#define VE_BGR_REG_VE_RST_CLEAR_MASK 0x00010000

◆ VE_BGR_REG_VE_RST_DE_ASSERT

#define VE_BGR_REG_VE_RST_DE_ASSERT 0b1

◆ VE_BGR_REG_VE_RST_OFFSET

#define VE_BGR_REG_VE_RST_OFFSET 16

◆ VE_CLK_REG

#define VE_CLK_REG 0x00000a80

◆ VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ VE_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b011

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b010

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b001

◆ VE_CLK_REG_CLK_SRC_SEL_VEPLL

#define VE_CLK_REG_CLK_SRC_SEL_VEPLL 0b000

◆ VE_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ VE_CLK_REG_FACTOR_M_OFFSET

#define VE_CLK_REG_FACTOR_M_OFFSET 0

◆ VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK

#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK 0x80000000

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF 0b0

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON 0b1

◆ VE_CLK_REG_VE_CLK_GATING_OFFSET

#define VE_CLK_REG_VE_CLK_GATING_OFFSET 31

◆ VIDEO_OUT0_BGR_REG

#define VIDEO_OUT0_BGR_REG 0x000016e4

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT 0b0

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK 0x00010000

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT 0b1

◆ VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET

#define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16

◆ VIDEOPLL_GATE_EN_REG

#define VIDEOPLL_GATE_EN_REG 0x00001910

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_AUTO 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_CLEAR_MASK 0x00000010

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_NO_AUTO 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_AUTO_GATE_EN_OFFSET 4

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_CLEAR_MASK 0x00100000

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_DISABLE 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_ENABLE 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL1X_GATE_SW_CFG_OFFSET 20

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000001

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00010000

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK 0x00000020

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK 0x00200000

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK 0x00000002

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK 0x00020000

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE 0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE 0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17

◆ VIDEOPLL_GATE_STAT_REG

#define VIDEOPLL_GATE_STAT_REG 0x00001998

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_CLEAR_MASK 0x00000001

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_DISABLE 0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_ENABLE 0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_1X_GATE_STAT_OFFSET 0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_CLEAR_MASK 0x00000002

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_DISABLE 0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_ENABLE 0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL_4X_GATE_STAT_OFFSET 1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_CLEAR_MASK 0x00010000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_DISABLE 0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_ENABLE 0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_3X_GATE_STAT_OFFSET 16

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_CLEAR_MASK 0x00020000

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_DISABLE 0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_ENABLE 0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL_4X_GATE_STAT_OFFSET 17

◆ VO0_COMBPHY0_CLK_REG

#define VO0_COMBPHY0_CLK_REG 0x000015c0

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b100

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL1X 0b010

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b000

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X 0b011

◆ VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b001

◆ VO0_COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ VO0_COMBPHY0_CLK_REG_FACTOR_M_OFFSET

#define VO0_COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0

◆ VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLEAR_MASK

#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLEAR_MASK 0x80000000

◆ VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_OFF

#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_ON

#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0b1

◆ VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_OFFSET

#define VO0_COMBPHY0_CLK_REG_VO0_COMBPHY0_CLK_GATING_OFFSET 31

◆ VO0_TCONLCD0_BGR_REG

#define VO0_TCONLCD0_BGR_REG 0x00001504

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK 0x00000001

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK 0b0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS 0b1

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0b0

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK 0x00010000

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0b1

◆ VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET

#define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16

◆ VO0_TCONLCD0_CLK_REG

#define VO0_TCONLCD0_CLK_REG 0x00001500

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0b000

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0b001

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0b010

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0b0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0b1

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31

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