SyterKit 0.4.0.x
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Macros
reg-ccu.h File Reference
#include <reg-ncat.h>
Include dependency graph for reg-ccu.h:

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Macros

#define PLL_CPU_CTRL_REG   0x00000000
 
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_OFFSET   31
 
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_DISABLE   0b0
 
#define PLL_CPU_CTRL_REG_PLL_PLL_EN_ENABLE   0b1
 
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_CPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CPU_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_CPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_CPU_CTRL_REG_PLL_UPDATE_OFFSET   26
 
#define PLL_CPU_CTRL_REG_PLL_UPDATE_CLEAR_MASK   0x04000000
 
#define PLL_CPU_CTRL_REG_PLL_M0_OFFSET   20
 
#define PLL_CPU_CTRL_REG_PLL_M0_CLEAR_MASK   0x00300000
 
#define PLL_CPU_CTRL_REG_PLL_P_OFFSET   16
 
#define PLL_CPU_CTRL_REG_PLL_P_CLEAR_MASK   0x00070000
 
#define PLL_CPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_CPU_CTRL_REG_PLL_M1_OFFSET   0
 
#define PLL_CPU_CTRL_REG_PLL_M1_CLEAR_MASK   0x0000000f
 
#define PLL_CPU_CTRL1_REG   0x00000004
 
#define PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_OFFSET   8
 
#define PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_CLEAR_MASK   0x0000ff00
 
#define PLL_DDR_CTRL_REG   0x00000010
 
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_PERI_CTRL_REG   0x00000020
 
#define PLL_PERI_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_PERI_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_PERI_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_PERI_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_PERI_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_PERI_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_PERI_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_PERI_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_PERI_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_PERI_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_PERI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_PERI_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_PERI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_PERI_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_PERI_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_PERI_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_PERI_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_PERI_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_PERI_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_PERI_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_PERI_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO_CTRL_REG   0x00000040
 
#define PLL_VIDEO_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_VIDEO_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_VIDEO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_VIDEO_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_CSI_CTRL_REG   0x00000048
 
#define PLL_CSI_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CSI_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CSI_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_CSI_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_CSI_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CSI_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CSI_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_CSI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_OFFSET   8
 
#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_AUDIO_CTRL_REG   0x00000078
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_AUDIO_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_AUDIO_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_AUDIO_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_AUDIO_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_OFFSET   8
 
#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK   0x0000ff00
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_AUDIO_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_AUDIO_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_NPU_CTRL_REG   0x00000080
 
#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0b0
 
#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE   0b0
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE   0b1
 
#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_CPU_PAT0_CTRL_REG   0x00000100
 
#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_SDM   0b00
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_1_8_BIT   0b01
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_2_8_BIT   0b10
 
#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_3_8_BIT   0b11
 
#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   17
 
#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ffe0000
 
#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_CPU_PAT1_CTRL_REG   0x00000104
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_OFFSET   22
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_CLEAR_MASK   0xffc00000
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_OFFSET   20
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   0x00100000
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_UP   0b0
 
#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_DOWM   0b1
 
#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   18
 
#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x00040000
 
#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   17
 
#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00020000
 
#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_DDR_PAT0_CTRL_REG   0x00000110
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_DDR_PAT1_CTRL_REG   0x00000114
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI_PAT0_CTRL_REG   0x00000120
 
#define PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_PERI_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI_PAT1_CTRL_REG   0x00000124
 
#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO_PAT0_CTRL_REG   0x00000140
 
#define PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO_PAT1_CTRL_REG   0x00000144
 
#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_CSI_PAT0_CTRL_REG   0x00000148
 
#define PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_CSI_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_CSI_PAT1_CTRL_REG   0x0000014c
 
#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO_PAT0_CTRL_REG   0x00000178
 
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO_PAT1_CTRL_REG   0x0000017c
 
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_NPU_PAT0_CTRL_REG   0x00000180
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_NPU_PAT1_CTRL_REG   0x00000184
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_CPU_SSC_REG   0x00000200
 
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_OFFSET   31
 
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CLEAR_MASK   0x80000000
 
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_NORMAL_MODE   0b0
 
#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CONTINUOUSLY_FREQUENCY_SCALE   0b1
 
#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_OFFSET   30
 
#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_CLEAR_MASK   0x40000000
 
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_OFFSET   29
 
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_CLEAR_MASK   0x20000000
 
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_PLL_CLK_SDM   0b0
 
#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_REF_CLK   0b1
 
#define PLL_CPU_SSC_REG_PLL_SSC_OFFSET   12
 
#define PLL_CPU_SSC_REG_PLL_SSC_CLEAR_MASK   0x1ffff000
 
#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_OFFSET   4
 
#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_CLEAR_MASK   0x00000070
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_OFFSET   0
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_CLEAR_MASK   0x0000000f
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00439MHZ_US_576_2_17   0b0000
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00879MHZ_US_576_2_16   0b0001
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_01758MHZ_US_576_2_15   0b0010
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_03516MHZ_US_576_2_14   0b0011
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_07031MHZ_US_576_2_13   0b0100
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_14062MHZ_US_576_2_12   0b0101
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_28125MHZ_US_576_2_11   0b0110
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_56250MHZ_US_576_2_10   0b0111
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_1_12500MHZ_US_576_2_9   0b1000
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_2_25000MHZ_US_576_2_8   0b1001
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_4_50000MHZ_US_576_2_7   0b1010
 
#define PLL_CPU_SSC_REG_PLL_SSC_STEP_9_00000MHZ_US_576_2_6   0b1011
 
#define PLL_CPU_BIAS_REG   0x00000300
 
#define PLL_CPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_CPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_DDR_BIAS_REG   0x00000310
 
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_PERI_BIAS_REG   0x00000320
 
#define PLL_PERI_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO_BIAS_REG   0x00000340
 
#define PLL_VIDEO_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_CSI_BIAS_REG   0x00000348
 
#define PLL_CSI_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_CSI_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_AUDIO_BIAS_REG   0x00000378
 
#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_NPU_BIAS_REG   0x00000380
 
#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_CPU_TUN1_REG   0x00000400
 
#define PLL_CPU_TUN1_REG_PLL_SDM_EN_OFFSET   31
 
#define PLL_CPU_TUN1_REG_PLL_SDM_EN_CLEAR_MASK   0x80000000
 
#define IPMC_CLK_REG   0x000004fc
 
#define IPMC_CLK_REG_IPMC_CLK_GATING_OFFSET   31
 
#define IPMC_CLK_REG_IPMC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define IPMC_CLK_REG_FACTOR_M_OFFSET   0
 
#define IPMC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CPU_CLK_REG   0x00000500
 
#define CPU_CLK_REG_CPU_CLK_SEL_OFFSET   24
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK   0x07000000
 
#define CPU_CLK_REG_CPU_CLK_SEL_HOSC   0b000
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLK32K   0b001
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC   0b010
 
#define CPU_CLK_REG_CPU_CLK_SEL_CPUPLL_P   0b011
 
#define CPU_CLK_REG_CPU_CLK_SEL_PERI_600M_BUS   0b100
 
#define CPU_CLK_REG_CPU_CLK_SEL_PERI_800M   0b101
 
#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_OFFSET   16
 
#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_CLEAR_MASK   0x00030000
 
#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_1   0b00
 
#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_2   0b01
 
#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_4   0b10
 
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET   8
 
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK   0x00000300
 
#define CPU_GATING_REG   0x00000504
 
#define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET   16
 
#define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK   0xffff0000
 
#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_OFFSET   12
 
#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_CLEAR_MASK   0x00001000
 
#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_ASSERT   0b0
 
#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_DE_ASSERT   0b1
 
#define CPU_GATING_REG_H_RESET_OFFSET   8
 
#define CPU_GATING_REG_H_RESET_CLEAR_MASK   0x00000100
 
#define CPU_GATING_REG_C1_CPUX_RESET_OFFSET   5
 
#define CPU_GATING_REG_C1_CPUX_RESET_CLEAR_MASK   0x00000020
 
#define CPU_GATING_REG_C1_CPUX_RESET_ASSERT   0b0
 
#define CPU_GATING_REG_C1_CPUX_RESET_DE_ASSERT   0b1
 
#define CPU_GATING_REG_C0_CPUX_RESET_OFFSET   4
 
#define CPU_GATING_REG_C0_CPUX_RESET_CLEAR_MASK   0x00000010
 
#define CPU_GATING_REG_C0_CPUX_RESET_ASSERT   0b0
 
#define CPU_GATING_REG_C0_CPUX_RESET_DE_ASSERT   0b1
 
#define CPU_GATING_REG_PIC_SOFT_RSTN_OFFSET   3
 
#define CPU_GATING_REG_PIC_SOFT_RSTN_CLEAR_MASK   0x00000008
 
#define CPU_GATING_REG_PIC_SOFT_RSTN_ASSERT   0b0
 
#define CPU_GATING_REG_PIC_SOFT_RSTN_DE_ASSERT   0b1
 
#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_OFFSET   2
 
#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_CLEAR_MASK   0x00000004
 
#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_ASSERT   0b0
 
#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_DE_ASSERT   0b1
 
#define CPU_GATING_REG_CPU_SOFT_RSTN_OFFSET   1
 
#define CPU_GATING_REG_CPU_SOFT_RSTN_CLEAR_MASK   0x00000002
 
#define CPU_GATING_REG_CPU_SOFT_RSTN_ASSERT   0b0
 
#define CPU_GATING_REG_CPU_SOFT_RSTN_DE_ASSERT   0b1
 
#define CPU_GATING_REG_CPU_CLK_GATING_OFFSET   0
 
#define CPU_GATING_REG_CPU_CLK_GATING_CLEAR_MASK   0x00000001
 
#define CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PIC_CLK_REG   0x00000508
 
#define PIC_CLK_REG_PIC_CLK_GATING_OFFSET   31
 
#define PIC_CLK_REG_PIC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define PIC_CLK_REG_CLK_SRC_SEL_PERI_200M   0b0
 
#define PIC_CLK_REG_CLK_SRC_SEL_PERI_400M   0b1
 
#define CPU_CFG_BGR_REG   0x0000050c
 
#define CPU_CFG_BGR_REG_CPU_CFG_RST_OFFSET   16
 
#define CPU_CFG_BGR_REG_CPU_CFG_RST_CLEAR_MASK   0x00010000
 
#define CPU_CFG_BGR_REG_CPU_CFG_RST_ASSERT   0b0
 
#define CPU_CFG_BGR_REG_CPU_CFG_RST_DE_ASSERT   0b1
 
#define CPU_CFG_BGR_REG_CPU_CFG_GATING_OFFSET   0
 
#define CPU_CFG_BGR_REG_CPU_CFG_GATING_CLEAR_MASK   0x00000001
 
#define CPU_CFG_BGR_REG_CPU_CFG_GATING_MASK   0b0
 
#define CPU_CFG_BGR_REG_CPU_CFG_GATING_PASS   0b1
 
#define AHB_CLK_REG   0x00000510
 
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define AHB_CLK_REG_CLK_SRC_SEL_HOSC   0b00
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define AHB_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11
 
#define AHB_CLK_REG_FACTOR_N_OFFSET   8
 
#define AHB_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define AHB_CLK_REG_FACTOR_N_1   0b00
 
#define AHB_CLK_REG_FACTOR_N_2   0b01
 
#define AHB_CLK_REG_FACTOR_N_4   0b10
 
#define AHB_CLK_REG_FACTOR_N_8   0b11
 
#define AHB_CLK_REG_FACTOR_M_OFFSET   0
 
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB0_CLK_REG   0x00000520
 
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB0_CLK_REG_CLK_SRC_SEL_HOSC   0b00
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define APB0_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11
 
#define APB0_CLK_REG_FACTOR_N_OFFSET   8
 
#define APB0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define APB0_CLK_REG_FACTOR_N_1   0b00
 
#define APB0_CLK_REG_FACTOR_N_2   0b01
 
#define APB0_CLK_REG_FACTOR_N_4   0b10
 
#define APB0_CLK_REG_FACTOR_N_8   0b11
 
#define APB0_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB1_CLK_REG   0x00000524
 
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB1_CLK_REG_CLK_SRC_SEL_HOSC   0b00
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0b01
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10
 
#define APB1_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11
 
#define APB1_CLK_REG_FACTOR_N_OFFSET   8
 
#define APB1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define APB1_CLK_REG_FACTOR_N_1   0b00
 
#define APB1_CLK_REG_FACTOR_N_2   0b01
 
#define APB1_CLK_REG_FACTOR_N_4   0b10
 
#define APB1_CLK_REG_FACTOR_N_8   0b11
 
#define APB1_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB_UART_CLK_REG   0x00000528
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K   0b001
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b011
 
#define APB_UART_CLK_REG_CLK_SRC_SEL_AUDIO_CKO_DIV2   0b100
 
#define APB_UART_CLK_REG_FACTOR_N_OFFSET   8
 
#define APB_UART_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define APB_UART_CLK_REG_FACTOR_N_1   0b00
 
#define APB_UART_CLK_REG_FACTOR_N_2   0b01
 
#define APB_UART_CLK_REG_FACTOR_N_4   0b10
 
#define APB_UART_CLK_REG_FACTOR_N_8   0b11
 
#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define MBUS_CLK_REG   0x00000540
 
#define MBUS_CLK_REG_MBUS_RST_OFFSET   30
 
#define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK   0x40000000
 
#define MBUS_CLK_REG_MBUS_RST_ASSERT   0b0
 
#define MBUS_CLK_REG_MBUS_RST_DE_ASSERT   0b1
 
#define DE_CLK_REG   0x00000600
 
#define DE_CLK_REG_DE_CLK_GATING_OFFSET   31
 
#define DE_CLK_REG_DE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define DE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b0
 
#define DE_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X   0b1
 
#define DE_CLK_REG_FACTOR_M_OFFSET   0
 
#define DE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DE_BGR_REG   0x0000060c
 
#define DE_BGR_REG_DE_RST_OFFSET   16
 
#define DE_BGR_REG_DE_RST_CLEAR_MASK   0x00010000
 
#define DE_BGR_REG_DE_RST_ASSERT   0b0
 
#define DE_BGR_REG_DE_RST_DE_ASSERT   0b1
 
#define DE_BGR_REG_DE_GATING_OFFSET   0
 
#define DE_BGR_REG_DE_GATING_CLEAR_MASK   0x00000001
 
#define DE_BGR_REG_DE_GATING_MASK   0b0
 
#define DE_BGR_REG_DE_GATING_PASS   0b1
 
#define G2D_CLK_REG   0x00000630
 
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1
 
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI_300M   0b0
 
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X   0b1
 
#define G2D_CLK_REG_FACTOR_M_OFFSET   0
 
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define G2D_BGR_REG   0x0000063c
 
#define G2D_BGR_REG_G2D_RST_OFFSET   16
 
#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   0x00010000
 
#define G2D_BGR_REG_G2D_RST_ASSERT   0b0
 
#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0b1
 
#define G2D_BGR_REG_G2D_GATING_OFFSET   0
 
#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   0x00000001
 
#define G2D_BGR_REG_G2D_GATING_MASK   0b0
 
#define G2D_BGR_REG_G2D_GATING_PASS   0b1
 
#define CE_CLK_REG   0x00000680
 
#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31
 
#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CE_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010
 
#define CE_CLK_REG_FACTOR_M_OFFSET   0
 
#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define CE_BGR_REG   0x0000068c
 
#define CE_BGR_REG_CE_SYS_RST_OFFSET   17
 
#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   0x00020000
 
#define CE_BGR_REG_CE_SYS_RST_ASSERT   0b0
 
#define CE_BGR_REG_CE_SYS_RST_DE_ASSERT   0b1
 
#define CE_BGR_REG_CE_RST_OFFSET   16
 
#define CE_BGR_REG_CE_RST_CLEAR_MASK   0x00010000
 
#define CE_BGR_REG_CE_RST_ASSERT   0b0
 
#define CE_BGR_REG_CE_RST_DE_ASSERT   0b1
 
#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1
 
#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   0x00000002
 
#define CE_BGR_REG_CE_SYS_GATING_MASK   0b0
 
#define CE_BGR_REG_CE_SYS_GATING_PASS   0b1
 
#define CE_BGR_REG_CE_GATING_OFFSET   0
 
#define CE_BGR_REG_CE_GATING_CLEAR_MASK   0x00000001
 
#define CE_BGR_REG_CE_GATING_MASK   0b0
 
#define CE_BGR_REG_CE_GATING_PASS   0b1
 
#define VE_CLK_REG   0x00000690
 
#define VE_CLK_REG_VE_CLK_GATING_OFFSET   31
 
#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON   0b1
 
#define VE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b000
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI_480M   0b010
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI_600M   0b011
 
#define VE_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b100
 
#define VE_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b101
 
#define VE_CLK_REG_CLK_SRC_SEL_AUDIOPLL_DIV3   0b110
 
#define VE_CLK_REG_FACTOR_M_OFFSET   0
 
#define VE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VE_BGR_REG   0x0000069c
 
#define VE_BGR_REG_VE_RST_OFFSET   16
 
#define VE_BGR_REG_VE_RST_CLEAR_MASK   0x00010000
 
#define VE_BGR_REG_VE_RST_ASSERT   0b0
 
#define VE_BGR_REG_VE_RST_DE_ASSERT   0b1
 
#define VE_BGR_REG_VE_GATING_OFFSET   0
 
#define VE_BGR_REG_VE_GATING_CLEAR_MASK   0x00000001
 
#define VE_BGR_REG_VE_GATING_MASK   0b0
 
#define VE_BGR_REG_VE_GATING_PASS   0b1
 
#define NPU_CLK_REG   0x000006e0
 
#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   0x80000000
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0b1
 
#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI_800M   0b00
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI_600M   0b01
 
#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X   0b10
 
#define NPU_CLK_REG_FACTOR_M_OFFSET   0
 
#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define NPU_GATING_REG   0x000006e4
 
#define NPU_GATING_REG_NPU_SW_RESET_CFG_OFFSET   8
 
#define NPU_GATING_REG_NPU_SW_RESET_CFG_CLEAR_MASK   0x00000100
 
#define NPU_GATING_REG_NPU_SW_RESET_CFG_DE_ASSERT   0b0
 
#define NPU_GATING_REG_NPU_SW_RESET_CFG_ASSERT   0b1
 
#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_OFFSET   4
 
#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_CLEAR_MASK   0x00000010
 
#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_RELEASE   0b0
 
#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_BYPASS   0b1
 
#define NPU_BGR_REG   0x000006ec
 
#define NPU_BGR_REG_NPU_RST_OFFSET   16
 
#define NPU_BGR_REG_NPU_RST_CLEAR_MASK   0x00010000
 
#define NPU_BGR_REG_NPU_RST_ASSERT   0b0
 
#define NPU_BGR_REG_NPU_RST_DE_ASSERT   0b1
 
#define NPU_BGR_REG_NPU_GATING_OFFSET   0
 
#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK   0x00000001
 
#define NPU_BGR_REG_NPU_GATING_MASK   0b0
 
#define NPU_BGR_REG_NPU_GATING_PASS   0b1
 
#define DMA_BGR_REG   0x0000070c
 
#define DMA_BGR_REG_NDMA_RST_OFFSET   17
 
#define DMA_BGR_REG_NDMA_RST_CLEAR_MASK   0x00020000
 
#define DMA_BGR_REG_NDMA_RST_ASSERT   0b0
 
#define DMA_BGR_REG_NDMA_RST_DE_ASSERT   0b1
 
#define DMA_BGR_REG_SGDMA_RST_OFFSET   16
 
#define DMA_BGR_REG_SGDMA_RST_CLEAR_MASK   0x00010000
 
#define DMA_BGR_REG_SGDMA_RST_ASSERT   0b0
 
#define DMA_BGR_REG_SGDMA_RST_DE_ASSERT   0b1
 
#define DMA_BGR_REG_NDMA_GATING_OFFSET   1
 
#define DMA_BGR_REG_NDMA_GATING_CLEAR_MASK   0x00000002
 
#define DMA_BGR_REG_NDMA_GATING_MASK   0b0
 
#define DMA_BGR_REG_NDMA_GATING_PASS   0b1
 
#define DMA_BGR_REG_SGDMA_GATING_OFFSET   0
 
#define DMA_BGR_REG_SGDMA_GATING_CLEAR_MASK   0x00000001
 
#define DMA_BGR_REG_SGDMA_GATING_MASK   0b0
 
#define DMA_BGR_REG_SGDMA_GATING_PASS   0b1
 
#define MSGBOX_BGR_REG   0x0000071c
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET   17
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK   0x00020000
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT   0b0
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT   0b1
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET   16
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK   0x00010000
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT   0b0
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT   0b1
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET   1
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK   0x00000002
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK   0b0
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS   0b1
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET   0
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   0x00000001
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK   0b0
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS   0b1
 
#define SPINLOCK_BGR_REG   0x0000072c
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   0x00010000
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0b0
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0b1
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   0x00000001
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0b0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0b1
 
#define HSTIMER_BGR_REG   0x0000073c
 
#define HSTIMER_BGR_REG_HSTIMER_RST_OFFSET   16
 
#define HSTIMER_BGR_REG_HSTIMER_RST_CLEAR_MASK   0x00010000
 
#define HSTIMER_BGR_REG_HSTIMER_RST_ASSERT   0b0
 
#define HSTIMER_BGR_REG_HSTIMER_RST_DE_ASSERT   0b1
 
#define HSTIMER_BGR_REG_HSTIMER_GATING_OFFSET   0
 
#define HSTIMER_BGR_REG_HSTIMER_GATING_CLEAR_MASK   0x00000001
 
#define HSTIMER_BGR_REG_HSTIMER_GATING_MASK   0b0
 
#define HSTIMER_BGR_REG_HSTIMER_GATING_PASS   0b1
 
#define AVS_CLK_REG   0x00000740
 
#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TIMER_APB_CLK_REG   0x00000744
 
#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_OFFSET   31
 
#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TIMER_BGR_REG   0x0000074c
 
#define TIMER_BGR_REG_TIMER_RST_OFFSET   16
 
#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK   0x00010000
 
#define TIMER_BGR_REG_TIMER_RST_ASSERT   0b0
 
#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT   0b1
 
#define CAN_BGR_REG   0x0000075c
 
#define CAN_BGR_REG_CAN1_RST_OFFSET   17
 
#define CAN_BGR_REG_CAN1_RST_CLEAR_MASK   0x00020000
 
#define CAN_BGR_REG_CAN1_RST_ASSERT   0b0
 
#define CAN_BGR_REG_CAN1_RST_DE_ASSERT   0b1
 
#define CAN_BGR_REG_CAN0_RST_OFFSET   16
 
#define CAN_BGR_REG_CAN0_RST_CLEAR_MASK   0x00010000
 
#define CAN_BGR_REG_CAN0_RST_ASSERT   0b0
 
#define CAN_BGR_REG_CAN0_RST_DE_ASSERT   0b1
 
#define CAN_BGR_REG_CAN1_GATING_OFFSET   1
 
#define CAN_BGR_REG_CAN1_GATING_CLEAR_MASK   0x00000002
 
#define CAN_BGR_REG_CAN1_GATING_MASK   0b0
 
#define CAN_BGR_REG_CAN1_GATING_PASS   0b1
 
#define CAN_BGR_REG_CAN0_GATING_OFFSET   0
 
#define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK   0x00000001
 
#define CAN_BGR_REG_CAN0_GATING_MASK   0b0
 
#define CAN_BGR_REG_CAN0_GATING_PASS   0b1
 
#define DBGSYS_BGR_REG   0x0000078c
 
#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16
 
#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   0x00010000
 
#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0b0
 
#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0b1
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   0x00000001
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0b0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0b1
 
#define PWM_BGR_REG   0x000007ac
 
#define PWM_BGR_REG_PWM_RST_OFFSET   16
 
#define PWM_BGR_REG_PWM_RST_CLEAR_MASK   0x00010000
 
#define PWM_BGR_REG_PWM_RST_ASSERT   0b0
 
#define PWM_BGR_REG_PWM_RST_DE_ASSERT   0b1
 
#define PWM_BGR_REG_PWM_GATING_OFFSET   0
 
#define PWM_BGR_REG_PWM_GATING_CLEAR_MASK   0x00000001
 
#define PWM_BGR_REG_PWM_GATING_MASK   0b0
 
#define PWM_BGR_REG_PWM_GATING_PASS   0b1
 
#define DRAM_CLK_REG   0x00000800
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET   31
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON   0b1
 
#define DRAM_CLK_REG_DRAM_UPD_OFFSET   27
 
#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK   0x08000000
 
#define DRAM_CLK_REG_DRAM_UPD_INVALID   0b0
 
#define DRAM_CLK_REG_DRAM_UPD_VALID   0b1
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET   24
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK   0x07000000
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_HOSC   0b000
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL   0b001
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERIPLL2X   0b010
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI_800M   0b011
 
#define DRAM_CLK_REG_DRAM_DIV2_OFFSET   8
 
#define DRAM_CLK_REG_DRAM_DIV2_CLEAR_MASK   0x00000300
 
#define DRAM_CLK_REG_DRAM_DIV2_1   0b00
 
#define DRAM_CLK_REG_DRAM_DIV2_2   0b01
 
#define DRAM_CLK_REG_DRAM_DIV2_4   0b10
 
#define DRAM_CLK_REG_DRAM_DIV2_8   0b11
 
#define DRAM_CLK_REG_DRAM_DIV1_OFFSET   0
 
#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK   0x0000001f
 
#define MBUS_MAT_CLK_GATING_REG   0x00000804
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   21
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00200000
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   20
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET   19
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET   18
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET   17
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET   16
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE   0b0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE   0b1
 
#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_OFFSET   10
 
#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_CLEAR_MASK   0x00000400
 
#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_PASS   0b1
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET   9
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK   0x00000200
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS   0b1
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET   8
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK   0x00000100
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS   0b1
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET   2
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK   0x00000004
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS   0b1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET   1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK   0x00000002
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS   0b1
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET   0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK   0x00000001
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK   0b0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS   0b1
 
#define DRAM_BGR_REG   0x0000080c
 
#define DRAM_BGR_REG_DRAM_RST_OFFSET   16
 
#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK   0x00010000
 
#define DRAM_BGR_REG_DRAM_RST_ASSERT   0b0
 
#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT   0b1
 
#define DRAM_BGR_REG_DRAM_GATING_OFFSET   0
 
#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK   0x00000001
 
#define DRAM_BGR_REG_DRAM_GATING_MASK   0b0
 
#define DRAM_BGR_REG_DRAM_GATING_PASS   0b1
 
#define SMHC0_CLK_REG   0x00000830
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100
 
#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SMHC0_CLK_REG_FACTOR_N_1   0b00
 
#define SMHC0_CLK_REG_FACTOR_N_2   0b01
 
#define SMHC0_CLK_REG_FACTOR_N_4   0b10
 
#define SMHC0_CLK_REG_FACTOR_N_8   0b11
 
#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SMHC1_CLK_REG   0x00000834
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100
 
#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SMHC1_CLK_REG_FACTOR_N_1   0b00
 
#define SMHC1_CLK_REG_FACTOR_N_2   0b01
 
#define SMHC1_CLK_REG_FACTOR_N_4   0b10
 
#define SMHC1_CLK_REG_FACTOR_N_8   0b11
 
#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SMHC2_CLK_REG   0x00000838
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI_600M   0b001
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI_800M   0b010
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100
 
#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SMHC2_CLK_REG_FACTOR_N_1   0b00
 
#define SMHC2_CLK_REG_FACTOR_N_2   0b01
 
#define SMHC2_CLK_REG_FACTOR_N_4   0b10
 
#define SMHC2_CLK_REG_FACTOR_N_8   0b11
 
#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SMHC_BGR_REG   0x0000084c
 
#define SMHC_BGR_REG_SMHC2_RST_OFFSET   18
 
#define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK   0x00040000
 
#define SMHC_BGR_REG_SMHC2_RST_ASSERT   0b0
 
#define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT   0b1
 
#define SMHC_BGR_REG_SMHC1_RST_OFFSET   17
 
#define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK   0x00020000
 
#define SMHC_BGR_REG_SMHC1_RST_ASSERT   0b0
 
#define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT   0b1
 
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   16
 
#define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK   0x00010000
 
#define SMHC_BGR_REG_SMHC0_RST_ASSERT   0b0
 
#define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT   0b1
 
#define SMHC_BGR_REG_SMHC2_GATING_OFFSET   2
 
#define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK   0x00000004
 
#define SMHC_BGR_REG_SMHC2_GATING_MASK   0b0
 
#define SMHC_BGR_REG_SMHC2_GATING_PASS   0b1
 
#define SMHC_BGR_REG_SMHC1_GATING_OFFSET   1
 
#define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK   0x00000002
 
#define SMHC_BGR_REG_SMHC1_GATING_MASK   0b0
 
#define SMHC_BGR_REG_SMHC1_GATING_PASS   0b1
 
#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET   0
 
#define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK   0x00000001
 
#define SMHC_BGR_REG_SMHC0_GATING_MASK   0b0
 
#define SMHC_BGR_REG_SMHC0_GATING_PASS   0b1
 
#define PSRAM_CLK_REG   0x00000850
 
#define PSRAM_CLK_REG_PSRAM_CLK_GATING_OFFSET   31
 
#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_ON   0b1
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_480M   0b001
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_400M   0b010
 
#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_300M   0b011
 
#define PSRAM_CLK_REG_FACTOR_M_OFFSET   0
 
#define PSRAM_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define PSRAM_BGR_REG   0x0000085c
 
#define PSRAM_BGR_REG_PSRAM_CTRL_RST_OFFSET   16
 
#define PSRAM_BGR_REG_PSRAM_CTRL_RST_CLEAR_MASK   0x00010000
 
#define PSRAM_BGR_REG_PSRAM_CTRL_RST_ASSERT   0b0
 
#define PSRAM_BGR_REG_PSRAM_CTRL_RST_DE_ASSERT   0b1
 
#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_OFFSET   0
 
#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_CLEAR_MASK   0x00000001
 
#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_MASK   0b0
 
#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_PASS   0b1
 
#define UART_BGR_REG   0x0000090c
 
#define UART_BGR_REG_UART3_RST_OFFSET   19
 
#define UART_BGR_REG_UART3_RST_CLEAR_MASK   0x00080000
 
#define UART_BGR_REG_UART3_RST_ASSERT   0b0
 
#define UART_BGR_REG_UART3_RST_DE_ASSERT   0b1
 
#define UART_BGR_REG_UART2_RST_OFFSET   18
 
#define UART_BGR_REG_UART2_RST_CLEAR_MASK   0x00040000
 
#define UART_BGR_REG_UART2_RST_ASSERT   0b0
 
#define UART_BGR_REG_UART2_RST_DE_ASSERT   0b1
 
#define UART_BGR_REG_UART1_RST_OFFSET   17
 
#define UART_BGR_REG_UART1_RST_CLEAR_MASK   0x00020000
 
#define UART_BGR_REG_UART1_RST_ASSERT   0b0
 
#define UART_BGR_REG_UART1_RST_DE_ASSERT   0b1
 
#define UART_BGR_REG_UART0_RST_OFFSET   16
 
#define UART_BGR_REG_UART0_RST_CLEAR_MASK   0x00010000
 
#define UART_BGR_REG_UART0_RST_ASSERT   0b0
 
#define UART_BGR_REG_UART0_RST_DE_ASSERT   0b1
 
#define UART_BGR_REG_UART3_GATING_OFFSET   3
 
#define UART_BGR_REG_UART3_GATING_CLEAR_MASK   0x00000008
 
#define UART_BGR_REG_UART3_GATING_MASK   0b0
 
#define UART_BGR_REG_UART3_GATING_PASS   0b1
 
#define UART_BGR_REG_UART2_GATING_OFFSET   2
 
#define UART_BGR_REG_UART2_GATING_CLEAR_MASK   0x00000004
 
#define UART_BGR_REG_UART2_GATING_MASK   0b0
 
#define UART_BGR_REG_UART2_GATING_PASS   0b1
 
#define UART_BGR_REG_UART1_GATING_OFFSET   1
 
#define UART_BGR_REG_UART1_GATING_CLEAR_MASK   0x00000002
 
#define UART_BGR_REG_UART1_GATING_MASK   0b0
 
#define UART_BGR_REG_UART1_GATING_PASS   0b1
 
#define UART_BGR_REG_UART0_GATING_OFFSET   0
 
#define UART_BGR_REG_UART0_GATING_CLEAR_MASK   0x00000001
 
#define UART_BGR_REG_UART0_GATING_MASK   0b0
 
#define UART_BGR_REG_UART0_GATING_PASS   0b1
 
#define TWI_BGR_REG   0x0000091c
 
#define TWI_BGR_REG_TWI3_RST_OFFSET   19
 
#define TWI_BGR_REG_TWI3_RST_CLEAR_MASK   0x00080000
 
#define TWI_BGR_REG_TWI3_RST_ASSERT   0b0
 
#define TWI_BGR_REG_TWI3_RST_DE_ASSERT   0b1
 
#define TWI_BGR_REG_TWI2_RST_OFFSET   18
 
#define TWI_BGR_REG_TWI2_RST_CLEAR_MASK   0x00040000
 
#define TWI_BGR_REG_TWI2_RST_ASSERT   0b0
 
#define TWI_BGR_REG_TWI2_RST_DE_ASSERT   0b1
 
#define TWI_BGR_REG_TWI1_RST_OFFSET   17
 
#define TWI_BGR_REG_TWI1_RST_CLEAR_MASK   0x00020000
 
#define TWI_BGR_REG_TWI1_RST_ASSERT   0b0
 
#define TWI_BGR_REG_TWI1_RST_DE_ASSERT   0b1
 
#define TWI_BGR_REG_TWI0_RST_OFFSET   16
 
#define TWI_BGR_REG_TWI0_RST_CLEAR_MASK   0x00010000
 
#define TWI_BGR_REG_TWI0_RST_ASSERT   0b0
 
#define TWI_BGR_REG_TWI0_RST_DE_ASSERT   0b1
 
#define TWI_BGR_REG_TWI3_GATING_OFFSET   3
 
#define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK   0x00000008
 
#define TWI_BGR_REG_TWI3_GATING_MASK   0b0
 
#define TWI_BGR_REG_TWI3_GATING_PASS   0b1
 
#define TWI_BGR_REG_TWI2_GATING_OFFSET   2
 
#define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK   0x00000004
 
#define TWI_BGR_REG_TWI2_GATING_MASK   0b0
 
#define TWI_BGR_REG_TWI2_GATING_PASS   0b1
 
#define TWI_BGR_REG_TWI1_GATING_OFFSET   1
 
#define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK   0x00000002
 
#define TWI_BGR_REG_TWI1_GATING_MASK   0b0
 
#define TWI_BGR_REG_TWI1_GATING_PASS   0b1
 
#define TWI_BGR_REG_TWI0_GATING_OFFSET   0
 
#define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK   0x00000001
 
#define TWI_BGR_REG_TWI0_GATING_MASK   0b0
 
#define TWI_BGR_REG_TWI0_GATING_PASS   0b1
 
#define SPI0_CLK_REG   0x00000940
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010
 
#define SPI0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SPI0_CLK_REG_FACTOR_N_1   0b00
 
#define SPI0_CLK_REG_FACTOR_N_2   0b01
 
#define SPI0_CLK_REG_FACTOR_N_4   0b10
 
#define SPI0_CLK_REG_FACTOR_N_8   0b11
 
#define SPI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SPI1_CLK_REG   0x00000944
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010
 
#define SPI1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SPI1_CLK_REG_FACTOR_N_1   0b00
 
#define SPI1_CLK_REG_FACTOR_N_2   0b01
 
#define SPI1_CLK_REG_FACTOR_N_4   0b10
 
#define SPI1_CLK_REG_FACTOR_N_8   0b11
 
#define SPI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SPI2_CLK_REG   0x00000948
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010
 
#define SPI2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SPI2_CLK_REG_FACTOR_N_1   0b00
 
#define SPI2_CLK_REG_FACTOR_N_2   0b01
 
#define SPI2_CLK_REG_FACTOR_N_4   0b10
 
#define SPI2_CLK_REG_FACTOR_N_8   0b11
 
#define SPI2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SPIF_CLK_REG   0x00000950
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0b1
 
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010
 
#define SPIF_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define SPIF_CLK_REG_FACTOR_N_1   0b00
 
#define SPIF_CLK_REG_FACTOR_N_2   0b01
 
#define SPIF_CLK_REG_FACTOR_N_4   0b10
 
#define SPIF_CLK_REG_FACTOR_N_8   0b11
 
#define SPIF_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define SPI_BGR_REG   0x0000096c
 
#define SPI_BGR_REG_SPIF_RST_OFFSET   20
 
#define SPI_BGR_REG_SPIF_RST_CLEAR_MASK   0x00100000
 
#define SPI_BGR_REG_SPIF_RST_ASSERT   0b0
 
#define SPI_BGR_REG_SPIF_RST_DE_ASSERT   0b1
 
#define SPI_BGR_REG_SPI2_RST_OFFSET   18
 
#define SPI_BGR_REG_SPI2_RST_CLEAR_MASK   0x00040000
 
#define SPI_BGR_REG_SPI2_RST_ASSERT   0b0
 
#define SPI_BGR_REG_SPI2_RST_DE_ASSERT   0b1
 
#define SPI_BGR_REG_SPI1_RST_OFFSET   17
 
#define SPI_BGR_REG_SPI1_RST_CLEAR_MASK   0x00020000
 
#define SPI_BGR_REG_SPI1_RST_ASSERT   0b0
 
#define SPI_BGR_REG_SPI1_RST_DE_ASSERT   0b1
 
#define SPI_BGR_REG_SPI0_RST_OFFSET   16
 
#define SPI_BGR_REG_SPI0_RST_CLEAR_MASK   0x00010000
 
#define SPI_BGR_REG_SPI0_RST_ASSERT   0b0
 
#define SPI_BGR_REG_SPI0_RST_DE_ASSERT   0b1
 
#define SPI_BGR_REG_SPIF_GATING_OFFSET   4
 
#define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK   0x00000010
 
#define SPI_BGR_REG_SPIF_GATING_MASK   0b0
 
#define SPI_BGR_REG_SPIF_GATING_PASS   0b1
 
#define SPI_BGR_REG_SPI2_GATING_OFFSET   2
 
#define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK   0x00000004
 
#define SPI_BGR_REG_SPI2_GATING_MASK   0b0
 
#define SPI_BGR_REG_SPI2_GATING_PASS   0b1
 
#define SPI_BGR_REG_SPI1_GATING_OFFSET   1
 
#define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK   0x00000002
 
#define SPI_BGR_REG_SPI1_GATING_MASK   0b0
 
#define SPI_BGR_REG_SPI1_GATING_PASS   0b1
 
#define SPI_BGR_REG_SPI0_GATING_OFFSET   0
 
#define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK   0x00000001
 
#define SPI_BGR_REG_SPI0_GATING_MASK   0b0
 
#define SPI_BGR_REG_SPI0_GATING_PASS   0b1
 
#define GMAC_25M_CLK_REG   0x00000970
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_OFFSET   31
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_ON   0b1
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_OFFSET   30
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0b0
 
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_ON   0b1
 
#define GMAC_BGR_REG   0x0000097c
 
#define GMAC_BGR_REG_GMAC_RST_OFFSET   16
 
#define GMAC_BGR_REG_GMAC_RST_CLEAR_MASK   0x00010000
 
#define GMAC_BGR_REG_GMAC_RST_ASSERT   0b0
 
#define GMAC_BGR_REG_GMAC_RST_DE_ASSERT   0b1
 
#define GMAC_BGR_REG_GMAC_GATING_OFFSET   0
 
#define GMAC_BGR_REG_GMAC_GATING_CLEAR_MASK   0x00000001
 
#define GMAC_BGR_REG_GMAC_GATING_MASK   0b0
 
#define GMAC_BGR_REG_GMAC_GATING_PASS   0b1
 
#define GPADC_BGR_REG   0x000009ec
 
#define GPADC_BGR_REG_GPADC_RST_OFFSET   16
 
#define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK   0x00010000
 
#define GPADC_BGR_REG_GPADC_RST_ASSERT   0b0
 
#define GPADC_BGR_REG_GPADC_RST_DE_ASSERT   0b1
 
#define GPADC_BGR_REG_GPADC_GATING_OFFSET   0
 
#define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK   0x00000001
 
#define GPADC_BGR_REG_GPADC_GATING_MASK   0b0
 
#define GPADC_BGR_REG_GPADC_GATING_PASS   0b1
 
#define THS_BGR_REG   0x000009fc
 
#define THS_BGR_REG_THS_RST_OFFSET   16
 
#define THS_BGR_REG_THS_RST_CLEAR_MASK   0x00010000
 
#define THS_BGR_REG_THS_RST_ASSERT   0b0
 
#define THS_BGR_REG_THS_RST_DE_ASSERT   0b1
 
#define THS_BGR_REG_THS_GATING_OFFSET   0
 
#define THS_BGR_REG_THS_GATING_CLEAR_MASK   0x00000001
 
#define THS_BGR_REG_THS_GATING_MASK   0b0
 
#define THS_BGR_REG_THS_GATING_PASS   0b1
 
#define I2S0_CLK_REG   0x00000a10
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET   31
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0
 
#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1
 
#define I2S0_CLK_REG_FACTOR_M_OFFSET   0
 
#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define I2S_BGR_REG   0x00000a2c
 
#define I2S_BGR_REG_I2S0_RST_OFFSET   16
 
#define I2S_BGR_REG_I2S0_RST_CLEAR_MASK   0x00010000
 
#define I2S_BGR_REG_I2S0_RST_ASSERT   0b0
 
#define I2S_BGR_REG_I2S0_RST_DE_ASSERT   0b1
 
#define I2S_BGR_REG_I2S0_GATING_OFFSET   0
 
#define I2S_BGR_REG_I2S0_GATING_CLEAR_MASK   0x00000001
 
#define I2S_BGR_REG_I2S0_GATING_MASK   0b0
 
#define I2S_BGR_REG_I2S0_GATING_PASS   0b1
 
#define AUDIO_CODEC_DAC_CLK_REG   0x00000a50
 
#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_OFFSET   31
 
#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0
 
#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1
 
#define AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_OFFSET   0
 
#define AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define AUDIO_CODEC_ADC_CLK_REG   0x00000a54
 
#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_OFFSET   31
 
#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_ON   0b1
 
#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0
 
#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1
 
#define AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_OFFSET   0
 
#define AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define AUDIO_CODEC_BGR_REG   0x00000a5c
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET   16
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK   0x00010000
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT   0b0
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT   0b1
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET   0
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK   0x00000001
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK   0b0
 
#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS   0b1
 
#define USB0_CLK_REG   0x00000a70
 
#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31
 
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1
 
#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET   30
 
#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK   0x40000000
 
#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT   0b0
 
#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT   0b1
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0b01
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K   0b10
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC   0b11
 
#define USB_BGR_REG   0x00000a8c
 
#define USB_BGR_REG_USBOTG0_RST_OFFSET   24
 
#define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK   0x01000000
 
#define USB_BGR_REG_USBOTG0_RST_ASSERT   0b0
 
#define USB_BGR_REG_USBOTG0_RST_DE_ASSERT   0b1
 
#define USB_BGR_REG_USBEHCI0_RST_OFFSET   20
 
#define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK   0x00100000
 
#define USB_BGR_REG_USBEHCI0_RST_ASSERT   0b0
 
#define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT   0b1
 
#define USB_BGR_REG_USBOHCI0_RST_OFFSET   16
 
#define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK   0x00010000
 
#define USB_BGR_REG_USBOHCI0_RST_ASSERT   0b0
 
#define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT   0b1
 
#define USB_BGR_REG_USBOTG0_GATING_OFFSET   8
 
#define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK   0x00000100
 
#define USB_BGR_REG_USBOTG0_GATING_MASK   0b0
 
#define USB_BGR_REG_USBOTG0_GATING_PASS   0b1
 
#define USB_BGR_REG_USBEHCI0_GATING_OFFSET   4
 
#define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK   0x00000010
 
#define USB_BGR_REG_USBEHCI0_GATING_MASK   0b0
 
#define USB_BGR_REG_USBEHCI0_GATING_PASS   0b1
 
#define USB_BGR_REG_USBOHCI0_GATING_OFFSET   0
 
#define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK   0x00000001
 
#define USB_BGR_REG_USBOHCI0_GATING_MASK   0b0
 
#define USB_BGR_REG_USBOHCI0_GATING_PASS   0b1
 
#define DPSS_TOP_BGR_REG   0x00000abc
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_OFFSET   16
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_CLEAR_MASK   0x00010000
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_ASSERT   0b0
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_DE_ASSERT   0b1
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_OFFSET   0
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_CLEAR_MASK   0x00000001
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_MASK   0b0
 
#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_PASS   0b1
 
#define TCONLCD_CLK_REG   0x00000b60
 
#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_OFFSET   31
 
#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_ON   0b1
 
#define TCONLCD_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TCONLCD_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TCONLCD_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b000
 
#define TCONLCD_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b001
 
#define TCONLCD_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b010
 
#define TCONLCD_CLK_REG_FACTOR_N_OFFSET   8
 
#define TCONLCD_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define TCONLCD_CLK_REG_FACTOR_N_1   0b00
 
#define TCONLCD_CLK_REG_FACTOR_N_2   0b01
 
#define TCONLCD_CLK_REG_FACTOR_N_4   0b10
 
#define TCONLCD_CLK_REG_FACTOR_N_8   0b11
 
#define TCONLCD_CLK_REG_FACTOR_M_OFFSET   0
 
#define TCONLCD_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define TCONLCD_BGR_REG   0x00000b7c
 
#define TCONLCD_BGR_REG_TCONLCD_RST_OFFSET   16
 
#define TCONLCD_BGR_REG_TCONLCD_RST_CLEAR_MASK   0x00010000
 
#define TCONLCD_BGR_REG_TCONLCD_RST_ASSERT   0b0
 
#define TCONLCD_BGR_REG_TCONLCD_RST_DE_ASSERT   0b1
 
#define TCONLCD_BGR_REG_TCONLCD_GATING_OFFSET   0
 
#define TCONLCD_BGR_REG_TCONLCD_GATING_CLEAR_MASK   0x00000001
 
#define TCONLCD_BGR_REG_TCONLCD_GATING_MASK   0b0
 
#define TCONLCD_BGR_REG_TCONLCD_GATING_PASS   0b1
 
#define CSI_CLK_REG   0x00000c04
 
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI_300M   0b000
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010
 
#define CSI_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b011
 
#define CSI_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER0_CLK_REG   0x00000c08
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_1   0b00
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_2   0b01
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_4   0b10
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_8   0b11
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER1_CLK_REG   0x00000c0c
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_1   0b00
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_2   0b01
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_4   0b10
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_8   0b11
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER2_CLK_REG   0x00000c10
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC   0b000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_1   0b00
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_2   0b01
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_4   0b10
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_8   0b11
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_BGR_REG   0x00000c2c
 
#define CSI_BGR_REG_CSI_RST_OFFSET   16
 
#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   0x00010000
 
#define CSI_BGR_REG_CSI_RST_ASSERT   0b0
 
#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0b1
 
#define CSI_BGR_REG_CSI_GATING_OFFSET   0
 
#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   0x00000001
 
#define CSI_BGR_REG_CSI_GATING_MASK   0b0
 
#define CSI_BGR_REG_CSI_GATING_PASS   0b1
 
#define E907_CLK_REG   0x00000d00
 
#define E907_CLK_REG_E907_CLK_SEL_OFFSET   24
 
#define E907_CLK_REG_E907_CLK_SEL_CLEAR_MASK   0x07000000
 
#define E907_CLK_REG_E907_CLK_SEL_HOSC   0b000
 
#define E907_CLK_REG_E907_CLK_SEL_CLK32K   0b001
 
#define E907_CLK_REG_E907_CLK_SEL_CLK16M_RC   0b010
 
#define E907_CLK_REG_E907_CLK_SEL_PERI_600M   0b011
 
#define E907_CLK_REG_E907_CLK_SEL_PERI_800M   0b100
 
#define E907_CLK_REG_E907_CLK_SEL_CPUPLL   0b101
 
#define E907_CLK_REG_E907_AXI_DIV_CFG_OFFSET   8
 
#define E907_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK   0x00000300
 
#define E907_CLK_REG_E907_DIV_CFG_OFFSET   0
 
#define E907_CLK_REG_E907_DIV_CFG_CLEAR_MASK   0x0000001f
 
#define E907_GATING_RST_REG   0x00000d04
 
#define E907_GATING_RST_REG_E907_GATING_RST_FIELD_OFFSET   16
 
#define E907_GATING_RST_REG_E907_GATING_RST_FIELD_CLEAR_MASK   0xffff0000
 
#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_OFFSET   3
 
#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_CLEAR_MASK   0x00000008
 
#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_ASSERT   0b0
 
#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_DE_ASSERT   0b1
 
#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_OFFSET   2
 
#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_CLEAR_MASK   0x00000004
 
#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_ASSERT   0b0
 
#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_DE_ASSERT   0b1
 
#define E907_GATING_RST_REG_E907_SOFT_RSTN_OFFSET   1
 
#define E907_GATING_RST_REG_E907_SOFT_RSTN_CLEAR_MASK   0x00000002
 
#define E907_GATING_RST_REG_E907_SOFT_RSTN_ASSERT   0b0
 
#define E907_GATING_RST_REG_E907_SOFT_RSTN_DE_ASSERT   0b1
 
#define E907_GATING_RST_REG_E907_CLK_GATING_OFFSET   0
 
#define E907_GATING_RST_REG_E907_CLK_GATING_CLEAR_MASK   0x00000001
 
#define E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_OFF   0b0
 
#define E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_ON   0b1
 
#define RISCV_CFG_BGR_REG   0x00000d0c
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_OFFSET   16
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_CLEAR_MASK   0x00010000
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_ASSERT   0b0
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_DE_ASSERT   0b1
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_OFFSET   0
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_CLEAR_MASK   0x00000001
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_MASK   0b0
 
#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_PASS   0b1
 
#define PLL_PRE_DIV_REG   0x00000e00
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_OFFSET   28
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_CLEAR_MASK   0x10000000
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIOPLL_DIV2   0b0
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIO_FRAC_DIV4X   0b1
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_OFFSET   24
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_CLEAR_MASK   0x01000000
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIOPLL_DIV5   0b0
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIO_FRAC_DIV1X   0b1
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_OFFSET   5
 
#define PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_CLEAR_MASK   0x000003e0
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_OFFSET   0
 
#define PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_CLEAR_MASK   0x0000001f
 
#define AHB_GATE_EN_REG   0x00000e04
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   0x10000000
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_OFFSET   13
 
#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00002000
 
#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET   12
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00001000
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET   11
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000800
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET   10
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000400
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET   9
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000200
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_OFFSET   8
 
#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100
 
#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   7
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   6
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000040
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   5
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000020
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET   4
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000010
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET   3
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET   1
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE   0b0
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG   0x00000e08
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_OFFSET   27
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_OFFSET   26
 
#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000
 
#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_OFFSET   25
 
#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000
 
#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_OFFSET   23
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_OFFSET   22
 
#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_OFFSET   20
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_OFFSET   19
 
#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_OFFSET   17
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_OFFSET   16
 
#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_DISABLE   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_ENABLE   0b1
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_OFFSET   11
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_OFFSET   10
 
#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400
 
#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200
 
#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040
 
#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008
 
#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_AUTO   0b0
 
#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_NO_AUTO   0b1
 
#define CLK24M_GATE_EN_REG   0x00000e0c
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   0x00000008
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0b0
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0b1
 
#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_OFFSET   2
 
#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_CLEAR_MASK   0x00000004
 
#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_DISABLE   0b0
 
#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_ENABLE   0b1
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET   0
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK   0x00000001
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE   0b0
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE   0b1
 
#define PLL_OPG_BYPASS_REG   0x00000e10
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET   0
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK   0x00000001
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE   0b0
 
#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG   0x00000e14
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_OFFSET   20
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_OFFSET   19
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_OFFSET   18
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_OFFSET   17
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_OFFSET   16
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_DISABLE   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_ENABLE   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_OFFSET   4
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_OFFSET   3
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000008
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_OFFSET   2
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_OFFSET   1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_NO_AUTO   0b1
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_OFFSET   0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_AUTO   0b0
 
#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG   0x00000e18
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_OFFSET   18
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_OFFSET   17
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_OFFSET   16
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_DISABLE   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_ENABLE   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_OFFSET   2
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_OFFSET   1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_OFFSET   0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_AUTO   0b0
 
#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define CSIPLL_GATE_EN_REG   0x00000e1c
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_OFFSET   18
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_OFFSET   17
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_OFFSET   16
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_DISABLE   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_ENABLE   0b1
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_OFFSET   2
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_OFFSET   1
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_OFFSET   0
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_AUTO   0b0
 
#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define DDRPLL_GATE_EN_REG   0x00000e20
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET   16
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE   0b0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE   0b1
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET   0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO   0b0
 
#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define CPUPLL_GATE_EN_REG   0x00000e24
 
#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_OFFSET   16
 
#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_DISABLE   0b0
 
#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_ENABLE   0b1
 
#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_OFFSET   0
 
#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_AUTO   0b0
 
#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_NO_AUTO   0b1
 
#define PERIPLL_GATE_STAT_REG   0x00000e28
 
#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_OFFSET   27
 
#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_CLEAR_MASK   0x08000000
 
#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_OFFSET   26
 
#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_CLEAR_MASK   0x04000000
 
#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_OFFSET   25
 
#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_CLEAR_MASK   0x02000000
 
#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_OFFSET   24
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_OFFSET   23
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_CLEAR_MASK   0x00800000
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_OFFSET   22
 
#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_CLEAR_MASK   0x00400000
 
#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_OFFSET   21
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_OFFSET   20
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_CLEAR_MASK   0x00100000
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_OFFSET   19
 
#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_CLEAR_MASK   0x00080000
 
#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_OFFSET   18
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_OFFSET   17
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_CLEAR_MASK   0x00020000
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_ENABLE   0b1
 
#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_OFFSET   16
 
#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_CLEAR_MASK   0x00010000
 
#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_DISABLE   0b0
 
#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG   0x00000e2c
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_OFFSET   20
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_CLEAR_MASK   0x00100000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_OFFSET   19
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_CLEAR_MASK   0x00080000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_OFFSET   18
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_CLEAR_MASK   0x00040000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_OFFSET   17
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_CLEAR_MASK   0x00020000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_ENABLE   0b1
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_OFFSET   16
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_CLEAR_MASK   0x00010000
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_DISABLE   0b0
 
#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG   0x00000e30
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_OFFSET   18
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_CLEAR_MASK   0x00040000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_OFFSET   17
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_CLEAR_MASK   0x00020000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_ENABLE   0b1
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_OFFSET   16
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_CLEAR_MASK   0x00010000
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_DISABLE   0b0
 
#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_ENABLE   0b1
 
#define CSIPLL_GATE_STAT_REG   0x00000e34
 
#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_OFFSET   18
 
#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_CLEAR_MASK   0x00040000
 
#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_DISABLE   0b0
 
#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_ENABLE   0b1
 
#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_OFFSET   17
 
#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_CLEAR_MASK   0x00020000
 
#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_DISABLE   0b0
 
#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_ENABLE   0b1
 
#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_OFFSET   16
 
#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_CLEAR_MASK   0x00010000
 
#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_DISABLE   0b0
 
#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_ENABLE   0b1
 
#define DDRPLL_GATE_STAT_REG   0x00000e38
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET   16
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK   0x00010000
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE   0b0
 
#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE   0b1
 
#define CPUPLL_GATE_STAT_REG   0x00000e3c
 
#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_OFFSET   16
 
#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_CLEAR_MASK   0x00010000
 
#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_DISABLE   0b0
 
#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_ENABLE   0b1
 
#define NPUPLL_GATE_EN_REG   0x00000e40
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_OFFSET   18
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_DISABLE   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_ENABLE   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_OFFSET   17
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_DISABLE   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_ENABLE   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_OFFSET   16
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_DISABLE   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_ENABLE   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_OFFSET   2
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_AUTO   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_OFFSET   1
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_AUTO   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_OFFSET   0
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_AUTO   0b0
 
#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_NO_AUTO   0b1
 
#define NPUPLL_GATE_STAT_REG   0x00000e44
 
#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_OFFSET   18
 
#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_CLEAR_MASK   0x00040000
 
#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_DISABLE   0b0
 
#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_ENABLE   0b1
 
#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_OFFSET   17
 
#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_CLEAR_MASK   0x00020000
 
#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_DISABLE   0b0
 
#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_ENABLE   0b1
 
#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_OFFSET   16
 
#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_CLEAR_MASK   0x00010000
 
#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_DISABLE   0b0
 
#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_ENABLE   0b1
 
#define CCU_SEC_SWITCH_REG   0x00000f00
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1
 
#define GPADC_CLK_SEL_REG   0x00000f04
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_OFFSET   20
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_CLEAR_MASK   0x00700000
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_32   0b000
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_16   0b001
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_8   0b010
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_4   0b011
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_2   0b100
 
#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC   0b101
 
#define FRE_DET_CTRL_REG   0x00000f08
 
#define FRE_DET_CTRL_REG_ERROR_FLAG_OFFSET   31
 
#define FRE_DET_CTRL_REG_ERROR_FLAG_CLEAR_MASK   0x80000000
 
#define FRE_DET_CTRL_REG_ERROR_FLAG_WRITE_0_TO_CLEAR   0b0
 
#define FRE_DET_CTRL_REG_ERROR_FLAG_ERROR   0b1
 
#define FRE_DET_CTRL_REG_DET_TIME_OFFSET   4
 
#define FRE_DET_CTRL_REG_DET_TIME_CLEAR_MASK   0x000001f0
 
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_OFFSET   1
 
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_CLEAR_MASK   0x00000002
 
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_DISABLE   0b0
 
#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_ENABLE   0b1
 
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_OFFSET   0
 
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_CLEAR_MASK   0x00000001
 
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_DISABLE   0b0
 
#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_ENABLE   0b1
 
#define FRE_UP_LIM_REG   0x00000f0c
 
#define FRE_UP_LIM_REG_FRE_UP_LIM_OFFSET   0
 
#define FRE_UP_LIM_REG_FRE_UP_LIM_CLEAR_MASK   0xffffffff
 
#define FRE_DOWN_LIM_REG   0x00000f10
 
#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_OFFSET   0
 
#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_CLEAR_MASK   0xffffffff
 
#define CCU_FAN_GATE_REG   0x00000f30
 
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG   0x00000f34
 
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31
 
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEOPLL1X   0b000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CSIPLL1X   0b001
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_PERI_300M   0b010
 
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8
 
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00000300
 
#define CLK27M_FAN_REG_CLK27M_DIV1_1   0b00
 
#define CLK27M_FAN_REG_CLK27M_DIV1_2   0b01
 
#define CLK27M_FAN_REG_CLK27M_DIV1_4   0b10
 
#define CLK27M_FAN_REG_CLK27M_DIV1_8   0b11
 
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0
 
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f
 
#define CLK_FAN_REG   0x00000f38
 
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1
 
#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5
 
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0
 
#define CLK_FAN_REG_PCLK_DIV_OFFSET   0
 
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f
 
#define CCU_FAN_REG   0x00000f3c
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   0x00800000
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   0x00400000
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   0x00200000
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0b0
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0b1
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   0x000001c0
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0b110
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   0x00000038
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0b110
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   0x00000007
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2   0b001
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10   0b010
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO   0b011
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6   0b100
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0b101
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0b110
 
#define CCU_VERSION_REG   0x00000ff0
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff
 
#define CCU_PLL_CPUX_CTRL_REG   (SUNXI_CCU_BASE + PLL_CPU_CTRL_REG)
 
#define CCU_PLL_DDR0_CTRL_REG   (SUNXI_CCU_BASE + PLL_DDR_CTRL_REG)
 
#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI_CTRL_REG)
 
#define CCU_PLL_VIDEO_CTRL_REG   (SUNXI_CCU_BASE + PLL_VIDEO_CTRL_REG)
 
#define CCU_PLL_AUDIO_CTRL_REG   (SUNXI_CCU_BASE + PLL_AUDIO_CTRL_REG)
 
#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC_BGR_REG)
 
#define CCU_CLK_SEL_REG   (SUNXI_CCU_BASE + GPADC_CLK_SEL_REG)
 
#define CCU_CLK24M_GATE_EN_REG   (SUNXI_CCU_BASE + CLK24M_GATE_EN_REG)
 
#define CCU_AUDIO_CODEC_BGR_REG   (SUNXI_CCU_BASE + AUDIO_CODEC_BGR_REG)
 
#define CCU_PLL_AUDIO0_PAT0_REG   (SUNXI_CCU_BASE + PLL_AUDIO_PAT0_CTRL_REG)
 
#define CCU_CPUX_AXI_CFG_REG   (SUNXI_CCU_BASE + CPU_CLK_REG)
 
#define CCU_E907_CFG_REG   (SUNXI_CCU_BASE + E907_CLK_REG)
 
#define CCU_PSI_AHB1_AHB2_CFG_REG   (SUNXI_CCU_BASE + AHB_CLK_REG)
 
#define CCU_APB0_CFG_GREG   (SUNXI_CCU_BASE + APB0_CLK_REG)
 
#define CCU_APB1_CFG_GREG   (SUNXI_CCU_BASE + APB1_CLK_REG)
 
#define CCU_MBUS_CFG_REG   (SUNXI_CCU_BASE + MBUS_CLK_REG)
 
#define CCU_CE_CLK_REG   (SUNXI_CCU_BASE + CE_CLK_REG)
 
#define CCU_CE_BGR_REG   (SUNXI_CCU_BASE + CE_BGR_REG)
 
#define CCU_DMA_BGR_REG   (SUNXI_CCU_BASE + DMA_BGR_REG)
 
#define CCU_AVS_CLK_REG   (SUNXI_CCU_BASE + AVS_CLK_REG)
 
#define CCU_DRAM_CLK_REG   (SUNXI_CCU_BASE + DRAM_CLK_REG)
 
#define CCU_MBUS_MST_CLK_GATING_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)
 
#define CCU_DRAM_BGR_REG   (SUNXI_CCU_BASE + DRAM_BGR_REG)
 
#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)
 
#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)
 
#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + 0x838)
 
#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC_BGR_REG)
 
#define CCU_SPI0_CLK_REG   (SUNXI_CCU_BASE + SPI0_CLK_REG)
 
#define CCU_SPI1_CLK_REG   (SUNXI_CCU_BASE + SPI1_CLK_REG)
 
#define CCU_SPI_BGR_CLK_REG   (SUNXI_CCU_BASE + SPI_BGR_REG)
 
#define CCU_USB0_CLK_REG   (SUNXI_CCU_BASE + USB0_CLK_REG)
 
#define CCU_USB_BGR_REG   (SUNXI_CCU_BASE + USB_BGR_REG)
 
#define DMA_GATING_BASE   CCU_DMA_BGR_REG
 
#define CE_USE_PLATFORM_CLOCK_FUNC
 
#define SUNXI_CE_MBUS_MST_CLK_GATE_EN_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)
 
#define SUNXI_CE_MBUS_MST_CLK_GATE_OFFSET   MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET
 
#define SUNXI_CE_CLK_REG   (SUNXI_CCU_BASE + CE_CLK_REG)
 
#define SUNXI_CE_SRC   CE_CLK_REG_CLK_SRC_SEL_PERI_400M
 
#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET   CE_CLK_REG_CLK_SRC_SEL_OFFSET
 
#define SUNXI_CE_FACTOR   (0b0)
 
#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET   CE_CLK_REG_FACTOR_M_OFFSET
 
#define SUNXI_CE_RESET_REG   (SUNXI_CCU_BASE + CE_BGR_REG)
 
#define SUNXI_CE_RESET_OFFSET   CE_BGR_REG_CE_RST_OFFSET
 
#define SUNXI_CE_SYS_RESET_OFFSET   CE_BGR_REG_CE_SYS_RST_OFFSET
 
#define SUNXI_CE_GATING_REG   (SUNXI_CCU_BASE + CE_BGR_REG)
 
#define SUNXI_CE_GATING_OFFSET   CE_BGR_REG_CE_GATING_OFFSET
 
#define SUNXI_CE_SYS_GATING_OFFSET   CE_BGR_REG_CE_SYS_GATING_OFFSET
 
#define E907_SYS_GATING_RESET_BASE   (SUNXI_CCU_BASE + 0xd04)
 
#define E907_GATING_RST_FIELD   (0x16aa)
 
#define E907_SYS_APB_SOFT_RST_BIT   (2)
 
#define E907_SOFT_RST_BIT   (1)
 
#define E907_CLK_GATING_BIT   (0)
 
#define E907_CFG_GATING_RESET_BASE   (SUNXI_CCU_BASE + 0xd0c)
 
#define E907_CFG_RST_BIT   (16)
 
#define E907_CFG_GATING_BIT   (0)
 
#define E907_CFG_BASE   (0x06010000)
 
#define E907_STA_ADD_REG   (E907_CFG_BASE + 0x0204)
 
#define PLL_CPUX_TUNING_REG   (0x1400)
 
#define CCM_SPIF_CTRL_M(x)   ((x) -1)
 
#define CCM_SPIF_CTRL_N(x)   ((x) << 8)
 
#define CCM_SPIF_CTRL_HOSC   (0x0 << 24)
 
#define CCM_SPIF_CTRL_PERI400M   (0x1 << 24)
 
#define CCM_SPIF_CTRL_PERI300M   (0x2 << 24)
 
#define CCM_SPIF_CTRL_ENABLE   (0x1 << 31)
 
#define GET_SPIF_CLK_SOURECS(x)   (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)
 
#define CCM_SPIF_CTRL_PERI   CCM_SPIF_CTRL_PERI400M
 
#define SPIF_RESET_SHIFT   (20)
 
#define SPIF_GATING_SHIFT   (4)
 

Macro Definition Documentation

◆ AHB_CLK_REG

#define AHB_CLK_REG   0x00000510

◆ AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK32K

#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ AHB_CLK_REG_CLK_SRC_SEL_HOSC

#define AHB_CLK_REG_CLK_SRC_SEL_HOSC   0b00

◆ AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AHB_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS

#define AHB_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11

◆ AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AHB_CLK_REG_FACTOR_M_OFFSET

#define AHB_CLK_REG_FACTOR_M_OFFSET   0

◆ AHB_CLK_REG_FACTOR_N_1

#define AHB_CLK_REG_FACTOR_N_1   0b00

◆ AHB_CLK_REG_FACTOR_N_2

#define AHB_CLK_REG_FACTOR_N_2   0b01

◆ AHB_CLK_REG_FACTOR_N_4

#define AHB_CLK_REG_FACTOR_N_4   0b10

◆ AHB_CLK_REG_FACTOR_N_8

#define AHB_CLK_REG_FACTOR_N_8   0b11

◆ AHB_CLK_REG_FACTOR_N_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ AHB_CLK_REG_FACTOR_N_OFFSET

#define AHB_CLK_REG_FACTOR_N_OFFSET   8

◆ AHB_GATE_EN_REG

#define AHB_GATE_EN_REG   0x00000e04

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   0x10000000

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28

◆ AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100

◆ AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC_AHB_GATE_SW_CFG_OFFSET   8

◆ AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00002000

◆ AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC_MBUS_AHB_GATE_SW_CFG_OFFSET   13

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0b0

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0b1

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000020

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   5

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000400

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET   10

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000040

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   6

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000800

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET   11

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   7

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00001000

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET   12

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000010

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET   4

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000200

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET   9

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET   1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE   0b0

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE   0b1

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET   3

◆ APB0_CLK_REG

#define APB0_CLK_REG   0x00000520

◆ APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ APB0_CLK_REG_CLK_SRC_SEL_HOSC

#define APB0_CLK_REG_CLK_SRC_SEL_HOSC   0b00

◆ APB0_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB0_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS

#define APB0_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11

◆ APB0_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB0_CLK_REG_FACTOR_M_OFFSET

#define APB0_CLK_REG_FACTOR_M_OFFSET   0

◆ APB0_CLK_REG_FACTOR_N_1

#define APB0_CLK_REG_FACTOR_N_1   0b00

◆ APB0_CLK_REG_FACTOR_N_2

#define APB0_CLK_REG_FACTOR_N_2   0b01

◆ APB0_CLK_REG_FACTOR_N_4

#define APB0_CLK_REG_FACTOR_N_4   0b10

◆ APB0_CLK_REG_FACTOR_N_8

#define APB0_CLK_REG_FACTOR_N_8   0b11

◆ APB0_CLK_REG_FACTOR_N_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ APB0_CLK_REG_FACTOR_N_OFFSET

#define APB0_CLK_REG_FACTOR_N_OFFSET   8

◆ APB1_CLK_REG

#define APB1_CLK_REG   0x00000524

◆ APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b10

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0b01

◆ APB1_CLK_REG_CLK_SRC_SEL_HOSC

#define APB1_CLK_REG_CLK_SRC_SEL_HOSC   0b00

◆ APB1_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB1_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS

#define APB1_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b11

◆ APB1_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB1_CLK_REG_FACTOR_M_OFFSET

#define APB1_CLK_REG_FACTOR_M_OFFSET   0

◆ APB1_CLK_REG_FACTOR_N_1

#define APB1_CLK_REG_FACTOR_N_1   0b00

◆ APB1_CLK_REG_FACTOR_N_2

#define APB1_CLK_REG_FACTOR_N_2   0b01

◆ APB1_CLK_REG_FACTOR_N_4

#define APB1_CLK_REG_FACTOR_N_4   0b10

◆ APB1_CLK_REG_FACTOR_N_8

#define APB1_CLK_REG_FACTOR_N_8   0b11

◆ APB1_CLK_REG_FACTOR_N_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ APB1_CLK_REG_FACTOR_N_OFFSET

#define APB1_CLK_REG_FACTOR_N_OFFSET   8

◆ APB_UART_CLK_REG

#define APB_UART_CLK_REG   0x00000528

◆ APB_UART_CLK_REG_CLK_SRC_SEL_AUDIO_CKO_DIV2

#define APB_UART_CLK_REG_CLK_SRC_SEL_AUDIO_CKO_DIV2   0b100

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0b010

◆ APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K   0b001

◆ APB_UART_CLK_REG_CLK_SRC_SEL_HOSC

#define APB_UART_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB_UART_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS

#define APB_UART_CLK_REG_CLK_SRC_SEL_PERI_600M_BUS   0b011

◆ APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB_UART_CLK_REG_FACTOR_M_OFFSET

#define APB_UART_CLK_REG_FACTOR_M_OFFSET   0

◆ APB_UART_CLK_REG_FACTOR_N_1

#define APB_UART_CLK_REG_FACTOR_N_1   0b00

◆ APB_UART_CLK_REG_FACTOR_N_2

#define APB_UART_CLK_REG_FACTOR_N_2   0b01

◆ APB_UART_CLK_REG_FACTOR_N_4

#define APB_UART_CLK_REG_FACTOR_N_4   0b10

◆ APB_UART_CLK_REG_FACTOR_N_8

#define APB_UART_CLK_REG_FACTOR_N_8   0b11

◆ APB_UART_CLK_REG_FACTOR_N_CLEAR_MASK

#define APB_UART_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ APB_UART_CLK_REG_FACTOR_N_OFFSET

#define APB_UART_CLK_REG_FACTOR_N_OFFSET   8

◆ AUDIO_CODEC_ADC_CLK_REG

#define AUDIO_CODEC_ADC_CLK_REG   0x00000a54

◆ AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLEAR_MASK

#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLEAR_MASK   0x80000000

◆ AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_OFF

#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_ON

#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_CLOCK_IS_ON   0b1

◆ AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_OFFSET

#define AUDIO_CODEC_ADC_CLK_REG_AUDIO_CODEC_ADC_CLK_GATING_OFFSET   31

◆ AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X

#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0

◆ AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X

#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1

◆ AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIO_CODEC_ADC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_OFFSET

#define AUDIO_CODEC_ADC_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIO_CODEC_BGR_REG

#define AUDIO_CODEC_BGR_REG   0x00000a5c

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_CLEAR_MASK   0x00000001

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_MASK   0b0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_OFFSET   0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_GATING_PASS   0b1

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_ASSERT   0b0

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_CLEAR_MASK   0x00010000

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_DE_ASSERT   0b1

◆ AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET

#define AUDIO_CODEC_BGR_REG_AUDIO_CODEC_RST_OFFSET   16

◆ AUDIO_CODEC_DAC_CLK_REG

#define AUDIO_CODEC_DAC_CLK_REG   0x00000a50

◆ AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLEAR_MASK

#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLEAR_MASK   0x80000000

◆ AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_OFF

#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_ON

#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_CLOCK_IS_ON   0b1

◆ AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_OFFSET

#define AUDIO_CODEC_DAC_CLK_REG_AUDIO_CODEC_DAC_CLK_GATING_OFFSET   31

◆ AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X

#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0

◆ AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X

#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1

◆ AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_OFFSET

#define AUDIO_CODEC_DAC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_CLEAR_MASK

#define AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_OFFSET

#define AUDIO_CODEC_DAC_CLK_REG_FACTOR_M_OFFSET   0

◆ AUDIOPLL_GATE_EN_REG

#define AUDIOPLL_GATE_EN_REG   0x00000e14

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000008

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_AUTO_GATE_EN_OFFSET   3

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL1X_GATE_SW_CFG_OFFSET   19

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_AUTO_GATE_EN_OFFSET   4

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL4X_GATE_SW_CFG_OFFSET   20

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_AUTO_GATE_EN_OFFSET   0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV2_GATE_SW_CFG_OFFSET   16

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_AUTO_GATE_EN_OFFSET   1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV3_GATE_SW_CFG_OFFSET   17

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_AUTO   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_NO_AUTO

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_NO_AUTO   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_AUTO_GATE_EN_OFFSET   2

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_CLEAR_MASK

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_DISABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_DISABLE   0b0

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_ENABLE

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_ENABLE   0b1

◆ AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_OFFSET

#define AUDIOPLL_GATE_EN_REG_AUDIOPLL_DIV5_GATE_SW_CFG_OFFSET   18

◆ AUDIOPLL_GATE_STAT_REG

#define AUDIOPLL_GATE_STAT_REG   0x00000e2c

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_CLEAR_MASK   0x00080000

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL1X_GATE_STAT_OFFSET   19

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_CLEAR_MASK   0x00100000

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL4X_GATE_STAT_OFFSET   20

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_CLEAR_MASK   0x00010000

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV2_GATE_STAT_OFFSET   16

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_CLEAR_MASK   0x00020000

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV3_GATE_STAT_OFFSET   17

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_CLEAR_MASK

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_CLEAR_MASK   0x00040000

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_DISABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_DISABLE   0b0

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_ENABLE

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_ENABLE   0b1

◆ AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_OFFSET

#define AUDIOPLL_GATE_STAT_REG_AUDIOPLL_DIV5_GATE_STAT_OFFSET   18

◆ AVS_CLK_REG

#define AVS_CLK_REG   0x00000740

◆ AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK

#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   0x80000000

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0b0

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0b1

◆ AVS_CLK_REG_AVS_CLK_GATING_OFFSET

#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31

◆ CAN_BGR_REG

#define CAN_BGR_REG   0x0000075c

◆ CAN_BGR_REG_CAN0_GATING_CLEAR_MASK

#define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK   0x00000001

◆ CAN_BGR_REG_CAN0_GATING_MASK

#define CAN_BGR_REG_CAN0_GATING_MASK   0b0

◆ CAN_BGR_REG_CAN0_GATING_OFFSET

#define CAN_BGR_REG_CAN0_GATING_OFFSET   0

◆ CAN_BGR_REG_CAN0_GATING_PASS

#define CAN_BGR_REG_CAN0_GATING_PASS   0b1

◆ CAN_BGR_REG_CAN0_RST_ASSERT

#define CAN_BGR_REG_CAN0_RST_ASSERT   0b0

◆ CAN_BGR_REG_CAN0_RST_CLEAR_MASK

#define CAN_BGR_REG_CAN0_RST_CLEAR_MASK   0x00010000

◆ CAN_BGR_REG_CAN0_RST_DE_ASSERT

#define CAN_BGR_REG_CAN0_RST_DE_ASSERT   0b1

◆ CAN_BGR_REG_CAN0_RST_OFFSET

#define CAN_BGR_REG_CAN0_RST_OFFSET   16

◆ CAN_BGR_REG_CAN1_GATING_CLEAR_MASK

#define CAN_BGR_REG_CAN1_GATING_CLEAR_MASK   0x00000002

◆ CAN_BGR_REG_CAN1_GATING_MASK

#define CAN_BGR_REG_CAN1_GATING_MASK   0b0

◆ CAN_BGR_REG_CAN1_GATING_OFFSET

#define CAN_BGR_REG_CAN1_GATING_OFFSET   1

◆ CAN_BGR_REG_CAN1_GATING_PASS

#define CAN_BGR_REG_CAN1_GATING_PASS   0b1

◆ CAN_BGR_REG_CAN1_RST_ASSERT

#define CAN_BGR_REG_CAN1_RST_ASSERT   0b0

◆ CAN_BGR_REG_CAN1_RST_CLEAR_MASK

#define CAN_BGR_REG_CAN1_RST_CLEAR_MASK   0x00020000

◆ CAN_BGR_REG_CAN1_RST_DE_ASSERT

#define CAN_BGR_REG_CAN1_RST_DE_ASSERT   0b1

◆ CAN_BGR_REG_CAN1_RST_OFFSET

#define CAN_BGR_REG_CAN1_RST_OFFSET   17

◆ CCM_SPIF_CTRL_ENABLE

#define CCM_SPIF_CTRL_ENABLE   (0x1 << 31)

◆ CCM_SPIF_CTRL_HOSC

#define CCM_SPIF_CTRL_HOSC   (0x0 << 24)

◆ CCM_SPIF_CTRL_M

#define CCM_SPIF_CTRL_M (   x)    ((x) -1)

◆ CCM_SPIF_CTRL_N

#define CCM_SPIF_CTRL_N (   x)    ((x) << 8)

◆ CCM_SPIF_CTRL_PERI

#define CCM_SPIF_CTRL_PERI   CCM_SPIF_CTRL_PERI400M

◆ CCM_SPIF_CTRL_PERI300M

#define CCM_SPIF_CTRL_PERI300M   (0x2 << 24)

◆ CCM_SPIF_CTRL_PERI400M

#define CCM_SPIF_CTRL_PERI400M   (0x1 << 24)

◆ CCU_APB0_CFG_GREG

#define CCU_APB0_CFG_GREG   (SUNXI_CCU_BASE + APB0_CLK_REG)

◆ CCU_APB1_CFG_GREG

#define CCU_APB1_CFG_GREG   (SUNXI_CCU_BASE + APB1_CLK_REG)

◆ CCU_AUDIO_CODEC_BGR_REG

#define CCU_AUDIO_CODEC_BGR_REG   (SUNXI_CCU_BASE + AUDIO_CODEC_BGR_REG)

◆ CCU_AVS_CLK_REG

#define CCU_AVS_CLK_REG   (SUNXI_CCU_BASE + AVS_CLK_REG)

◆ CCU_CE_BGR_REG

#define CCU_CE_BGR_REG   (SUNXI_CCU_BASE + CE_BGR_REG)

◆ CCU_CE_CLK_REG

#define CCU_CE_CLK_REG   (SUNXI_CCU_BASE + CE_CLK_REG)

◆ CCU_CLK24M_GATE_EN_REG

#define CCU_CLK24M_GATE_EN_REG   (SUNXI_CCU_BASE + CLK24M_GATE_EN_REG)

◆ CCU_CLK_SEL_REG

#define CCU_CLK_SEL_REG   (SUNXI_CCU_BASE + GPADC_CLK_SEL_REG)

◆ CCU_CPUX_AXI_CFG_REG

#define CCU_CPUX_AXI_CFG_REG   (SUNXI_CCU_BASE + CPU_CLK_REG)

◆ CCU_DMA_BGR_REG

#define CCU_DMA_BGR_REG   (SUNXI_CCU_BASE + DMA_BGR_REG)

◆ CCU_DRAM_BGR_REG

#define CCU_DRAM_BGR_REG   (SUNXI_CCU_BASE + DRAM_BGR_REG)

◆ CCU_DRAM_CLK_REG

#define CCU_DRAM_CLK_REG   (SUNXI_CCU_BASE + DRAM_CLK_REG)

◆ CCU_E907_CFG_REG

#define CCU_E907_CFG_REG   (SUNXI_CCU_BASE + E907_CLK_REG)

◆ CCU_FAN_GATE_REG

#define CCU_FAN_GATE_REG   0x00000f30

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK12M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK16M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK24M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_GATE_REG_CLK25M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3

◆ CCU_FAN_REG

#define CCU_FAN_REG   0x00000f3c

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   0x00200000

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   0x00000007

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0b110

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   0x00400000

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   0x00000038

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0b110

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   0x00800000

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0b0

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0b1

◆ CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   0x000001c0

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2   0b001

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10   0b010

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO   0b011

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6   0b100

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0b101

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0b000

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0b110

◆ CCU_GPADC_BGR_REG

#define CCU_GPADC_BGR_REG   (SUNXI_CCU_BASE + GPADC_BGR_REG)

◆ CCU_MBUS_CFG_REG

#define CCU_MBUS_CFG_REG   (SUNXI_CCU_BASE + MBUS_CLK_REG)

◆ CCU_MBUS_MST_CLK_GATING_REG

#define CCU_MBUS_MST_CLK_GATING_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

◆ CCU_PLL_AUDIO0_PAT0_REG

#define CCU_PLL_AUDIO0_PAT0_REG   (SUNXI_CCU_BASE + PLL_AUDIO_PAT0_CTRL_REG)

◆ CCU_PLL_AUDIO_CTRL_REG

#define CCU_PLL_AUDIO_CTRL_REG   (SUNXI_CCU_BASE + PLL_AUDIO_CTRL_REG)

◆ CCU_PLL_CPUX_CTRL_REG

#define CCU_PLL_CPUX_CTRL_REG   (SUNXI_CCU_BASE + PLL_CPU_CTRL_REG)

◆ CCU_PLL_DDR0_CTRL_REG

#define CCU_PLL_DDR0_CTRL_REG   (SUNXI_CCU_BASE + PLL_DDR_CTRL_REG)

◆ CCU_PLL_PERI0_CTRL_REG

#define CCU_PLL_PERI0_CTRL_REG   (SUNXI_CCU_BASE + PLL_PERI_CTRL_REG)

◆ CCU_PLL_VIDEO_CTRL_REG

#define CCU_PLL_VIDEO_CTRL_REG   (SUNXI_CCU_BASE + PLL_VIDEO_CTRL_REG)

◆ CCU_PSI_AHB1_AHB2_CFG_REG

#define CCU_PSI_AHB1_AHB2_CFG_REG   (SUNXI_CCU_BASE + AHB_CLK_REG)

◆ CCU_SDMMC0_CLK_REG

#define CCU_SDMMC0_CLK_REG   (SUNXI_CCU_BASE + SMHC0_CLK_REG)

◆ CCU_SDMMC1_CLK_REG

#define CCU_SDMMC1_CLK_REG   (SUNXI_CCU_BASE + SMHC1_CLK_REG)

◆ CCU_SDMMC2_CLK_REG

#define CCU_SDMMC2_CLK_REG   (SUNXI_CCU_BASE + 0x838)

◆ CCU_SEC_SWITCH_REG

#define CCU_SEC_SWITCH_REG   0x00000f00

◆ CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002

◆ CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0b0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001

◆ CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0b1

◆ CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0b0

◆ CCU_SMHC0_BGR_REG

#define CCU_SMHC0_BGR_REG   (SUNXI_CCU_BASE + SMHC_BGR_REG)

◆ CCU_SPI0_CLK_REG

#define CCU_SPI0_CLK_REG   (SUNXI_CCU_BASE + SPI0_CLK_REG)

◆ CCU_SPI1_CLK_REG

#define CCU_SPI1_CLK_REG   (SUNXI_CCU_BASE + SPI1_CLK_REG)

◆ CCU_SPI_BGR_CLK_REG

#define CCU_SPI_BGR_CLK_REG   (SUNXI_CCU_BASE + SPI_BGR_REG)

◆ CCU_USB0_CLK_REG

#define CCU_USB0_CLK_REG   (SUNXI_CCU_BASE + USB0_CLK_REG)

◆ CCU_USB_BGR_REG

#define CCU_USB_BGR_REG   (SUNXI_CCU_BASE + USB_BGR_REG)

◆ CCU_VERSION_REG

#define CCU_VERSION_REG   0x00000ff0

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16

◆ CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff

◆ CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0

◆ CE_BGR_REG

#define CE_BGR_REG   0x0000068c

◆ CE_BGR_REG_CE_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_GATING_CLEAR_MASK   0x00000001

◆ CE_BGR_REG_CE_GATING_MASK

#define CE_BGR_REG_CE_GATING_MASK   0b0

◆ CE_BGR_REG_CE_GATING_OFFSET

#define CE_BGR_REG_CE_GATING_OFFSET   0

◆ CE_BGR_REG_CE_GATING_PASS

#define CE_BGR_REG_CE_GATING_PASS   0b1

◆ CE_BGR_REG_CE_RST_ASSERT

#define CE_BGR_REG_CE_RST_ASSERT   0b0

◆ CE_BGR_REG_CE_RST_CLEAR_MASK

#define CE_BGR_REG_CE_RST_CLEAR_MASK   0x00010000

◆ CE_BGR_REG_CE_RST_DE_ASSERT

#define CE_BGR_REG_CE_RST_DE_ASSERT   0b1

◆ CE_BGR_REG_CE_RST_OFFSET

#define CE_BGR_REG_CE_RST_OFFSET   16

◆ CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   0x00000002

◆ CE_BGR_REG_CE_SYS_GATING_MASK

#define CE_BGR_REG_CE_SYS_GATING_MASK   0b0

◆ CE_BGR_REG_CE_SYS_GATING_OFFSET

#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1

◆ CE_BGR_REG_CE_SYS_GATING_PASS

#define CE_BGR_REG_CE_SYS_GATING_PASS   0b1

◆ CE_BGR_REG_CE_SYS_RST_ASSERT

#define CE_BGR_REG_CE_SYS_RST_ASSERT   0b0

◆ CE_BGR_REG_CE_SYS_RST_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   0x00020000

◆ CE_BGR_REG_CE_SYS_RST_DE_ASSERT

#define CE_BGR_REG_CE_SYS_RST_DE_ASSERT   0b1

◆ CE_BGR_REG_CE_SYS_RST_OFFSET

#define CE_BGR_REG_CE_SYS_RST_OFFSET   17

◆ CE_CLK_REG

#define CE_CLK_REG   0x00000680

◆ CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK

#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   0x80000000

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON   0b1

◆ CE_CLK_REG_CE_CLK_GATING_OFFSET

#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31

◆ CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CE_CLK_REG_CLK_SRC_SEL_HOSC

#define CE_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ CE_CLK_REG_CLK_SRC_SEL_OFFSET

#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CE_CLK_REG_CLK_SRC_SEL_PERI_300M

#define CE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010

◆ CE_CLK_REG_CLK_SRC_SEL_PERI_400M

#define CE_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ CE_CLK_REG_FACTOR_M_CLEAR_MASK

#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ CE_CLK_REG_FACTOR_M_OFFSET

#define CE_CLK_REG_FACTOR_M_OFFSET   0

◆ CE_USE_PLATFORM_CLOCK_FUNC

#define CE_USE_PLATFORM_CLOCK_FUNC

◆ CLK24M_GATE_EN_REG

#define CLK24M_GATE_EN_REG   0x00000e0c

◆ CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_CLEAR_MASK   0x00000004

◆ CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_DISABLE   0b0

◆ CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_ENABLE   0b1

◆ CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_GPADC_24M_GATE_EN_OFFSET   2

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   0x00000008

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0b0

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0b1

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK   0x00000001

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE   0b0

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE   0b1

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET   0

◆ CLK27M_FAN_REG

#define CLK27M_FAN_REG   0x00000f34

◆ CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f

◆ CLK27M_FAN_REG_CLK27M_DIV0_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0

◆ CLK27M_FAN_REG_CLK27M_DIV1_1

#define CLK27M_FAN_REG_CLK27M_DIV1_1   0b00

◆ CLK27M_FAN_REG_CLK27M_DIV1_2

#define CLK27M_FAN_REG_CLK27M_DIV1_2   0b01

◆ CLK27M_FAN_REG_CLK27M_DIV1_4

#define CLK27M_FAN_REG_CLK27M_DIV1_4   0b10

◆ CLK27M_FAN_REG_CLK27M_DIV1_8

#define CLK27M_FAN_REG_CLK27M_DIV1_8   0b11

◆ CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00000300

◆ CLK27M_FAN_REG_CLK27M_DIV1_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8

◆ CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0b0

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0b1

◆ CLK27M_FAN_REG_CLK27M_EN_OFFSET

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CSIPLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CSIPLL1X   0b001

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_PERI_300M

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_PERI_300M   0b010

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEOPLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEOPLL1X   0b000

◆ CLK_FAN_REG

#define CLK_FAN_REG   0x00000f38

◆ CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0

◆ CLK_FAN_REG_PCLK_DIV1_OFFSET

#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5

◆ CLK_FAN_REG_PCLK_DIV_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f

◆ CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0b0

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0b1

◆ CLK_FAN_REG_PCLK_DIV_EN_OFFSET

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31

◆ CLK_FAN_REG_PCLK_DIV_OFFSET

#define CLK_FAN_REG_PCLK_DIV_OFFSET   0

◆ CPU_CFG_BGR_REG

#define CPU_CFG_BGR_REG   0x0000050c

◆ CPU_CFG_BGR_REG_CPU_CFG_GATING_CLEAR_MASK

#define CPU_CFG_BGR_REG_CPU_CFG_GATING_CLEAR_MASK   0x00000001

◆ CPU_CFG_BGR_REG_CPU_CFG_GATING_MASK

#define CPU_CFG_BGR_REG_CPU_CFG_GATING_MASK   0b0

◆ CPU_CFG_BGR_REG_CPU_CFG_GATING_OFFSET

#define CPU_CFG_BGR_REG_CPU_CFG_GATING_OFFSET   0

◆ CPU_CFG_BGR_REG_CPU_CFG_GATING_PASS

#define CPU_CFG_BGR_REG_CPU_CFG_GATING_PASS   0b1

◆ CPU_CFG_BGR_REG_CPU_CFG_RST_ASSERT

#define CPU_CFG_BGR_REG_CPU_CFG_RST_ASSERT   0b0

◆ CPU_CFG_BGR_REG_CPU_CFG_RST_CLEAR_MASK

#define CPU_CFG_BGR_REG_CPU_CFG_RST_CLEAR_MASK   0x00010000

◆ CPU_CFG_BGR_REG_CPU_CFG_RST_DE_ASSERT

#define CPU_CFG_BGR_REG_CPU_CFG_RST_DE_ASSERT   0b1

◆ CPU_CFG_BGR_REG_CPU_CFG_RST_OFFSET

#define CPU_CFG_BGR_REG_CPU_CFG_RST_OFFSET   16

◆ CPU_CLK_REG

#define CPU_CLK_REG   0x00000500

◆ CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK

#define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK   0x00000300

◆ CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET

#define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET   8

◆ CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK

#define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK   0x07000000

◆ CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC

#define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC   0b010

◆ CPU_CLK_REG_CPU_CLK_SEL_CLK32K

#define CPU_CLK_REG_CPU_CLK_SEL_CLK32K   0b001

◆ CPU_CLK_REG_CPU_CLK_SEL_CPUPLL_P

#define CPU_CLK_REG_CPU_CLK_SEL_CPUPLL_P   0b011

◆ CPU_CLK_REG_CPU_CLK_SEL_HOSC

#define CPU_CLK_REG_CPU_CLK_SEL_HOSC   0b000

◆ CPU_CLK_REG_CPU_CLK_SEL_OFFSET

#define CPU_CLK_REG_CPU_CLK_SEL_OFFSET   24

◆ CPU_CLK_REG_CPU_CLK_SEL_PERI_600M_BUS

#define CPU_CLK_REG_CPU_CLK_SEL_PERI_600M_BUS   0b100

◆ CPU_CLK_REG_CPU_CLK_SEL_PERI_800M

#define CPU_CLK_REG_CPU_CLK_SEL_PERI_800M   0b101

◆ CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_1

#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_1   0b00

◆ CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_2

#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_2   0b01

◆ CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_4

#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_4   0b10

◆ CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_CLEAR_MASK

#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_CLEAR_MASK   0x00030000

◆ CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_OFFSET

#define CPU_CLK_REG_PLL_CPU_OUT_EXT_DIVP_OFFSET   16

◆ CPU_GATING_REG

#define CPU_GATING_REG   0x00000504

◆ CPU_GATING_REG_C0_CPUX_RESET_ASSERT

#define CPU_GATING_REG_C0_CPUX_RESET_ASSERT   0b0

◆ CPU_GATING_REG_C0_CPUX_RESET_CLEAR_MASK

#define CPU_GATING_REG_C0_CPUX_RESET_CLEAR_MASK   0x00000010

◆ CPU_GATING_REG_C0_CPUX_RESET_DE_ASSERT

#define CPU_GATING_REG_C0_CPUX_RESET_DE_ASSERT   0b1

◆ CPU_GATING_REG_C0_CPUX_RESET_OFFSET

#define CPU_GATING_REG_C0_CPUX_RESET_OFFSET   4

◆ CPU_GATING_REG_C1_CPUX_RESET_ASSERT

#define CPU_GATING_REG_C1_CPUX_RESET_ASSERT   0b0

◆ CPU_GATING_REG_C1_CPUX_RESET_CLEAR_MASK

#define CPU_GATING_REG_C1_CPUX_RESET_CLEAR_MASK   0x00000020

◆ CPU_GATING_REG_C1_CPUX_RESET_DE_ASSERT

#define CPU_GATING_REG_C1_CPUX_RESET_DE_ASSERT   0b1

◆ CPU_GATING_REG_C1_CPUX_RESET_OFFSET

#define CPU_GATING_REG_C1_CPUX_RESET_OFFSET   5

◆ CPU_GATING_REG_CPU_CLK_GATING_CLEAR_MASK

#define CPU_GATING_REG_CPU_CLK_GATING_CLEAR_MASK   0x00000001

◆ CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_OFF

#define CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_ON

#define CPU_GATING_REG_CPU_CLK_GATING_CLOCK_IS_ON   0b1

◆ CPU_GATING_REG_CPU_CLK_GATING_OFFSET

#define CPU_GATING_REG_CPU_CLK_GATING_OFFSET   0

◆ CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK

#define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK   0xffff0000

◆ CPU_GATING_REG_CPU_GATING_FIELD_OFFSET

#define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET   16

◆ CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_ASSERT

#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_ASSERT   0b0

◆ CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_CLEAR_MASK

#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_CLEAR_MASK   0x00001000

◆ CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_DE_ASSERT

#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_DE_ASSERT   0b1

◆ CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_OFFSET

#define CPU_GATING_REG_CPU_IPMC_SOFT_RSTN_OFFSET   12

◆ CPU_GATING_REG_CPU_SOFT_RSTN_ASSERT

#define CPU_GATING_REG_CPU_SOFT_RSTN_ASSERT   0b0

◆ CPU_GATING_REG_CPU_SOFT_RSTN_CLEAR_MASK

#define CPU_GATING_REG_CPU_SOFT_RSTN_CLEAR_MASK   0x00000002

◆ CPU_GATING_REG_CPU_SOFT_RSTN_DE_ASSERT

#define CPU_GATING_REG_CPU_SOFT_RSTN_DE_ASSERT   0b1

◆ CPU_GATING_REG_CPU_SOFT_RSTN_OFFSET

#define CPU_GATING_REG_CPU_SOFT_RSTN_OFFSET   1

◆ CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_ASSERT

#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_ASSERT   0b0

◆ CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_CLEAR_MASK

#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_CLEAR_MASK   0x00000004

◆ CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_DE_ASSERT

#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_DE_ASSERT   0b1

◆ CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_OFFSET

#define CPU_GATING_REG_CPU_SYS_APB_SOFT_RSTN_OFFSET   2

◆ CPU_GATING_REG_H_RESET_CLEAR_MASK

#define CPU_GATING_REG_H_RESET_CLEAR_MASK   0x00000100

◆ CPU_GATING_REG_H_RESET_OFFSET

#define CPU_GATING_REG_H_RESET_OFFSET   8

◆ CPU_GATING_REG_PIC_SOFT_RSTN_ASSERT

#define CPU_GATING_REG_PIC_SOFT_RSTN_ASSERT   0b0

◆ CPU_GATING_REG_PIC_SOFT_RSTN_CLEAR_MASK

#define CPU_GATING_REG_PIC_SOFT_RSTN_CLEAR_MASK   0x00000008

◆ CPU_GATING_REG_PIC_SOFT_RSTN_DE_ASSERT

#define CPU_GATING_REG_PIC_SOFT_RSTN_DE_ASSERT   0b1

◆ CPU_GATING_REG_PIC_SOFT_RSTN_OFFSET

#define CPU_GATING_REG_PIC_SOFT_RSTN_OFFSET   3

◆ CPUPLL_GATE_EN_REG

#define CPUPLL_GATE_EN_REG   0x00000e24

◆ CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_AUTO

#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_AUTO   0b0

◆ CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_CLEAR_MASK

#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_NO_AUTO

#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_OFFSET

#define CPUPLL_GATE_EN_REG_CPUPLL_AUTO_GATE_EN_OFFSET   0

◆ CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_CLEAR_MASK

#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_DISABLE

#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_DISABLE   0b0

◆ CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_ENABLE

#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_ENABLE   0b1

◆ CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_OFFSET

#define CPUPLL_GATE_EN_REG_CPUPLL_GATE_SW_CFG_OFFSET   16

◆ CPUPLL_GATE_STAT_REG

#define CPUPLL_GATE_STAT_REG   0x00000e3c

◆ CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_CLEAR_MASK

#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_CLEAR_MASK   0x00010000

◆ CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_DISABLE

#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_DISABLE   0b0

◆ CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_ENABLE

#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_ENABLE   0b1

◆ CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_OFFSET

#define CPUPLL_GATE_STAT_REG_CPUPLL_GATE_STAT_OFFSET   16

◆ CSI_BGR_REG

#define CSI_BGR_REG   0x00000c2c

◆ CSI_BGR_REG_CSI_GATING_CLEAR_MASK

#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   0x00000001

◆ CSI_BGR_REG_CSI_GATING_MASK

#define CSI_BGR_REG_CSI_GATING_MASK   0b0

◆ CSI_BGR_REG_CSI_GATING_OFFSET

#define CSI_BGR_REG_CSI_GATING_OFFSET   0

◆ CSI_BGR_REG_CSI_GATING_PASS

#define CSI_BGR_REG_CSI_GATING_PASS   0b1

◆ CSI_BGR_REG_CSI_RST_ASSERT

#define CSI_BGR_REG_CSI_RST_ASSERT   0b0

◆ CSI_BGR_REG_CSI_RST_CLEAR_MASK

#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   0x00010000

◆ CSI_BGR_REG_CSI_RST_DE_ASSERT

#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0b1

◆ CSI_BGR_REG_CSI_RST_OFFSET

#define CSI_BGR_REG_CSI_RST_OFFSET   16

◆ CSI_CLK_REG

#define CSI_CLK_REG   0x00000c04

◆ CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b011

◆ CSI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI_300M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI_300M   0b000

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI_400M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010

◆ CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_CLK_REG_CSI_CLK_GATING_OFFSET

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31

◆ CSI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_CLK_REG_FACTOR_M_OFFSET

#define CSI_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG

#define CSI_MASTER0_CLK_REG   0x00000c08

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_PERIPLL2X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31

◆ CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG_FACTOR_N_1

#define CSI_MASTER0_CLK_REG_FACTOR_N_1   0b00

◆ CSI_MASTER0_CLK_REG_FACTOR_N_2

#define CSI_MASTER0_CLK_REG_FACTOR_N_2   0b01

◆ CSI_MASTER0_CLK_REG_FACTOR_N_4

#define CSI_MASTER0_CLK_REG_FACTOR_N_4   0b10

◆ CSI_MASTER0_CLK_REG_FACTOR_N_8

#define CSI_MASTER0_CLK_REG_FACTOR_N_8   0b11

◆ CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER1_CLK_REG

#define CSI_MASTER1_CLK_REG   0x00000c0c

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_PERIPLL2X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31

◆ CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER1_CLK_REG_FACTOR_N_1

#define CSI_MASTER1_CLK_REG_FACTOR_N_1   0b00

◆ CSI_MASTER1_CLK_REG_FACTOR_N_2

#define CSI_MASTER1_CLK_REG_FACTOR_N_2   0b01

◆ CSI_MASTER1_CLK_REG_FACTOR_N_4

#define CSI_MASTER1_CLK_REG_FACTOR_N_4   0b10

◆ CSI_MASTER1_CLK_REG_FACTOR_N_8

#define CSI_MASTER1_CLK_REG_FACTOR_N_8   0b11

◆ CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER2_CLK_REG

#define CSI_MASTER2_CLK_REG   0x00000c10

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b001

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_PERIPLL2X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b011

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b010

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0b1

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31

◆ CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER2_CLK_REG_FACTOR_N_1

#define CSI_MASTER2_CLK_REG_FACTOR_N_1   0b00

◆ CSI_MASTER2_CLK_REG_FACTOR_N_2

#define CSI_MASTER2_CLK_REG_FACTOR_N_2   0b01

◆ CSI_MASTER2_CLK_REG_FACTOR_N_4

#define CSI_MASTER2_CLK_REG_FACTOR_N_4   0b10

◆ CSI_MASTER2_CLK_REG_FACTOR_N_8

#define CSI_MASTER2_CLK_REG_FACTOR_N_8   0b11

◆ CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8

◆ CSIPLL_GATE_EN_REG

#define CSIPLL_GATE_EN_REG   0x00000e1c

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_AUTO   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_NO_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_NO_AUTO   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL1X_AUTO_GATE_EN_OFFSET   0

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_DISABLE

#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_DISABLE   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_ENABLE

#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_ENABLE   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL1X_GATE_SW_CFG_OFFSET   16

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_AUTO   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_NO_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL2X_AUTO_GATE_EN_OFFSET   1

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_DISABLE

#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_DISABLE   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_ENABLE

#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_ENABLE   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL2X_GATE_SW_CFG_OFFSET   17

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_AUTO   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_NO_AUTO

#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL4X_AUTO_GATE_EN_OFFSET   2

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_CLEAR_MASK

#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_DISABLE

#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_DISABLE   0b0

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_ENABLE

#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_ENABLE   0b1

◆ CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_OFFSET

#define CSIPLL_GATE_EN_REG_CSIPLL4X_GATE_SW_CFG_OFFSET   18

◆ CSIPLL_GATE_STAT_REG

#define CSIPLL_GATE_STAT_REG   0x00000e34

◆ CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_CLEAR_MASK

#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_CLEAR_MASK   0x00010000

◆ CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_DISABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_DISABLE   0b0

◆ CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_ENABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_ENABLE   0b1

◆ CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_OFFSET

#define CSIPLL_GATE_STAT_REG_CSIPLL1X_GATE_STAT_OFFSET   16

◆ CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_CLEAR_MASK

#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_CLEAR_MASK   0x00020000

◆ CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_DISABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_DISABLE   0b0

◆ CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_ENABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_ENABLE   0b1

◆ CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_OFFSET

#define CSIPLL_GATE_STAT_REG_CSIPLL2X_GATE_STAT_OFFSET   17

◆ CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_CLEAR_MASK

#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_CLEAR_MASK   0x00040000

◆ CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_DISABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_DISABLE   0b0

◆ CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_ENABLE

#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_ENABLE   0b1

◆ CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_OFFSET

#define CSIPLL_GATE_STAT_REG_CSIPLL4X_GATE_STAT_OFFSET   18

◆ DBGSYS_BGR_REG

#define DBGSYS_BGR_REG   0x0000078c

◆ DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   0x00000001

◆ DBGSYS_BGR_REG_DBGSYS_GATING_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0b0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_PASS

#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0b0

◆ DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   0x00010000

◆ DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0b1

◆ DBGSYS_BGR_REG_DBGSYS_RST_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16

◆ DDRPLL_GATE_EN_REG

#define DDRPLL_GATE_EN_REG   0x00000e20

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO   0b0

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO   0b1

◆ DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET

#define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET   0

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE   0b0

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE   0b1

◆ DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET

#define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET   16

◆ DDRPLL_GATE_STAT_REG

#define DDRPLL_GATE_STAT_REG   0x00000e38

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK   0x00010000

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE   0b0

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE   0b1

◆ DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET

#define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET   16

◆ DE_BGR_REG

#define DE_BGR_REG   0x0000060c

◆ DE_BGR_REG_DE_GATING_CLEAR_MASK

#define DE_BGR_REG_DE_GATING_CLEAR_MASK   0x00000001

◆ DE_BGR_REG_DE_GATING_MASK

#define DE_BGR_REG_DE_GATING_MASK   0b0

◆ DE_BGR_REG_DE_GATING_OFFSET

#define DE_BGR_REG_DE_GATING_OFFSET   0

◆ DE_BGR_REG_DE_GATING_PASS

#define DE_BGR_REG_DE_GATING_PASS   0b1

◆ DE_BGR_REG_DE_RST_ASSERT

#define DE_BGR_REG_DE_RST_ASSERT   0b0

◆ DE_BGR_REG_DE_RST_CLEAR_MASK

#define DE_BGR_REG_DE_RST_CLEAR_MASK   0x00010000

◆ DE_BGR_REG_DE_RST_DE_ASSERT

#define DE_BGR_REG_DE_RST_DE_ASSERT   0b1

◆ DE_BGR_REG_DE_RST_OFFSET

#define DE_BGR_REG_DE_RST_OFFSET   16

◆ DE_CLK_REG

#define DE_CLK_REG   0x00000600

◆ DE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ DE_CLK_REG_CLK_SRC_SEL_OFFSET

#define DE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DE_CLK_REG_CLK_SRC_SEL_PERI_300M

#define DE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b0

◆ DE_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X

#define DE_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X   0b1

◆ DE_CLK_REG_DE_CLK_GATING_CLEAR_MASK

#define DE_CLK_REG_DE_CLK_GATING_CLEAR_MASK   0x80000000

◆ DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF

#define DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON

#define DE_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON   0b1

◆ DE_CLK_REG_DE_CLK_GATING_OFFSET

#define DE_CLK_REG_DE_CLK_GATING_OFFSET   31

◆ DE_CLK_REG_FACTOR_M_CLEAR_MASK

#define DE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DE_CLK_REG_FACTOR_M_OFFSET

#define DE_CLK_REG_FACTOR_M_OFFSET   0

◆ DMA_BGR_REG

#define DMA_BGR_REG   0x0000070c

◆ DMA_BGR_REG_NDMA_GATING_CLEAR_MASK

#define DMA_BGR_REG_NDMA_GATING_CLEAR_MASK   0x00000002

◆ DMA_BGR_REG_NDMA_GATING_MASK

#define DMA_BGR_REG_NDMA_GATING_MASK   0b0

◆ DMA_BGR_REG_NDMA_GATING_OFFSET

#define DMA_BGR_REG_NDMA_GATING_OFFSET   1

◆ DMA_BGR_REG_NDMA_GATING_PASS

#define DMA_BGR_REG_NDMA_GATING_PASS   0b1

◆ DMA_BGR_REG_NDMA_RST_ASSERT

#define DMA_BGR_REG_NDMA_RST_ASSERT   0b0

◆ DMA_BGR_REG_NDMA_RST_CLEAR_MASK

#define DMA_BGR_REG_NDMA_RST_CLEAR_MASK   0x00020000

◆ DMA_BGR_REG_NDMA_RST_DE_ASSERT

#define DMA_BGR_REG_NDMA_RST_DE_ASSERT   0b1

◆ DMA_BGR_REG_NDMA_RST_OFFSET

#define DMA_BGR_REG_NDMA_RST_OFFSET   17

◆ DMA_BGR_REG_SGDMA_GATING_CLEAR_MASK

#define DMA_BGR_REG_SGDMA_GATING_CLEAR_MASK   0x00000001

◆ DMA_BGR_REG_SGDMA_GATING_MASK

#define DMA_BGR_REG_SGDMA_GATING_MASK   0b0

◆ DMA_BGR_REG_SGDMA_GATING_OFFSET

#define DMA_BGR_REG_SGDMA_GATING_OFFSET   0

◆ DMA_BGR_REG_SGDMA_GATING_PASS

#define DMA_BGR_REG_SGDMA_GATING_PASS   0b1

◆ DMA_BGR_REG_SGDMA_RST_ASSERT

#define DMA_BGR_REG_SGDMA_RST_ASSERT   0b0

◆ DMA_BGR_REG_SGDMA_RST_CLEAR_MASK

#define DMA_BGR_REG_SGDMA_RST_CLEAR_MASK   0x00010000

◆ DMA_BGR_REG_SGDMA_RST_DE_ASSERT

#define DMA_BGR_REG_SGDMA_RST_DE_ASSERT   0b1

◆ DMA_BGR_REG_SGDMA_RST_OFFSET

#define DMA_BGR_REG_SGDMA_RST_OFFSET   16

◆ DMA_GATING_BASE

#define DMA_GATING_BASE   CCU_DMA_BGR_REG

◆ DPSS_TOP_BGR_REG

#define DPSS_TOP_BGR_REG   0x00000abc

◆ DPSS_TOP_BGR_REG_DPSS_TOP_GATING_CLEAR_MASK

#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_CLEAR_MASK   0x00000001

◆ DPSS_TOP_BGR_REG_DPSS_TOP_GATING_MASK

#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_MASK   0b0

◆ DPSS_TOP_BGR_REG_DPSS_TOP_GATING_OFFSET

#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_OFFSET   0

◆ DPSS_TOP_BGR_REG_DPSS_TOP_GATING_PASS

#define DPSS_TOP_BGR_REG_DPSS_TOP_GATING_PASS   0b1

◆ DPSS_TOP_BGR_REG_DPSS_TOP_RST_ASSERT

#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_ASSERT   0b0

◆ DPSS_TOP_BGR_REG_DPSS_TOP_RST_CLEAR_MASK

#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_CLEAR_MASK   0x00010000

◆ DPSS_TOP_BGR_REG_DPSS_TOP_RST_DE_ASSERT

#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_DE_ASSERT   0b1

◆ DPSS_TOP_BGR_REG_DPSS_TOP_RST_OFFSET

#define DPSS_TOP_BGR_REG_DPSS_TOP_RST_OFFSET   16

◆ DRAM_BGR_REG

#define DRAM_BGR_REG   0x0000080c

◆ DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK   0x00000001

◆ DRAM_BGR_REG_DRAM_GATING_MASK

#define DRAM_BGR_REG_DRAM_GATING_MASK   0b0

◆ DRAM_BGR_REG_DRAM_GATING_OFFSET

#define DRAM_BGR_REG_DRAM_GATING_OFFSET   0

◆ DRAM_BGR_REG_DRAM_GATING_PASS

#define DRAM_BGR_REG_DRAM_GATING_PASS   0b1

◆ DRAM_BGR_REG_DRAM_RST_ASSERT

#define DRAM_BGR_REG_DRAM_RST_ASSERT   0b0

◆ DRAM_BGR_REG_DRAM_RST_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK   0x00010000

◆ DRAM_BGR_REG_DRAM_RST_DE_ASSERT

#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT   0b1

◆ DRAM_BGR_REG_DRAM_RST_OFFSET

#define DRAM_BGR_REG_DRAM_RST_OFFSET   16

◆ DRAM_CLK_REG

#define DRAM_CLK_REG   0x00000800

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK   0x80000000

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF   0b0

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON   0b1

◆ DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET   31

◆ DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK   0x07000000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL

#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL   0b001

◆ DRAM_CLK_REG_DRAM_CLK_SEL_HOSC

#define DRAM_CLK_REG_DRAM_CLK_SEL_HOSC   0b000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET   24

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI_800M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI_800M   0b011

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERIPLL2X

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERIPLL2X   0b010

◆ DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK   0x0000001f

◆ DRAM_CLK_REG_DRAM_DIV1_OFFSET

#define DRAM_CLK_REG_DRAM_DIV1_OFFSET   0

◆ DRAM_CLK_REG_DRAM_DIV2_1

#define DRAM_CLK_REG_DRAM_DIV2_1   0b00

◆ DRAM_CLK_REG_DRAM_DIV2_2

#define DRAM_CLK_REG_DRAM_DIV2_2   0b01

◆ DRAM_CLK_REG_DRAM_DIV2_4

#define DRAM_CLK_REG_DRAM_DIV2_4   0b10

◆ DRAM_CLK_REG_DRAM_DIV2_8

#define DRAM_CLK_REG_DRAM_DIV2_8   0b11

◆ DRAM_CLK_REG_DRAM_DIV2_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_DIV2_CLEAR_MASK   0x00000300

◆ DRAM_CLK_REG_DRAM_DIV2_OFFSET

#define DRAM_CLK_REG_DRAM_DIV2_OFFSET   8

◆ DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK   0x08000000

◆ DRAM_CLK_REG_DRAM_UPD_INVALID

#define DRAM_CLK_REG_DRAM_UPD_INVALID   0b0

◆ DRAM_CLK_REG_DRAM_UPD_OFFSET

#define DRAM_CLK_REG_DRAM_UPD_OFFSET   27

◆ DRAM_CLK_REG_DRAM_UPD_VALID

#define DRAM_CLK_REG_DRAM_UPD_VALID   0b1

◆ E907_CFG_BASE

#define E907_CFG_BASE   (0x06010000)

◆ E907_CFG_GATING_BIT

#define E907_CFG_GATING_BIT   (0)

◆ E907_CFG_GATING_RESET_BASE

#define E907_CFG_GATING_RESET_BASE   (SUNXI_CCU_BASE + 0xd0c)

◆ E907_CFG_RST_BIT

#define E907_CFG_RST_BIT   (16)

◆ E907_CLK_GATING_BIT

#define E907_CLK_GATING_BIT   (0)

◆ E907_CLK_REG

#define E907_CLK_REG   0x00000d00

◆ E907_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK

#define E907_CLK_REG_E907_AXI_DIV_CFG_CLEAR_MASK   0x00000300

◆ E907_CLK_REG_E907_AXI_DIV_CFG_OFFSET

#define E907_CLK_REG_E907_AXI_DIV_CFG_OFFSET   8

◆ E907_CLK_REG_E907_CLK_SEL_CLEAR_MASK

#define E907_CLK_REG_E907_CLK_SEL_CLEAR_MASK   0x07000000

◆ E907_CLK_REG_E907_CLK_SEL_CLK16M_RC

#define E907_CLK_REG_E907_CLK_SEL_CLK16M_RC   0b010

◆ E907_CLK_REG_E907_CLK_SEL_CLK32K

#define E907_CLK_REG_E907_CLK_SEL_CLK32K   0b001

◆ E907_CLK_REG_E907_CLK_SEL_CPUPLL

#define E907_CLK_REG_E907_CLK_SEL_CPUPLL   0b101

◆ E907_CLK_REG_E907_CLK_SEL_HOSC

#define E907_CLK_REG_E907_CLK_SEL_HOSC   0b000

◆ E907_CLK_REG_E907_CLK_SEL_OFFSET

#define E907_CLK_REG_E907_CLK_SEL_OFFSET   24

◆ E907_CLK_REG_E907_CLK_SEL_PERI_600M

#define E907_CLK_REG_E907_CLK_SEL_PERI_600M   0b011

◆ E907_CLK_REG_E907_CLK_SEL_PERI_800M

#define E907_CLK_REG_E907_CLK_SEL_PERI_800M   0b100

◆ E907_CLK_REG_E907_DIV_CFG_CLEAR_MASK

#define E907_CLK_REG_E907_DIV_CFG_CLEAR_MASK   0x0000001f

◆ E907_CLK_REG_E907_DIV_CFG_OFFSET

#define E907_CLK_REG_E907_DIV_CFG_OFFSET   0

◆ E907_GATING_RST_FIELD

#define E907_GATING_RST_FIELD   (0x16aa)

◆ E907_GATING_RST_REG

#define E907_GATING_RST_REG   0x00000d04

◆ E907_GATING_RST_REG_E907_CLK_GATING_CLEAR_MASK

#define E907_GATING_RST_REG_E907_CLK_GATING_CLEAR_MASK   0x00000001

◆ E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_OFF

#define E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_OFF   0b0

◆ E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_ON

#define E907_GATING_RST_REG_E907_CLK_GATING_CLOCK_IS_ON   0b1

◆ E907_GATING_RST_REG_E907_CLK_GATING_OFFSET

#define E907_GATING_RST_REG_E907_CLK_GATING_OFFSET   0

◆ E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_ASSERT

#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_ASSERT   0b0

◆ E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_CLEAR_MASK

#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_CLEAR_MASK   0x00000008

◆ E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_DE_ASSERT

#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_DE_ASSERT   0b1

◆ E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_OFFSET

#define E907_GATING_RST_REG_E907_CORE_SOFT_RSTN_OFFSET   3

◆ E907_GATING_RST_REG_E907_GATING_RST_FIELD_CLEAR_MASK

#define E907_GATING_RST_REG_E907_GATING_RST_FIELD_CLEAR_MASK   0xffff0000

◆ E907_GATING_RST_REG_E907_GATING_RST_FIELD_OFFSET

#define E907_GATING_RST_REG_E907_GATING_RST_FIELD_OFFSET   16

◆ E907_GATING_RST_REG_E907_SOFT_RSTN_ASSERT

#define E907_GATING_RST_REG_E907_SOFT_RSTN_ASSERT   0b0

◆ E907_GATING_RST_REG_E907_SOFT_RSTN_CLEAR_MASK

#define E907_GATING_RST_REG_E907_SOFT_RSTN_CLEAR_MASK   0x00000002

◆ E907_GATING_RST_REG_E907_SOFT_RSTN_DE_ASSERT

#define E907_GATING_RST_REG_E907_SOFT_RSTN_DE_ASSERT   0b1

◆ E907_GATING_RST_REG_E907_SOFT_RSTN_OFFSET

#define E907_GATING_RST_REG_E907_SOFT_RSTN_OFFSET   1

◆ E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_ASSERT

#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_ASSERT   0b0

◆ E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_CLEAR_MASK

#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_CLEAR_MASK   0x00000004

◆ E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_DE_ASSERT

#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_DE_ASSERT   0b1

◆ E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_OFFSET

#define E907_GATING_RST_REG_RISCV_SYS_APB_SOFT_RSTN_OFFSET   2

◆ E907_SOFT_RST_BIT

#define E907_SOFT_RST_BIT   (1)

◆ E907_STA_ADD_REG

#define E907_STA_ADD_REG   (E907_CFG_BASE + 0x0204)

◆ E907_SYS_APB_SOFT_RST_BIT

#define E907_SYS_APB_SOFT_RST_BIT   (2)

◆ E907_SYS_GATING_RESET_BASE

#define E907_SYS_GATING_RESET_BASE   (SUNXI_CCU_BASE + 0xd04)

◆ FRE_DET_CTRL_REG

#define FRE_DET_CTRL_REG   0x00000f08

◆ FRE_DET_CTRL_REG_DET_TIME_CLEAR_MASK

#define FRE_DET_CTRL_REG_DET_TIME_CLEAR_MASK   0x000001f0

◆ FRE_DET_CTRL_REG_DET_TIME_OFFSET

#define FRE_DET_CTRL_REG_DET_TIME_OFFSET   4

◆ FRE_DET_CTRL_REG_ERROR_FLAG_CLEAR_MASK

#define FRE_DET_CTRL_REG_ERROR_FLAG_CLEAR_MASK   0x80000000

◆ FRE_DET_CTRL_REG_ERROR_FLAG_ERROR

#define FRE_DET_CTRL_REG_ERROR_FLAG_ERROR   0b1

◆ FRE_DET_CTRL_REG_ERROR_FLAG_OFFSET

#define FRE_DET_CTRL_REG_ERROR_FLAG_OFFSET   31

◆ FRE_DET_CTRL_REG_ERROR_FLAG_WRITE_0_TO_CLEAR

#define FRE_DET_CTRL_REG_ERROR_FLAG_WRITE_0_TO_CLEAR   0b0

◆ FRE_DET_CTRL_REG_FRE_DET_FUN_EN_CLEAR_MASK

#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_CLEAR_MASK   0x00000001

◆ FRE_DET_CTRL_REG_FRE_DET_FUN_EN_DISABLE

#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_DISABLE   0b0

◆ FRE_DET_CTRL_REG_FRE_DET_FUN_EN_ENABLE

#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_ENABLE   0b1

◆ FRE_DET_CTRL_REG_FRE_DET_FUN_EN_OFFSET

#define FRE_DET_CTRL_REG_FRE_DET_FUN_EN_OFFSET   0

◆ FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_CLEAR_MASK

#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_CLEAR_MASK   0x00000002

◆ FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_DISABLE

#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_DISABLE   0b0

◆ FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_ENABLE

#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_ENABLE   0b1

◆ FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_OFFSET

#define FRE_DET_CTRL_REG_FRE_DET_IRQ_EN_OFFSET   1

◆ FRE_DOWN_LIM_REG

#define FRE_DOWN_LIM_REG   0x00000f10

◆ FRE_DOWN_LIM_REG_FRE_DOWN_LIM_CLEAR_MASK

#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_CLEAR_MASK   0xffffffff

◆ FRE_DOWN_LIM_REG_FRE_DOWN_LIM_OFFSET

#define FRE_DOWN_LIM_REG_FRE_DOWN_LIM_OFFSET   0

◆ FRE_UP_LIM_REG

#define FRE_UP_LIM_REG   0x00000f0c

◆ FRE_UP_LIM_REG_FRE_UP_LIM_CLEAR_MASK

#define FRE_UP_LIM_REG_FRE_UP_LIM_CLEAR_MASK   0xffffffff

◆ FRE_UP_LIM_REG_FRE_UP_LIM_OFFSET

#define FRE_UP_LIM_REG_FRE_UP_LIM_OFFSET   0

◆ G2D_BGR_REG

#define G2D_BGR_REG   0x0000063c

◆ G2D_BGR_REG_G2D_GATING_CLEAR_MASK

#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   0x00000001

◆ G2D_BGR_REG_G2D_GATING_MASK

#define G2D_BGR_REG_G2D_GATING_MASK   0b0

◆ G2D_BGR_REG_G2D_GATING_OFFSET

#define G2D_BGR_REG_G2D_GATING_OFFSET   0

◆ G2D_BGR_REG_G2D_GATING_PASS

#define G2D_BGR_REG_G2D_GATING_PASS   0b1

◆ G2D_BGR_REG_G2D_RST_ASSERT

#define G2D_BGR_REG_G2D_RST_ASSERT   0b0

◆ G2D_BGR_REG_G2D_RST_CLEAR_MASK

#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   0x00010000

◆ G2D_BGR_REG_G2D_RST_DE_ASSERT

#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0b1

◆ G2D_BGR_REG_G2D_RST_OFFSET

#define G2D_BGR_REG_G2D_RST_OFFSET   16

◆ G2D_CLK_REG

#define G2D_CLK_REG   0x00000630

◆ G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ G2D_CLK_REG_CLK_SRC_SEL_OFFSET

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI_300M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI_300M   0b0

◆ G2D_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEOPLL1X   0b1

◆ G2D_CLK_REG_FACTOR_M_CLEAR_MASK

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ G2D_CLK_REG_FACTOR_M_OFFSET

#define G2D_CLK_REG_FACTOR_M_OFFSET   0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0b0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0b1

◆ G2D_CLK_REG_G2D_CLK_GATING_OFFSET

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31

◆ GET_SPIF_CLK_SOURECS

#define GET_SPIF_CLK_SOURECS (   x)    (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)

◆ GMAC_25M_CLK_REG

#define GMAC_25M_CLK_REG   0x00000970

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLEAR_MASK

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLEAR_MASK   0x80000000

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_OFF

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_OFF   0b0

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_ON

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_CLOCK_IS_ON   0b1

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_OFFSET

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_GATING_OFFSET   31

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLEAR_MASK

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_OFF

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0b0

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_ON

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_CLOCK_IS_ON   0b1

◆ GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_OFFSET

#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SRC_GATING_OFFSET   30

◆ GMAC_BGR_REG

#define GMAC_BGR_REG   0x0000097c

◆ GMAC_BGR_REG_GMAC_GATING_CLEAR_MASK

#define GMAC_BGR_REG_GMAC_GATING_CLEAR_MASK   0x00000001

◆ GMAC_BGR_REG_GMAC_GATING_MASK

#define GMAC_BGR_REG_GMAC_GATING_MASK   0b0

◆ GMAC_BGR_REG_GMAC_GATING_OFFSET

#define GMAC_BGR_REG_GMAC_GATING_OFFSET   0

◆ GMAC_BGR_REG_GMAC_GATING_PASS

#define GMAC_BGR_REG_GMAC_GATING_PASS   0b1

◆ GMAC_BGR_REG_GMAC_RST_ASSERT

#define GMAC_BGR_REG_GMAC_RST_ASSERT   0b0

◆ GMAC_BGR_REG_GMAC_RST_CLEAR_MASK

#define GMAC_BGR_REG_GMAC_RST_CLEAR_MASK   0x00010000

◆ GMAC_BGR_REG_GMAC_RST_DE_ASSERT

#define GMAC_BGR_REG_GMAC_RST_DE_ASSERT   0b1

◆ GMAC_BGR_REG_GMAC_RST_OFFSET

#define GMAC_BGR_REG_GMAC_RST_OFFSET   16

◆ GPADC_BGR_REG

#define GPADC_BGR_REG   0x000009ec

◆ GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK

#define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK   0x00000001

◆ GPADC_BGR_REG_GPADC_GATING_MASK

#define GPADC_BGR_REG_GPADC_GATING_MASK   0b0

◆ GPADC_BGR_REG_GPADC_GATING_OFFSET

#define GPADC_BGR_REG_GPADC_GATING_OFFSET   0

◆ GPADC_BGR_REG_GPADC_GATING_PASS

#define GPADC_BGR_REG_GPADC_GATING_PASS   0b1

◆ GPADC_BGR_REG_GPADC_RST_ASSERT

#define GPADC_BGR_REG_GPADC_RST_ASSERT   0b0

◆ GPADC_BGR_REG_GPADC_RST_CLEAR_MASK

#define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK   0x00010000

◆ GPADC_BGR_REG_GPADC_RST_DE_ASSERT

#define GPADC_BGR_REG_GPADC_RST_DE_ASSERT   0b1

◆ GPADC_BGR_REG_GPADC_RST_OFFSET

#define GPADC_BGR_REG_GPADC_RST_OFFSET   16

◆ GPADC_CLK_SEL_REG

#define GPADC_CLK_SEL_REG   0x00000f04

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_CLEAR_MASK

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_CLEAR_MASK   0x00700000

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC   0b101

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_16

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_16   0b001

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_2

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_2   0b100

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_32

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_32   0b000

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_4

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_4   0b011

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_8

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_HOSC_8   0b010

◆ GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_OFFSET

#define GPADC_CLK_SEL_REG_GPADC_24M_CLK_SEL_OFFSET   20

◆ HSTIMER_BGR_REG

#define HSTIMER_BGR_REG   0x0000073c

◆ HSTIMER_BGR_REG_HSTIMER_GATING_CLEAR_MASK

#define HSTIMER_BGR_REG_HSTIMER_GATING_CLEAR_MASK   0x00000001

◆ HSTIMER_BGR_REG_HSTIMER_GATING_MASK

#define HSTIMER_BGR_REG_HSTIMER_GATING_MASK   0b0

◆ HSTIMER_BGR_REG_HSTIMER_GATING_OFFSET

#define HSTIMER_BGR_REG_HSTIMER_GATING_OFFSET   0

◆ HSTIMER_BGR_REG_HSTIMER_GATING_PASS

#define HSTIMER_BGR_REG_HSTIMER_GATING_PASS   0b1

◆ HSTIMER_BGR_REG_HSTIMER_RST_ASSERT

#define HSTIMER_BGR_REG_HSTIMER_RST_ASSERT   0b0

◆ HSTIMER_BGR_REG_HSTIMER_RST_CLEAR_MASK

#define HSTIMER_BGR_REG_HSTIMER_RST_CLEAR_MASK   0x00010000

◆ HSTIMER_BGR_REG_HSTIMER_RST_DE_ASSERT

#define HSTIMER_BGR_REG_HSTIMER_RST_DE_ASSERT   0b1

◆ HSTIMER_BGR_REG_HSTIMER_RST_OFFSET

#define HSTIMER_BGR_REG_HSTIMER_RST_OFFSET   16

◆ I2S0_CLK_REG

#define I2S0_CLK_REG   0x00000a10

◆ I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X

#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL1X   0b0

◆ I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X

#define I2S0_CLK_REG_CLK_SRC_SEL_AUDIOPLL4X   0b1

◆ I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define I2S0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ I2S0_CLK_REG_CLK_SRC_SEL_OFFSET

#define I2S0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ I2S0_CLK_REG_FACTOR_M_CLEAR_MASK

#define I2S0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ I2S0_CLK_REG_FACTOR_M_OFFSET

#define I2S0_CLK_REG_FACTOR_M_OFFSET   0

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLEAR_MASK   0x80000000

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON

#define I2S0_CLK_REG_I2S0_CLK_GATING_CLOCK_IS_ON   0b1

◆ I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET

#define I2S0_CLK_REG_I2S0_CLK_GATING_OFFSET   31

◆ I2S_BGR_REG

#define I2S_BGR_REG   0x00000a2c

◆ I2S_BGR_REG_I2S0_GATING_CLEAR_MASK

#define I2S_BGR_REG_I2S0_GATING_CLEAR_MASK   0x00000001

◆ I2S_BGR_REG_I2S0_GATING_MASK

#define I2S_BGR_REG_I2S0_GATING_MASK   0b0

◆ I2S_BGR_REG_I2S0_GATING_OFFSET

#define I2S_BGR_REG_I2S0_GATING_OFFSET   0

◆ I2S_BGR_REG_I2S0_GATING_PASS

#define I2S_BGR_REG_I2S0_GATING_PASS   0b1

◆ I2S_BGR_REG_I2S0_RST_ASSERT

#define I2S_BGR_REG_I2S0_RST_ASSERT   0b0

◆ I2S_BGR_REG_I2S0_RST_CLEAR_MASK

#define I2S_BGR_REG_I2S0_RST_CLEAR_MASK   0x00010000

◆ I2S_BGR_REG_I2S0_RST_DE_ASSERT

#define I2S_BGR_REG_I2S0_RST_DE_ASSERT   0b1

◆ I2S_BGR_REG_I2S0_RST_OFFSET

#define I2S_BGR_REG_I2S0_RST_OFFSET   16

◆ IPMC_CLK_REG

#define IPMC_CLK_REG   0x000004fc

◆ IPMC_CLK_REG_FACTOR_M_CLEAR_MASK

#define IPMC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ IPMC_CLK_REG_FACTOR_M_OFFSET

#define IPMC_CLK_REG_FACTOR_M_OFFSET   0

◆ IPMC_CLK_REG_IPMC_CLK_GATING_CLEAR_MASK

#define IPMC_CLK_REG_IPMC_CLK_GATING_CLEAR_MASK   0x80000000

◆ IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_OFF

#define IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_ON

#define IPMC_CLK_REG_IPMC_CLK_GATING_CLOCK_IS_ON   0b1

◆ IPMC_CLK_REG_IPMC_CLK_GATING_OFFSET

#define IPMC_CLK_REG_IPMC_CLK_GATING_OFFSET   31

◆ MBUS_CLK_REG

#define MBUS_CLK_REG   0x00000540

◆ MBUS_CLK_REG_MBUS_RST_ASSERT

#define MBUS_CLK_REG_MBUS_RST_ASSERT   0b0

◆ MBUS_CLK_REG_MBUS_RST_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK   0x40000000

◆ MBUS_CLK_REG_MBUS_RST_DE_ASSERT

#define MBUS_CLK_REG_MBUS_RST_DE_ASSERT   0b1

◆ MBUS_CLK_REG_MBUS_RST_OFFSET

#define MBUS_CLK_REG_MBUS_RST_OFFSET   30

◆ MBUS_MAT_CLK_GATING_REG

#define MBUS_MAT_CLK_GATING_REG   0x00000804

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET   18

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK   0x00000004

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET   2

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK   0x00000100

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET   8

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET   16

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK   0x00000001

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET   0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_CLEAR_MASK   0x00000400

◆ MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_OFFSET   10

◆ MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_G2D_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK   0x00000200

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET   9

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00200000

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   21

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET   17

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK   0x00000002

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK   0b0

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET   1

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS   0b1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   20

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE   0b0

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE   0b1

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET   19

◆ MSGBOX_BGR_REG

#define MSGBOX_BGR_REG   0x0000071c

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   0x00000001

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_MASK

#define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK   0b0

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET

#define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET   0

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_PASS

#define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS   0b1

◆ MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT

#define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT   0b0

◆ MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK   0x00010000

◆ MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT

#define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT   0b1

◆ MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET

#define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET   16

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK   0x00000002

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_MASK

#define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK   0b0

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET

#define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET   1

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_PASS

#define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS   0b1

◆ MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT

#define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT   0b0

◆ MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK   0x00020000

◆ MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT

#define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT   0b1

◆ MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET

#define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET   17

◆ NPU_BGR_REG

#define NPU_BGR_REG   0x000006ec

◆ NPU_BGR_REG_NPU_GATING_CLEAR_MASK

#define NPU_BGR_REG_NPU_GATING_CLEAR_MASK   0x00000001

◆ NPU_BGR_REG_NPU_GATING_MASK

#define NPU_BGR_REG_NPU_GATING_MASK   0b0

◆ NPU_BGR_REG_NPU_GATING_OFFSET

#define NPU_BGR_REG_NPU_GATING_OFFSET   0

◆ NPU_BGR_REG_NPU_GATING_PASS

#define NPU_BGR_REG_NPU_GATING_PASS   0b1

◆ NPU_BGR_REG_NPU_RST_ASSERT

#define NPU_BGR_REG_NPU_RST_ASSERT   0b0

◆ NPU_BGR_REG_NPU_RST_CLEAR_MASK

#define NPU_BGR_REG_NPU_RST_CLEAR_MASK   0x00010000

◆ NPU_BGR_REG_NPU_RST_DE_ASSERT

#define NPU_BGR_REG_NPU_RST_DE_ASSERT   0b1

◆ NPU_BGR_REG_NPU_RST_OFFSET

#define NPU_BGR_REG_NPU_RST_OFFSET   16

◆ NPU_CLK_REG

#define NPU_CLK_REG   0x000006e0

◆ NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X

#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X   0b10

◆ NPU_CLK_REG_CLK_SRC_SEL_OFFSET

#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI_600M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI_600M   0b01

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI_800M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI_800M   0b00

◆ NPU_CLK_REG_FACTOR_M_CLEAR_MASK

#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ NPU_CLK_REG_FACTOR_M_OFFSET

#define NPU_CLK_REG_FACTOR_M_OFFSET   0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK

#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   0x80000000

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0b0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0b1

◆ NPU_CLK_REG_NPU_CLK_GATING_OFFSET

#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31

◆ NPU_GATING_REG

#define NPU_GATING_REG   0x000006e4

◆ NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_BYPASS

#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_BYPASS   0b1

◆ NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_CLEAR_MASK

#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_CLEAR_MASK   0x00000010

◆ NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_OFFSET

#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_OFFSET   4

◆ NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_RELEASE

#define NPU_GATING_REG_NPU_GLB_CLKG_BPS_CFG_RELEASE   0b0

◆ NPU_GATING_REG_NPU_SW_RESET_CFG_ASSERT

#define NPU_GATING_REG_NPU_SW_RESET_CFG_ASSERT   0b1

◆ NPU_GATING_REG_NPU_SW_RESET_CFG_CLEAR_MASK

#define NPU_GATING_REG_NPU_SW_RESET_CFG_CLEAR_MASK   0x00000100

◆ NPU_GATING_REG_NPU_SW_RESET_CFG_DE_ASSERT

#define NPU_GATING_REG_NPU_SW_RESET_CFG_DE_ASSERT   0b0

◆ NPU_GATING_REG_NPU_SW_RESET_CFG_OFFSET

#define NPU_GATING_REG_NPU_SW_RESET_CFG_OFFSET   8

◆ NPUPLL_GATE_EN_REG

#define NPUPLL_GATE_EN_REG   0x00000e40

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_AUTO   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_NO_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_NO_AUTO   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL1X_AUTO_GATE_EN_OFFSET   0

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_DISABLE

#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_DISABLE   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_ENABLE

#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_ENABLE   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL1X_GATE_SW_CFG_OFFSET   16

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_AUTO   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_NO_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL2X_AUTO_GATE_EN_OFFSET   1

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_DISABLE

#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_DISABLE   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_ENABLE

#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_ENABLE   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL2X_GATE_SW_CFG_OFFSET   17

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_AUTO   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_NO_AUTO

#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL4X_AUTO_GATE_EN_OFFSET   2

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_CLEAR_MASK

#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_DISABLE

#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_DISABLE   0b0

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_ENABLE

#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_ENABLE   0b1

◆ NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_OFFSET

#define NPUPLL_GATE_EN_REG_NPUPLL4X_GATE_SW_CFG_OFFSET   18

◆ NPUPLL_GATE_STAT_REG

#define NPUPLL_GATE_STAT_REG   0x00000e44

◆ NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_CLEAR_MASK

#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_CLEAR_MASK   0x00010000

◆ NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_DISABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_DISABLE   0b0

◆ NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_ENABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_ENABLE   0b1

◆ NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_OFFSET

#define NPUPLL_GATE_STAT_REG_NPUPLL1X_GATE_STAT_OFFSET   16

◆ NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_CLEAR_MASK

#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_CLEAR_MASK   0x00020000

◆ NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_DISABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_DISABLE   0b0

◆ NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_ENABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_ENABLE   0b1

◆ NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_OFFSET

#define NPUPLL_GATE_STAT_REG_NPUPLL2X_GATE_STAT_OFFSET   17

◆ NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_CLEAR_MASK

#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_CLEAR_MASK   0x00040000

◆ NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_DISABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_DISABLE   0b0

◆ NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_ENABLE

#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_ENABLE   0b1

◆ NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_OFFSET

#define NPUPLL_GATE_STAT_REG_NPUPLL4X_GATE_STAT_OFFSET   18

◆ PERIPLL_GATE_EN_REG

#define PERIPLL_GATE_EN_REG   0x00000e08

◆ PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008

◆ PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_150M_AUTO_GATE_EN_OFFSET   3

◆ PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_150M_GATE_SW_CFG_OFFSET   19

◆ PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040

◆ PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_160M_AUTO_GATE_EN_OFFSET   6

◆ PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_160M_GATE_SW_CFG_OFFSET   22

◆ PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_200M_AUTO_GATE_EN_OFFSET   0

◆ PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_200M_GATE_SW_CFG_OFFSET   16

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_AUTO

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_300M_AUTO_GATE_EN_OFFSET   4

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_ALL_CFG_OFFSET   21

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_300M_GATE_SW_CFG_OFFSET   20

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_AUTO

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_400M_AUTO_GATE_EN_OFFSET   1

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_ALL_CFG_OFFSET   18

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_400M_GATE_SW_CFG_OFFSET   17

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_AUTO

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_480M_AUTO_GATE_EN_OFFSET   7

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_ALL_CFG_OFFSET   24

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_480M_GATE_SW_CFG_OFFSET   23

◆ PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200

◆ PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_600M_AUTO_GATE_EN_OFFSET   9

◆ PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000

◆ PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_600M_GATE_SW_CFG_OFFSET   25

◆ PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400

◆ PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_800M_AUTO_GATE_EN_OFFSET   10

◆ PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000

◆ PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERI_800M_GATE_SW_CFG_OFFSET   26

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_AUTO

#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_AUTO   0b0

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_NO_AUTO

#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_OFFSET

#define PERIPLL_GATE_EN_REG_PERIPLL2X_AUTO_GATE_EN_OFFSET   11

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_DISABLE

#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_DISABLE   0b0

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_ENABLE

#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_ENABLE   0b1

◆ PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_OFFSET

#define PERIPLL_GATE_EN_REG_PERIPLL2X_GATE_SW_CFG_OFFSET   27

◆ PERIPLL_GATE_STAT_REG

#define PERIPLL_GATE_STAT_REG   0x00000e28

◆ PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_CLEAR_MASK   0x00080000

◆ PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_150M_GATE_STAT_OFFSET   19

◆ PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_CLEAR_MASK   0x00400000

◆ PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_160M_GATE_STAT_OFFSET   22

◆ PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_CLEAR_MASK   0x00010000

◆ PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_200M_GATE_STAT_OFFSET   16

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_CLEAR_MASK   0x00200000

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_ALL_STAT_OFFSET   21

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_CLEAR_MASK   0x00100000

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_300M_GATE_STAT_OFFSET   20

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_CLEAR_MASK   0x00040000

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_ALL_STAT_OFFSET   18

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_CLEAR_MASK   0x00020000

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_400M_GATE_STAT_OFFSET   17

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_CLEAR_MASK   0x01000000

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_ALL_STAT_OFFSET   24

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_CLEAR_MASK   0x00800000

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_480M_GATE_STAT_OFFSET   23

◆ PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_CLEAR_MASK   0x02000000

◆ PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_600M_GATE_STAT_OFFSET   25

◆ PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_CLEAR_MASK   0x04000000

◆ PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERI_800M_GATE_STAT_OFFSET   26

◆ PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_CLEAR_MASK

#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_CLEAR_MASK   0x08000000

◆ PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_DISABLE

#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_DISABLE   0b0

◆ PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_ENABLE

#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_ENABLE   0b1

◆ PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_OFFSET

#define PERIPLL_GATE_STAT_REG_PERIPLL2X_GATE_STAT_OFFSET   27

◆ PIC_CLK_REG

#define PIC_CLK_REG   0x00000508

◆ PIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ PIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define PIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PIC_CLK_REG_CLK_SRC_SEL_PERI_200M

#define PIC_CLK_REG_CLK_SRC_SEL_PERI_200M   0b0

◆ PIC_CLK_REG_CLK_SRC_SEL_PERI_400M

#define PIC_CLK_REG_CLK_SRC_SEL_PERI_400M   0b1

◆ PIC_CLK_REG_PIC_CLK_GATING_CLEAR_MASK

#define PIC_CLK_REG_PIC_CLK_GATING_CLEAR_MASK   0x80000000

◆ PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_OFF

#define PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_ON

#define PIC_CLK_REG_PIC_CLK_GATING_CLOCK_IS_ON   0b1

◆ PIC_CLK_REG_PIC_CLK_GATING_OFFSET

#define PIC_CLK_REG_PIC_CLK_GATING_OFFSET   31

◆ PLL_AUDIO_BIAS_REG

#define PLL_AUDIO_BIAS_REG   0x00000378

◆ PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO_CTRL_REG

#define PLL_AUDIO_CTRL_REG   0x00000078

◆ PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_AUDIO_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK   0x0000ff00

◆ PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_OFFSET   8

◆ PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_AUDIO_CTRL_REG_PLL_P0_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_AUDIO_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_AUDIO_CTRL_REG_PLL_P1_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_AUDIO_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_AUDIO_CTRL_REG_PLL_P2_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO_PAT0_CTRL_REG

#define PLL_AUDIO_PAT0_CTRL_REG   0x00000178

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO_PAT1_CTRL_REG

#define PLL_AUDIO_PAT1_CTRL_REG   0x0000017c

◆ PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_CPU_BIAS_REG

#define PLL_CPU_BIAS_REG   0x00000300

◆ PLL_CPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_CPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_CPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_CPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_CPU_CTRL1_REG

#define PLL_CPU_CTRL1_REG   0x00000004

◆ PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_CLEAR_MASK

#define PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_CLEAR_MASK   0x0000ff00

◆ PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_OFFSET

#define PLL_CPU_CTRL1_REG_PLL_SDM_N_PLLCFG_OFFSET   8

◆ PLL_CPU_CTRL_REG

#define PLL_CPU_CTRL_REG   0x00000000

◆ PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_CPU_CTRL_REG_LOCK_OFFSET

#define PLL_CPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_CPU_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_CPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_CPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CPU_CTRL_REG_PLL_M0_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_M0_CLEAR_MASK   0x00300000

◆ PLL_CPU_CTRL_REG_PLL_M0_OFFSET

#define PLL_CPU_CTRL_REG_PLL_M0_OFFSET   20

◆ PLL_CPU_CTRL_REG_PLL_M1_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_M1_CLEAR_MASK   0x0000000f

◆ PLL_CPU_CTRL_REG_PLL_M1_OFFSET

#define PLL_CPU_CTRL_REG_PLL_M1_OFFSET   0

◆ PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_CPU_CTRL_REG_PLL_N_OFFSET

#define PLL_CPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CPU_CTRL_REG_PLL_P_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_P_CLEAR_MASK   0x00070000

◆ PLL_CPU_CTRL_REG_PLL_P_OFFSET

#define PLL_CPU_CTRL_REG_PLL_P_OFFSET   16

◆ PLL_CPU_CTRL_REG_PLL_PLL_EN_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU_CTRL_REG_PLL_PLL_EN_DISABLE

#define PLL_CPU_CTRL_REG_PLL_PLL_EN_DISABLE   0b0

◆ PLL_CPU_CTRL_REG_PLL_PLL_EN_ENABLE

#define PLL_CPU_CTRL_REG_PLL_PLL_EN_ENABLE   0b1

◆ PLL_CPU_CTRL_REG_PLL_PLL_EN_OFFSET

#define PLL_CPU_CTRL_REG_PLL_PLL_EN_OFFSET   31

◆ PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_CPU_CTRL_REG_PLL_UPDATE_CLEAR_MASK

#define PLL_CPU_CTRL_REG_PLL_UPDATE_CLEAR_MASK   0x04000000

◆ PLL_CPU_CTRL_REG_PLL_UPDATE_OFFSET

#define PLL_CPU_CTRL_REG_PLL_UPDATE_OFFSET   26

◆ PLL_CPU_PAT0_CTRL_REG

#define PLL_CPU_PAT0_CTRL_REG   0x00000100

◆ PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_CPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_1_8_BIT

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_1_8_BIT   0b01

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_2_8_BIT

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_2_8_BIT   0b10

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_3_8_BIT

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_MASH_3_8_BIT   0b11

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_SDM

#define PLL_CPU_PAT0_CTRL_REG_SPR_FREQ_MODE_SDM   0b00

◆ PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_CPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ffe0000

◆ PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_CPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   17

◆ PLL_CPU_PAT1_CTRL_REG

#define PLL_CPU_PAT1_CTRL_REG   0x00000104

◆ PLL_CPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x00040000

◆ PLL_CPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_CPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   18

◆ PLL_CPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00020000

◆ PLL_CPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_CPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   17

◆ PLL_CPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_CPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_CPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_CLEAR_MASK

#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_CLEAR_MASK   0xffc00000

◆ PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_OFFSET

#define PLL_CPU_PAT1_CTRL_REG_SDM_CYCLE_OFFSET   22

◆ PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_CLEAR_MASK

#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_CLEAR_MASK   0x00100000

◆ PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_DOWM

#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_DOWM   0b1

◆ PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_OFFSET

#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_OFFSET   20

◆ PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_UP

#define PLL_CPU_PAT1_CTRL_REG_SDM_DIRECTION_UP   0b0

◆ PLL_CPU_SSC_REG

#define PLL_CPU_SSC_REG   0x00000200

◆ PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_CLEAR_MASK   0x00000070

◆ PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_OFFSET

#define PLL_CPU_SSC_REG_PLL_PHASE_COMPENSATE_OFFSET   4

◆ PLL_CPU_SSC_REG_PLL_SSC_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_SSC_CLEAR_MASK   0x1ffff000

◆ PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_CLEAR_MASK   0x20000000

◆ PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_OFFSET

#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_OFFSET   29

◆ PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_PLL_CLK_SDM

#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_PLL_CLK_SDM   0b0

◆ PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_REF_CLK

#define PLL_CPU_SSC_REG_PLL_SSC_CLK_SEL_REF_CLK   0b1

◆ PLL_CPU_SSC_REG_PLL_SSC_MODE_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CLEAR_MASK   0x80000000

◆ PLL_CPU_SSC_REG_PLL_SSC_MODE_CONTINUOUSLY_FREQUENCY_SCALE

#define PLL_CPU_SSC_REG_PLL_SSC_MODE_CONTINUOUSLY_FREQUENCY_SCALE   0b1

◆ PLL_CPU_SSC_REG_PLL_SSC_MODE_NORMAL_MODE

#define PLL_CPU_SSC_REG_PLL_SSC_MODE_NORMAL_MODE   0b0

◆ PLL_CPU_SSC_REG_PLL_SSC_MODE_OFFSET

#define PLL_CPU_SSC_REG_PLL_SSC_MODE_OFFSET   31

◆ PLL_CPU_SSC_REG_PLL_SSC_OFFSET

#define PLL_CPU_SSC_REG_PLL_SSC_OFFSET   12

◆ PLL_CPU_SSC_REG_PLL_SSC_RSTN_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_CLEAR_MASK   0x40000000

◆ PLL_CPU_SSC_REG_PLL_SSC_RSTN_OFFSET

#define PLL_CPU_SSC_REG_PLL_SSC_RSTN_OFFSET   30

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00439MHZ_US_576_2_17

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00439MHZ_US_576_2_17   0b0000

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00879MHZ_US_576_2_16

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_00879MHZ_US_576_2_16   0b0001

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_01758MHZ_US_576_2_15

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_01758MHZ_US_576_2_15   0b0010

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_03516MHZ_US_576_2_14

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_03516MHZ_US_576_2_14   0b0011

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_07031MHZ_US_576_2_13

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_07031MHZ_US_576_2_13   0b0100

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_14062MHZ_US_576_2_12

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_14062MHZ_US_576_2_12   0b0101

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_28125MHZ_US_576_2_11

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_28125MHZ_US_576_2_11   0b0110

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_0_56250MHZ_US_576_2_10

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_0_56250MHZ_US_576_2_10   0b0111

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_1_12500MHZ_US_576_2_9

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_1_12500MHZ_US_576_2_9   0b1000

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_2_25000MHZ_US_576_2_8

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_2_25000MHZ_US_576_2_8   0b1001

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_4_50000MHZ_US_576_2_7

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_4_50000MHZ_US_576_2_7   0b1010

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_9_00000MHZ_US_576_2_6

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_9_00000MHZ_US_576_2_6   0b1011

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_CLEAR_MASK

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_CLEAR_MASK   0x0000000f

◆ PLL_CPU_SSC_REG_PLL_SSC_STEP_OFFSET

#define PLL_CPU_SSC_REG_PLL_SSC_STEP_OFFSET   0

◆ PLL_CPU_TUN1_REG

#define PLL_CPU_TUN1_REG   0x00000400

◆ PLL_CPU_TUN1_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_CPU_TUN1_REG_PLL_SDM_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU_TUN1_REG_PLL_SDM_EN_OFFSET

#define PLL_CPU_TUN1_REG_PLL_SDM_EN_OFFSET   31

◆ PLL_CPUX_TUNING_REG

#define PLL_CPUX_TUNING_REG   (0x1400)

◆ PLL_CSI_BIAS_REG

#define PLL_CSI_BIAS_REG   0x00000348

◆ PLL_CSI_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_CSI_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_CSI_BIAS_REG_PLL_CP_OFFSET

#define PLL_CSI_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_CSI_CTRL_REG

#define PLL_CSI_CTRL_REG   0x00000048

◆ PLL_CSI_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CSI_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CSI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CSI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CSI_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CSI_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_CSI_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CSI_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_CSI_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CSI_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CSI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CSI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_CSI_CTRL_REG_LOCK_OFFSET

#define PLL_CSI_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CSI_CTRL_REG_LOCK_UNLOCKED

#define PLL_CSI_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_CSI_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CSI_CTRL_REG_PLL_EN_DISABLE

#define PLL_CSI_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_CSI_CTRL_REG_PLL_EN_ENABLE

#define PLL_CSI_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_CSI_CTRL_REG_PLL_EN_OFFSET

#define PLL_CSI_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CSI_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK   0x0000ff00

◆ PLL_CSI_CTRL_REG_PLL_FACTOR_N_OFFSET

#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_OFFSET   8

◆ PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_CSI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CSI_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CSI_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_CSI_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CSI_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_CSI_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CSI_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CSI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_CSI_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_CSI_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_CSI_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_CSI_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_CSI_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_CSI_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_CSI_PAT0_CTRL_REG

#define PLL_CSI_PAT0_CTRL_REG   0x00000148

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_CSI_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_CSI_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_CSI_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_CSI_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_CSI_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_CSI_PAT1_CTRL_REG

#define PLL_CSI_PAT1_CTRL_REG   0x0000014c

◆ PLL_CSI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_CSI_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_CSI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_CSI_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_CSI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_CSI_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_DDR_BIAS_REG

#define PLL_DDR_BIAS_REG   0x00000310

◆ PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_DDR_BIAS_REG_PLL_CP_OFFSET

#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_DDR_CTRL_REG

#define PLL_DDR_CTRL_REG   0x00000010

◆ PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_DDR_CTRL_REG_LOCK_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28

◆ PLL_DDR_CTRL_REG_LOCK_UNLOCKED

#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_DDR_CTRL_REG_PLL_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_DDR_CTRL_REG_PLL_N_OFFSET

#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_DDR_PAT0_CTRL_REG

#define PLL_DDR_PAT0_CTRL_REG   0x00000110

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG

#define PLL_DDR_PAT1_CTRL_REG   0x00000114

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_NPU_BIAS_REG

#define PLL_NPU_BIAS_REG   0x00000380

◆ PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_NPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_NPU_CTRL_REG

#define PLL_NPU_CTRL_REG   0x00000080

◆ PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_NPU_CTRL_REG_LOCK_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_NPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_NPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_NPU_CTRL_REG_PLL_N_OFFSET

#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_NPU_PAT0_CTRL_REG

#define PLL_NPU_PAT0_CTRL_REG   0x00000180

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG

#define PLL_NPU_PAT1_CTRL_REG   0x00000184

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_OPG_BYPASS_REG

#define PLL_OPG_BYPASS_REG   0x00000e10

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_CLEAR_MASK   0x00000001

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_DISABLE   0b0

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_ENABLE   0b1

◆ PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET

#define PLL_OPG_BYPASS_REG_PLL_OUTPUT_GATE_BYPASS_OFFSET   0

◆ PLL_PERI_BIAS_REG

#define PLL_PERI_BIAS_REG   0x00000320

◆ PLL_PERI_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_PERI_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI_CTRL_REG

#define PLL_PERI_CTRL_REG   0x00000020

◆ PLL_PERI_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_PERI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_PERI_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_PERI_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_PERI_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_PERI_CTRL_REG_LOCK_OFFSET

#define PLL_PERI_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_PERI_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_PERI_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_PERI_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_PERI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_PERI_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_PERI_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_PERI_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_PERI_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_PERI_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_PERI_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_PERI_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_PERI_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_PERI_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_PERI_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_PERI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_PERI_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_PERI_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI_PAT0_CTRL_REG

#define PLL_PERI_PAT0_CTRL_REG   0x00000120

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_PERI_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI_PAT1_CTRL_REG

#define PLL_PERI_PAT1_CTRL_REG   0x00000124

◆ PLL_PERI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_PERI_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_PERI_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PRE_DIV_REG

#define PLL_PRE_DIV_REG   0x00000e00

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_CLEAR_MASK

#define PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_CLEAR_MASK   0x0000001f

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_OFFSET

#define PLL_PRE_DIV_REG_AUDIOPLL1X_DIV_OFFSET   0

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIO_FRAC_DIV1X

#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIO_FRAC_DIV1X   0b1

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIOPLL_DIV5

#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_AUDIOPLL_DIV5   0b0

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_CLEAR_MASK

#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_CLEAR_MASK   0x01000000

◆ PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_OFFSET

#define PLL_PRE_DIV_REG_AUDIOPLL1X_SEL_OFFSET   24

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_CLEAR_MASK

#define PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_CLEAR_MASK   0x000003e0

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_OFFSET

#define PLL_PRE_DIV_REG_AUDIOPLL4X_DIV_OFFSET   5

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIO_FRAC_DIV4X

#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIO_FRAC_DIV4X   0b1

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIOPLL_DIV2

#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_AUDIOPLL_DIV2   0b0

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_CLEAR_MASK

#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_CLEAR_MASK   0x10000000

◆ PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_OFFSET

#define PLL_PRE_DIV_REG_AUDIOPLL4X_SEL_OFFSET   28

◆ PLL_VIDEO_BIAS_REG

#define PLL_VIDEO_BIAS_REG   0x00000340

◆ PLL_VIDEO_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO_CTRL_REG

#define PLL_VIDEO_CTRL_REG   0x00000040

◆ PLL_VIDEO_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_DISABLE   0b0

◆ PLL_VIDEO_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_ENABLE   0b1

◆ PLL_VIDEO_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0b1

◆ PLL_VIDEO_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO_CTRL_REG_LOCK_UNLOCKED   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO_CTRL_REG_PLL_EN_DISABLE   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO_CTRL_REG_PLL_EN_ENABLE   0b1

◆ PLL_VIDEO_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_DISABLE   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_ENABLE   0b1

◆ PLL_VIDEO_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0b1

◆ PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0b1

◆ PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_DISABLE   0b0

◆ PLL_VIDEO_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_ENABLE   0b1

◆ PLL_VIDEO_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0b10

◆ PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0b00

◆ PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0b01

◆ PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO_PAT0_CTRL_REG

#define PLL_VIDEO_PAT0_CTRL_REG   0x00000140

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_31_5KHZ   0b00

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32_5KHZ   0b10

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32KHZ   0b01

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_33KHZ   0b11

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0b1

◆ PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0b0

◆ PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0b00

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0b01

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0b10

◆ PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0b11

◆ PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO_PAT1_CTRL_REG

#define PLL_VIDEO_PAT1_CTRL_REG   0x00000144

◆ PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PSRAM_BGR_REG

#define PSRAM_BGR_REG   0x0000085c

◆ PSRAM_BGR_REG_PSRAM_CTRL_GATING_CLEAR_MASK

#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_CLEAR_MASK   0x00000001

◆ PSRAM_BGR_REG_PSRAM_CTRL_GATING_MASK

#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_MASK   0b0

◆ PSRAM_BGR_REG_PSRAM_CTRL_GATING_OFFSET

#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_OFFSET   0

◆ PSRAM_BGR_REG_PSRAM_CTRL_GATING_PASS

#define PSRAM_BGR_REG_PSRAM_CTRL_GATING_PASS   0b1

◆ PSRAM_BGR_REG_PSRAM_CTRL_RST_ASSERT

#define PSRAM_BGR_REG_PSRAM_CTRL_RST_ASSERT   0b0

◆ PSRAM_BGR_REG_PSRAM_CTRL_RST_CLEAR_MASK

#define PSRAM_BGR_REG_PSRAM_CTRL_RST_CLEAR_MASK   0x00010000

◆ PSRAM_BGR_REG_PSRAM_CTRL_RST_DE_ASSERT

#define PSRAM_BGR_REG_PSRAM_CTRL_RST_DE_ASSERT   0b1

◆ PSRAM_BGR_REG_PSRAM_CTRL_RST_OFFSET

#define PSRAM_BGR_REG_PSRAM_CTRL_RST_OFFSET   16

◆ PSRAM_CLK_REG

#define PSRAM_CLK_REG   0x00000850

◆ PSRAM_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PSRAM_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ PSRAM_CLK_REG_CLK_SRC_SEL_HOSC

#define PSRAM_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ PSRAM_CLK_REG_CLK_SRC_SEL_OFFSET

#define PSRAM_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PSRAM_CLK_REG_CLK_SRC_SEL_PERI_300M

#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_300M   0b011

◆ PSRAM_CLK_REG_CLK_SRC_SEL_PERI_400M

#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_400M   0b010

◆ PSRAM_CLK_REG_CLK_SRC_SEL_PERI_480M

#define PSRAM_CLK_REG_CLK_SRC_SEL_PERI_480M   0b001

◆ PSRAM_CLK_REG_FACTOR_M_CLEAR_MASK

#define PSRAM_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ PSRAM_CLK_REG_FACTOR_M_OFFSET

#define PSRAM_CLK_REG_FACTOR_M_OFFSET   0

◆ PSRAM_CLK_REG_PSRAM_CLK_GATING_CLEAR_MASK

#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLEAR_MASK   0x80000000

◆ PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_OFF

#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_OFF   0b0

◆ PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_ON

#define PSRAM_CLK_REG_PSRAM_CLK_GATING_CLOCK_IS_ON   0b1

◆ PSRAM_CLK_REG_PSRAM_CLK_GATING_OFFSET

#define PSRAM_CLK_REG_PSRAM_CLK_GATING_OFFSET   31

◆ PWM_BGR_REG

#define PWM_BGR_REG   0x000007ac

◆ PWM_BGR_REG_PWM_GATING_CLEAR_MASK

#define PWM_BGR_REG_PWM_GATING_CLEAR_MASK   0x00000001

◆ PWM_BGR_REG_PWM_GATING_MASK

#define PWM_BGR_REG_PWM_GATING_MASK   0b0

◆ PWM_BGR_REG_PWM_GATING_OFFSET

#define PWM_BGR_REG_PWM_GATING_OFFSET   0

◆ PWM_BGR_REG_PWM_GATING_PASS

#define PWM_BGR_REG_PWM_GATING_PASS   0b1

◆ PWM_BGR_REG_PWM_RST_ASSERT

#define PWM_BGR_REG_PWM_RST_ASSERT   0b0

◆ PWM_BGR_REG_PWM_RST_CLEAR_MASK

#define PWM_BGR_REG_PWM_RST_CLEAR_MASK   0x00010000

◆ PWM_BGR_REG_PWM_RST_DE_ASSERT

#define PWM_BGR_REG_PWM_RST_DE_ASSERT   0b1

◆ PWM_BGR_REG_PWM_RST_OFFSET

#define PWM_BGR_REG_PWM_RST_OFFSET   16

◆ RISCV_CFG_BGR_REG

#define RISCV_CFG_BGR_REG   0x00000d0c

◆ RISCV_CFG_BGR_REG_RISCV_CFG_GATING_CLEAR_MASK

#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_CLEAR_MASK   0x00000001

◆ RISCV_CFG_BGR_REG_RISCV_CFG_GATING_MASK

#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_MASK   0b0

◆ RISCV_CFG_BGR_REG_RISCV_CFG_GATING_OFFSET

#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_OFFSET   0

◆ RISCV_CFG_BGR_REG_RISCV_CFG_GATING_PASS

#define RISCV_CFG_BGR_REG_RISCV_CFG_GATING_PASS   0b1

◆ RISCV_CFG_BGR_REG_RISCV_CFG_RST_ASSERT

#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_ASSERT   0b0

◆ RISCV_CFG_BGR_REG_RISCV_CFG_RST_CLEAR_MASK

#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_CLEAR_MASK   0x00010000

◆ RISCV_CFG_BGR_REG_RISCV_CFG_RST_DE_ASSERT

#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_DE_ASSERT   0b1

◆ RISCV_CFG_BGR_REG_RISCV_CFG_RST_OFFSET

#define RISCV_CFG_BGR_REG_RISCV_CFG_RST_OFFSET   16

◆ SMHC0_BGR_REG_SMHC0_GATING_OFFSET

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET   0

◆ SMHC0_BGR_REG_SMHC0_RST_OFFSET

#define SMHC0_BGR_REG_SMHC0_RST_OFFSET   16

◆ SMHC0_CLK_REG

#define SMHC0_CLK_REG   0x00000830

◆ SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_DDRPLL

#define SMHC0_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100

◆ SMHC0_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ SMHC0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define SMHC0_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011

◆ SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SMHC0_CLK_REG_FACTOR_M_OFFSET

#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC0_CLK_REG_FACTOR_N_1

#define SMHC0_CLK_REG_FACTOR_N_1   0b00

◆ SMHC0_CLK_REG_FACTOR_N_2

#define SMHC0_CLK_REG_FACTOR_N_2   0b01

◆ SMHC0_CLK_REG_FACTOR_N_4

#define SMHC0_CLK_REG_FACTOR_N_4   0b10

◆ SMHC0_CLK_REG_FACTOR_N_8

#define SMHC0_CLK_REG_FACTOR_N_8   0b11

◆ SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SMHC0_CLK_REG_FACTOR_N_OFFSET

#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31

◆ SMHC1_CLK_REG

#define SMHC1_CLK_REG   0x00000834

◆ SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_DDRPLL

#define SMHC1_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100

◆ SMHC1_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ SMHC1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define SMHC1_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011

◆ SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SMHC1_CLK_REG_FACTOR_M_OFFSET

#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC1_CLK_REG_FACTOR_N_1

#define SMHC1_CLK_REG_FACTOR_N_1   0b00

◆ SMHC1_CLK_REG_FACTOR_N_2

#define SMHC1_CLK_REG_FACTOR_N_2   0b01

◆ SMHC1_CLK_REG_FACTOR_N_4

#define SMHC1_CLK_REG_FACTOR_N_4   0b10

◆ SMHC1_CLK_REG_FACTOR_N_8

#define SMHC1_CLK_REG_FACTOR_N_8   0b11

◆ SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SMHC1_CLK_REG_FACTOR_N_OFFSET

#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31

◆ SMHC2_CLK_REG

#define SMHC2_CLK_REG   0x00000838

◆ SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_DDRPLL

#define SMHC2_CLK_REG_CLK_SRC_SEL_DDRPLL   0b100

◆ SMHC2_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI_600M   0b001

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI_800M   0b010

◆ SMHC2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define SMHC2_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b011

◆ SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SMHC2_CLK_REG_FACTOR_M_OFFSET

#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC2_CLK_REG_FACTOR_N_1

#define SMHC2_CLK_REG_FACTOR_N_1   0b00

◆ SMHC2_CLK_REG_FACTOR_N_2

#define SMHC2_CLK_REG_FACTOR_N_2   0b01

◆ SMHC2_CLK_REG_FACTOR_N_4

#define SMHC2_CLK_REG_FACTOR_N_4   0b10

◆ SMHC2_CLK_REG_FACTOR_N_8

#define SMHC2_CLK_REG_FACTOR_N_8   0b11

◆ SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SMHC2_CLK_REG_FACTOR_N_OFFSET

#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31

◆ SMHC_BGR_REG

#define SMHC_BGR_REG   0x0000084c

◆ SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK   0x00000001

◆ SMHC_BGR_REG_SMHC0_GATING_MASK

#define SMHC_BGR_REG_SMHC0_GATING_MASK   0b0

◆ SMHC_BGR_REG_SMHC0_GATING_PASS

#define SMHC_BGR_REG_SMHC0_GATING_PASS   0b1

◆ SMHC_BGR_REG_SMHC0_RST_ASSERT

#define SMHC_BGR_REG_SMHC0_RST_ASSERT   0b0

◆ SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK   0x00010000

◆ SMHC_BGR_REG_SMHC0_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT   0b1

◆ SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK   0x00000002

◆ SMHC_BGR_REG_SMHC1_GATING_MASK

#define SMHC_BGR_REG_SMHC1_GATING_MASK   0b0

◆ SMHC_BGR_REG_SMHC1_GATING_OFFSET

#define SMHC_BGR_REG_SMHC1_GATING_OFFSET   1

◆ SMHC_BGR_REG_SMHC1_GATING_PASS

#define SMHC_BGR_REG_SMHC1_GATING_PASS   0b1

◆ SMHC_BGR_REG_SMHC1_RST_ASSERT

#define SMHC_BGR_REG_SMHC1_RST_ASSERT   0b0

◆ SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK   0x00020000

◆ SMHC_BGR_REG_SMHC1_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT   0b1

◆ SMHC_BGR_REG_SMHC1_RST_OFFSET

#define SMHC_BGR_REG_SMHC1_RST_OFFSET   17

◆ SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK   0x00000004

◆ SMHC_BGR_REG_SMHC2_GATING_MASK

#define SMHC_BGR_REG_SMHC2_GATING_MASK   0b0

◆ SMHC_BGR_REG_SMHC2_GATING_OFFSET

#define SMHC_BGR_REG_SMHC2_GATING_OFFSET   2

◆ SMHC_BGR_REG_SMHC2_GATING_PASS

#define SMHC_BGR_REG_SMHC2_GATING_PASS   0b1

◆ SMHC_BGR_REG_SMHC2_RST_ASSERT

#define SMHC_BGR_REG_SMHC2_RST_ASSERT   0b0

◆ SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK   0x00040000

◆ SMHC_BGR_REG_SMHC2_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT   0b1

◆ SMHC_BGR_REG_SMHC2_RST_OFFSET

#define SMHC_BGR_REG_SMHC2_RST_OFFSET   18

◆ SPI0_CLK_REG

#define SPI0_CLK_REG   0x00000940

◆ SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI0_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SPI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001

◆ SPI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SPI0_CLK_REG_FACTOR_M_OFFSET

#define SPI0_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI0_CLK_REG_FACTOR_N_1

#define SPI0_CLK_REG_FACTOR_N_1   0b00

◆ SPI0_CLK_REG_FACTOR_N_2

#define SPI0_CLK_REG_FACTOR_N_2   0b01

◆ SPI0_CLK_REG_FACTOR_N_4

#define SPI0_CLK_REG_FACTOR_N_4   0b10

◆ SPI0_CLK_REG_FACTOR_N_8

#define SPI0_CLK_REG_FACTOR_N_8   0b11

◆ SPI0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SPI0_CLK_REG_FACTOR_N_OFFSET

#define SPI0_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31

◆ SPI1_CLK_REG

#define SPI1_CLK_REG   0x00000944

◆ SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI1_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SPI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001

◆ SPI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SPI1_CLK_REG_FACTOR_M_OFFSET

#define SPI1_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI1_CLK_REG_FACTOR_N_1

#define SPI1_CLK_REG_FACTOR_N_1   0b00

◆ SPI1_CLK_REG_FACTOR_N_2

#define SPI1_CLK_REG_FACTOR_N_2   0b01

◆ SPI1_CLK_REG_FACTOR_N_4

#define SPI1_CLK_REG_FACTOR_N_4   0b10

◆ SPI1_CLK_REG_FACTOR_N_8

#define SPI1_CLK_REG_FACTOR_N_8   0b11

◆ SPI1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SPI1_CLK_REG_FACTOR_N_OFFSET

#define SPI1_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31

◆ SPI2_CLK_REG

#define SPI2_CLK_REG   0x00000948

◆ SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI2_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SPI2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI_200M   0b010

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI_300M   0b001

◆ SPI2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SPI2_CLK_REG_FACTOR_M_OFFSET

#define SPI2_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI2_CLK_REG_FACTOR_N_1

#define SPI2_CLK_REG_FACTOR_N_1   0b00

◆ SPI2_CLK_REG_FACTOR_N_2

#define SPI2_CLK_REG_FACTOR_N_2   0b01

◆ SPI2_CLK_REG_FACTOR_N_4

#define SPI2_CLK_REG_FACTOR_N_4   0b10

◆ SPI2_CLK_REG_FACTOR_N_8

#define SPI2_CLK_REG_FACTOR_N_8   0b11

◆ SPI2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SPI2_CLK_REG_FACTOR_N_OFFSET

#define SPI2_CLK_REG_FACTOR_N_OFFSET   8

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31

◆ SPI_BGR_REG

#define SPI_BGR_REG   0x0000096c

◆ SPI_BGR_REG_SPI0_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK   0x00000001

◆ SPI_BGR_REG_SPI0_GATING_MASK

#define SPI_BGR_REG_SPI0_GATING_MASK   0b0

◆ SPI_BGR_REG_SPI0_GATING_OFFSET

#define SPI_BGR_REG_SPI0_GATING_OFFSET   0

◆ SPI_BGR_REG_SPI0_GATING_PASS

#define SPI_BGR_REG_SPI0_GATING_PASS   0b1

◆ SPI_BGR_REG_SPI0_RST_ASSERT

#define SPI_BGR_REG_SPI0_RST_ASSERT   0b0

◆ SPI_BGR_REG_SPI0_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI0_RST_CLEAR_MASK   0x00010000

◆ SPI_BGR_REG_SPI0_RST_DE_ASSERT

#define SPI_BGR_REG_SPI0_RST_DE_ASSERT   0b1

◆ SPI_BGR_REG_SPI0_RST_OFFSET

#define SPI_BGR_REG_SPI0_RST_OFFSET   16

◆ SPI_BGR_REG_SPI1_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK   0x00000002

◆ SPI_BGR_REG_SPI1_GATING_MASK

#define SPI_BGR_REG_SPI1_GATING_MASK   0b0

◆ SPI_BGR_REG_SPI1_GATING_OFFSET

#define SPI_BGR_REG_SPI1_GATING_OFFSET   1

◆ SPI_BGR_REG_SPI1_GATING_PASS

#define SPI_BGR_REG_SPI1_GATING_PASS   0b1

◆ SPI_BGR_REG_SPI1_RST_ASSERT

#define SPI_BGR_REG_SPI1_RST_ASSERT   0b0

◆ SPI_BGR_REG_SPI1_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI1_RST_CLEAR_MASK   0x00020000

◆ SPI_BGR_REG_SPI1_RST_DE_ASSERT

#define SPI_BGR_REG_SPI1_RST_DE_ASSERT   0b1

◆ SPI_BGR_REG_SPI1_RST_OFFSET

#define SPI_BGR_REG_SPI1_RST_OFFSET   17

◆ SPI_BGR_REG_SPI2_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK   0x00000004

◆ SPI_BGR_REG_SPI2_GATING_MASK

#define SPI_BGR_REG_SPI2_GATING_MASK   0b0

◆ SPI_BGR_REG_SPI2_GATING_OFFSET

#define SPI_BGR_REG_SPI2_GATING_OFFSET   2

◆ SPI_BGR_REG_SPI2_GATING_PASS

#define SPI_BGR_REG_SPI2_GATING_PASS   0b1

◆ SPI_BGR_REG_SPI2_RST_ASSERT

#define SPI_BGR_REG_SPI2_RST_ASSERT   0b0

◆ SPI_BGR_REG_SPI2_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI2_RST_CLEAR_MASK   0x00040000

◆ SPI_BGR_REG_SPI2_RST_DE_ASSERT

#define SPI_BGR_REG_SPI2_RST_DE_ASSERT   0b1

◆ SPI_BGR_REG_SPI2_RST_OFFSET

#define SPI_BGR_REG_SPI2_RST_OFFSET   18

◆ SPI_BGR_REG_SPIF_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK   0x00000010

◆ SPI_BGR_REG_SPIF_GATING_MASK

#define SPI_BGR_REG_SPIF_GATING_MASK   0b0

◆ SPI_BGR_REG_SPIF_GATING_OFFSET

#define SPI_BGR_REG_SPIF_GATING_OFFSET   4

◆ SPI_BGR_REG_SPIF_GATING_PASS

#define SPI_BGR_REG_SPIF_GATING_PASS   0b1

◆ SPI_BGR_REG_SPIF_RST_ASSERT

#define SPI_BGR_REG_SPIF_RST_ASSERT   0b0

◆ SPI_BGR_REG_SPIF_RST_CLEAR_MASK

#define SPI_BGR_REG_SPIF_RST_CLEAR_MASK   0x00100000

◆ SPI_BGR_REG_SPIF_RST_DE_ASSERT

#define SPI_BGR_REG_SPIF_RST_DE_ASSERT   0b1

◆ SPI_BGR_REG_SPIF_RST_OFFSET

#define SPI_BGR_REG_SPIF_RST_OFFSET   20

◆ SPIF_CLK_REG

#define SPIF_CLK_REG   0x00000950

◆ SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPIF_CLK_REG_CLK_SRC_SEL_HOSC

#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0b000

◆ SPIF_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI_300M   0b010

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI_400M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ SPIF_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ SPIF_CLK_REG_FACTOR_M_OFFSET

#define SPIF_CLK_REG_FACTOR_M_OFFSET   0

◆ SPIF_CLK_REG_FACTOR_N_1

#define SPIF_CLK_REG_FACTOR_N_1   0b00

◆ SPIF_CLK_REG_FACTOR_N_2

#define SPIF_CLK_REG_FACTOR_N_2   0b01

◆ SPIF_CLK_REG_FACTOR_N_4

#define SPIF_CLK_REG_FACTOR_N_4   0b10

◆ SPIF_CLK_REG_FACTOR_N_8

#define SPIF_CLK_REG_FACTOR_N_8   0b11

◆ SPIF_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ SPIF_CLK_REG_FACTOR_N_OFFSET

#define SPIF_CLK_REG_FACTOR_N_OFFSET   8

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0b0

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0b1

◆ SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET

#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31

◆ SPIF_GATING_SHIFT

#define SPIF_GATING_SHIFT   (4)

◆ SPIF_RESET_SHIFT

#define SPIF_RESET_SHIFT   (20)

◆ SPINLOCK_BGR_REG

#define SPINLOCK_BGR_REG   0x0000072c

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   0x00000001

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0b0

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   0x00010000

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0b1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16

◆ SUNXI_CE_CLK_REG

#define SUNXI_CE_CLK_REG   (SUNXI_CCU_BASE + CE_CLK_REG)

◆ SUNXI_CE_FACTOR

#define SUNXI_CE_FACTOR   (0b0)

◆ SUNXI_CE_GATING_OFFSET

#define SUNXI_CE_GATING_OFFSET   CE_BGR_REG_CE_GATING_OFFSET

◆ SUNXI_CE_GATING_REG

#define SUNXI_CE_GATING_REG   (SUNXI_CCU_BASE + CE_BGR_REG)

◆ SUNXI_CE_MBUS_MST_CLK_GATE_EN_REG

#define SUNXI_CE_MBUS_MST_CLK_GATE_EN_REG   (SUNXI_CCU_BASE + MBUS_MAT_CLK_GATING_REG)

◆ SUNXI_CE_MBUS_MST_CLK_GATE_OFFSET

#define SUNXI_CE_MBUS_MST_CLK_GATE_OFFSET   MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET

◆ SUNXI_CE_RESET_OFFSET

#define SUNXI_CE_RESET_OFFSET   CE_BGR_REG_CE_RST_OFFSET

◆ SUNXI_CE_RESET_REG

#define SUNXI_CE_RESET_REG   (SUNXI_CCU_BASE + CE_BGR_REG)

◆ SUNXI_CE_SRC

#define SUNXI_CE_SRC   CE_CLK_REG_CLK_SRC_SEL_PERI_400M

◆ SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET

#define SUNXI_CE_SYS_CLK_FACTOR_M_OFFSET   CE_CLK_REG_FACTOR_M_OFFSET

◆ SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET

#define SUNXI_CE_SYS_CLK_SRC_SEL_OFFSET   CE_CLK_REG_CLK_SRC_SEL_OFFSET

◆ SUNXI_CE_SYS_GATING_OFFSET

#define SUNXI_CE_SYS_GATING_OFFSET   CE_BGR_REG_CE_SYS_GATING_OFFSET

◆ SUNXI_CE_SYS_RESET_OFFSET

#define SUNXI_CE_SYS_RESET_OFFSET   CE_BGR_REG_CE_SYS_RST_OFFSET

◆ TCONLCD_BGR_REG

#define TCONLCD_BGR_REG   0x00000b7c

◆ TCONLCD_BGR_REG_TCONLCD_GATING_CLEAR_MASK

#define TCONLCD_BGR_REG_TCONLCD_GATING_CLEAR_MASK   0x00000001

◆ TCONLCD_BGR_REG_TCONLCD_GATING_MASK

#define TCONLCD_BGR_REG_TCONLCD_GATING_MASK   0b0

◆ TCONLCD_BGR_REG_TCONLCD_GATING_OFFSET

#define TCONLCD_BGR_REG_TCONLCD_GATING_OFFSET   0

◆ TCONLCD_BGR_REG_TCONLCD_GATING_PASS

#define TCONLCD_BGR_REG_TCONLCD_GATING_PASS   0b1

◆ TCONLCD_BGR_REG_TCONLCD_RST_ASSERT

#define TCONLCD_BGR_REG_TCONLCD_RST_ASSERT   0b0

◆ TCONLCD_BGR_REG_TCONLCD_RST_CLEAR_MASK

#define TCONLCD_BGR_REG_TCONLCD_RST_CLEAR_MASK   0x00010000

◆ TCONLCD_BGR_REG_TCONLCD_RST_DE_ASSERT

#define TCONLCD_BGR_REG_TCONLCD_RST_DE_ASSERT   0b1

◆ TCONLCD_BGR_REG_TCONLCD_RST_OFFSET

#define TCONLCD_BGR_REG_TCONLCD_RST_OFFSET   16

◆ TCONLCD_CLK_REG

#define TCONLCD_CLK_REG   0x00000b60

◆ TCONLCD_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TCONLCD_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TCONLCD_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define TCONLCD_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b010

◆ TCONLCD_CLK_REG_CLK_SRC_SEL_OFFSET

#define TCONLCD_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TCONLCD_CLK_REG_CLK_SRC_SEL_PERIPLL2X

#define TCONLCD_CLK_REG_CLK_SRC_SEL_PERIPLL2X   0b001

◆ TCONLCD_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define TCONLCD_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b000

◆ TCONLCD_CLK_REG_FACTOR_M_CLEAR_MASK

#define TCONLCD_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ TCONLCD_CLK_REG_FACTOR_M_OFFSET

#define TCONLCD_CLK_REG_FACTOR_M_OFFSET   0

◆ TCONLCD_CLK_REG_FACTOR_N_1

#define TCONLCD_CLK_REG_FACTOR_N_1   0b00

◆ TCONLCD_CLK_REG_FACTOR_N_2

#define TCONLCD_CLK_REG_FACTOR_N_2   0b01

◆ TCONLCD_CLK_REG_FACTOR_N_4

#define TCONLCD_CLK_REG_FACTOR_N_4   0b10

◆ TCONLCD_CLK_REG_FACTOR_N_8

#define TCONLCD_CLK_REG_FACTOR_N_8   0b11

◆ TCONLCD_CLK_REG_FACTOR_N_CLEAR_MASK

#define TCONLCD_CLK_REG_FACTOR_N_CLEAR_MASK   0x00000300

◆ TCONLCD_CLK_REG_FACTOR_N_OFFSET

#define TCONLCD_CLK_REG_FACTOR_N_OFFSET   8

◆ TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLEAR_MASK

#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLEAR_MASK   0x80000000

◆ TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_OFF

#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_OFF   0b0

◆ TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_ON

#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_CLOCK_IS_ON   0b1

◆ TCONLCD_CLK_REG_TCONLCD_CLK_GATING_OFFSET

#define TCONLCD_CLK_REG_TCONLCD_CLK_GATING_OFFSET   31

◆ THS_BGR_REG

#define THS_BGR_REG   0x000009fc

◆ THS_BGR_REG_THS_GATING_CLEAR_MASK

#define THS_BGR_REG_THS_GATING_CLEAR_MASK   0x00000001

◆ THS_BGR_REG_THS_GATING_MASK

#define THS_BGR_REG_THS_GATING_MASK   0b0

◆ THS_BGR_REG_THS_GATING_OFFSET

#define THS_BGR_REG_THS_GATING_OFFSET   0

◆ THS_BGR_REG_THS_GATING_PASS

#define THS_BGR_REG_THS_GATING_PASS   0b1

◆ THS_BGR_REG_THS_RST_ASSERT

#define THS_BGR_REG_THS_RST_ASSERT   0b0

◆ THS_BGR_REG_THS_RST_CLEAR_MASK

#define THS_BGR_REG_THS_RST_CLEAR_MASK   0x00010000

◆ THS_BGR_REG_THS_RST_DE_ASSERT

#define THS_BGR_REG_THS_RST_DE_ASSERT   0b1

◆ THS_BGR_REG_THS_RST_OFFSET

#define THS_BGR_REG_THS_RST_OFFSET   16

◆ TIMER_APB_CLK_REG

#define TIMER_APB_CLK_REG   0x00000744

◆ TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLEAR_MASK

#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_OFF

#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_OFF   0b0

◆ TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_ON

#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_CLOCK_IS_ON   0b1

◆ TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_OFFSET

#define TIMER_APB_CLK_REG_TIMER_APB_CLK_GATING_OFFSET   31

◆ TIMER_BGR_REG

#define TIMER_BGR_REG   0x0000074c

◆ TIMER_BGR_REG_TIMER_RST_ASSERT

#define TIMER_BGR_REG_TIMER_RST_ASSERT   0b0

◆ TIMER_BGR_REG_TIMER_RST_CLEAR_MASK

#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK   0x00010000

◆ TIMER_BGR_REG_TIMER_RST_DE_ASSERT

#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT   0b1

◆ TIMER_BGR_REG_TIMER_RST_OFFSET

#define TIMER_BGR_REG_TIMER_RST_OFFSET   16

◆ TWI_BGR_REG

#define TWI_BGR_REG   0x0000091c

◆ TWI_BGR_REG_TWI0_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK   0x00000001

◆ TWI_BGR_REG_TWI0_GATING_MASK

#define TWI_BGR_REG_TWI0_GATING_MASK   0b0

◆ TWI_BGR_REG_TWI0_GATING_OFFSET

#define TWI_BGR_REG_TWI0_GATING_OFFSET   0

◆ TWI_BGR_REG_TWI0_GATING_PASS

#define TWI_BGR_REG_TWI0_GATING_PASS   0b1

◆ TWI_BGR_REG_TWI0_RST_ASSERT

#define TWI_BGR_REG_TWI0_RST_ASSERT   0b0

◆ TWI_BGR_REG_TWI0_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI0_RST_CLEAR_MASK   0x00010000

◆ TWI_BGR_REG_TWI0_RST_DE_ASSERT

#define TWI_BGR_REG_TWI0_RST_DE_ASSERT   0b1

◆ TWI_BGR_REG_TWI0_RST_OFFSET

#define TWI_BGR_REG_TWI0_RST_OFFSET   16

◆ TWI_BGR_REG_TWI1_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK   0x00000002

◆ TWI_BGR_REG_TWI1_GATING_MASK

#define TWI_BGR_REG_TWI1_GATING_MASK   0b0

◆ TWI_BGR_REG_TWI1_GATING_OFFSET

#define TWI_BGR_REG_TWI1_GATING_OFFSET   1

◆ TWI_BGR_REG_TWI1_GATING_PASS

#define TWI_BGR_REG_TWI1_GATING_PASS   0b1

◆ TWI_BGR_REG_TWI1_RST_ASSERT

#define TWI_BGR_REG_TWI1_RST_ASSERT   0b0

◆ TWI_BGR_REG_TWI1_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI1_RST_CLEAR_MASK   0x00020000

◆ TWI_BGR_REG_TWI1_RST_DE_ASSERT

#define TWI_BGR_REG_TWI1_RST_DE_ASSERT   0b1

◆ TWI_BGR_REG_TWI1_RST_OFFSET

#define TWI_BGR_REG_TWI1_RST_OFFSET   17

◆ TWI_BGR_REG_TWI2_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK   0x00000004

◆ TWI_BGR_REG_TWI2_GATING_MASK

#define TWI_BGR_REG_TWI2_GATING_MASK   0b0

◆ TWI_BGR_REG_TWI2_GATING_OFFSET

#define TWI_BGR_REG_TWI2_GATING_OFFSET   2

◆ TWI_BGR_REG_TWI2_GATING_PASS

#define TWI_BGR_REG_TWI2_GATING_PASS   0b1

◆ TWI_BGR_REG_TWI2_RST_ASSERT

#define TWI_BGR_REG_TWI2_RST_ASSERT   0b0

◆ TWI_BGR_REG_TWI2_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI2_RST_CLEAR_MASK   0x00040000

◆ TWI_BGR_REG_TWI2_RST_DE_ASSERT

#define TWI_BGR_REG_TWI2_RST_DE_ASSERT   0b1

◆ TWI_BGR_REG_TWI2_RST_OFFSET

#define TWI_BGR_REG_TWI2_RST_OFFSET   18

◆ TWI_BGR_REG_TWI3_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK   0x00000008

◆ TWI_BGR_REG_TWI3_GATING_MASK

#define TWI_BGR_REG_TWI3_GATING_MASK   0b0

◆ TWI_BGR_REG_TWI3_GATING_OFFSET

#define TWI_BGR_REG_TWI3_GATING_OFFSET   3

◆ TWI_BGR_REG_TWI3_GATING_PASS

#define TWI_BGR_REG_TWI3_GATING_PASS   0b1

◆ TWI_BGR_REG_TWI3_RST_ASSERT

#define TWI_BGR_REG_TWI3_RST_ASSERT   0b0

◆ TWI_BGR_REG_TWI3_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI3_RST_CLEAR_MASK   0x00080000

◆ TWI_BGR_REG_TWI3_RST_DE_ASSERT

#define TWI_BGR_REG_TWI3_RST_DE_ASSERT   0b1

◆ TWI_BGR_REG_TWI3_RST_OFFSET

#define TWI_BGR_REG_TWI3_RST_OFFSET   19

◆ UART_BGR_REG

#define UART_BGR_REG   0x0000090c

◆ UART_BGR_REG_UART0_GATING_CLEAR_MASK

#define UART_BGR_REG_UART0_GATING_CLEAR_MASK   0x00000001

◆ UART_BGR_REG_UART0_GATING_MASK

#define UART_BGR_REG_UART0_GATING_MASK   0b0

◆ UART_BGR_REG_UART0_GATING_OFFSET

#define UART_BGR_REG_UART0_GATING_OFFSET   0

◆ UART_BGR_REG_UART0_GATING_PASS

#define UART_BGR_REG_UART0_GATING_PASS   0b1

◆ UART_BGR_REG_UART0_RST_ASSERT

#define UART_BGR_REG_UART0_RST_ASSERT   0b0

◆ UART_BGR_REG_UART0_RST_CLEAR_MASK

#define UART_BGR_REG_UART0_RST_CLEAR_MASK   0x00010000

◆ UART_BGR_REG_UART0_RST_DE_ASSERT

#define UART_BGR_REG_UART0_RST_DE_ASSERT   0b1

◆ UART_BGR_REG_UART0_RST_OFFSET

#define UART_BGR_REG_UART0_RST_OFFSET   16

◆ UART_BGR_REG_UART1_GATING_CLEAR_MASK

#define UART_BGR_REG_UART1_GATING_CLEAR_MASK   0x00000002

◆ UART_BGR_REG_UART1_GATING_MASK

#define UART_BGR_REG_UART1_GATING_MASK   0b0

◆ UART_BGR_REG_UART1_GATING_OFFSET

#define UART_BGR_REG_UART1_GATING_OFFSET   1

◆ UART_BGR_REG_UART1_GATING_PASS

#define UART_BGR_REG_UART1_GATING_PASS   0b1

◆ UART_BGR_REG_UART1_RST_ASSERT

#define UART_BGR_REG_UART1_RST_ASSERT   0b0

◆ UART_BGR_REG_UART1_RST_CLEAR_MASK

#define UART_BGR_REG_UART1_RST_CLEAR_MASK   0x00020000

◆ UART_BGR_REG_UART1_RST_DE_ASSERT

#define UART_BGR_REG_UART1_RST_DE_ASSERT   0b1

◆ UART_BGR_REG_UART1_RST_OFFSET

#define UART_BGR_REG_UART1_RST_OFFSET   17

◆ UART_BGR_REG_UART2_GATING_CLEAR_MASK

#define UART_BGR_REG_UART2_GATING_CLEAR_MASK   0x00000004

◆ UART_BGR_REG_UART2_GATING_MASK

#define UART_BGR_REG_UART2_GATING_MASK   0b0

◆ UART_BGR_REG_UART2_GATING_OFFSET

#define UART_BGR_REG_UART2_GATING_OFFSET   2

◆ UART_BGR_REG_UART2_GATING_PASS

#define UART_BGR_REG_UART2_GATING_PASS   0b1

◆ UART_BGR_REG_UART2_RST_ASSERT

#define UART_BGR_REG_UART2_RST_ASSERT   0b0

◆ UART_BGR_REG_UART2_RST_CLEAR_MASK

#define UART_BGR_REG_UART2_RST_CLEAR_MASK   0x00040000

◆ UART_BGR_REG_UART2_RST_DE_ASSERT

#define UART_BGR_REG_UART2_RST_DE_ASSERT   0b1

◆ UART_BGR_REG_UART2_RST_OFFSET

#define UART_BGR_REG_UART2_RST_OFFSET   18

◆ UART_BGR_REG_UART3_GATING_CLEAR_MASK

#define UART_BGR_REG_UART3_GATING_CLEAR_MASK   0x00000008

◆ UART_BGR_REG_UART3_GATING_MASK

#define UART_BGR_REG_UART3_GATING_MASK   0b0

◆ UART_BGR_REG_UART3_GATING_OFFSET

#define UART_BGR_REG_UART3_GATING_OFFSET   3

◆ UART_BGR_REG_UART3_GATING_PASS

#define UART_BGR_REG_UART3_GATING_PASS   0b1

◆ UART_BGR_REG_UART3_RST_ASSERT

#define UART_BGR_REG_UART3_RST_ASSERT   0b0

◆ UART_BGR_REG_UART3_RST_CLEAR_MASK

#define UART_BGR_REG_UART3_RST_CLEAR_MASK   0x00080000

◆ UART_BGR_REG_UART3_RST_DE_ASSERT

#define UART_BGR_REG_UART3_RST_DE_ASSERT   0b1

◆ UART_BGR_REG_UART3_RST_OFFSET

#define UART_BGR_REG_UART3_RST_OFFSET   19

◆ USB0_CLK_REG

#define USB0_CLK_REG   0x00000a70

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0b01

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0b00

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLK16M_RC   0b11

◆ USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24

◆ USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K

#define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K   0b10

◆ USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0b0

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0b1

◆ USB0_CLK_REG_USB0_CLKEN_OFFSET

#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31

◆ USB0_CLK_REG_USBPHY0_RSTN_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT   0b0

◆ USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK

#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK   0x40000000

◆ USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT   0b1

◆ USB0_CLK_REG_USBPHY0_RSTN_OFFSET

#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET   30

◆ USB_BGR_REG

#define USB_BGR_REG   0x00000a8c

◆ USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK   0x00000010

◆ USB_BGR_REG_USBEHCI0_GATING_MASK

#define USB_BGR_REG_USBEHCI0_GATING_MASK   0b0

◆ USB_BGR_REG_USBEHCI0_GATING_OFFSET

#define USB_BGR_REG_USBEHCI0_GATING_OFFSET   4

◆ USB_BGR_REG_USBEHCI0_GATING_PASS

#define USB_BGR_REG_USBEHCI0_GATING_PASS   0b1

◆ USB_BGR_REG_USBEHCI0_RST_ASSERT

#define USB_BGR_REG_USBEHCI0_RST_ASSERT   0b0

◆ USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK

#define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK   0x00100000

◆ USB_BGR_REG_USBEHCI0_RST_DE_ASSERT

#define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT   0b1

◆ USB_BGR_REG_USBEHCI0_RST_OFFSET

#define USB_BGR_REG_USBEHCI0_RST_OFFSET   20

◆ USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK   0x00000001

◆ USB_BGR_REG_USBOHCI0_GATING_MASK

#define USB_BGR_REG_USBOHCI0_GATING_MASK   0b0

◆ USB_BGR_REG_USBOHCI0_GATING_OFFSET

#define USB_BGR_REG_USBOHCI0_GATING_OFFSET   0

◆ USB_BGR_REG_USBOHCI0_GATING_PASS

#define USB_BGR_REG_USBOHCI0_GATING_PASS   0b1

◆ USB_BGR_REG_USBOHCI0_RST_ASSERT

#define USB_BGR_REG_USBOHCI0_RST_ASSERT   0b0

◆ USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK

#define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK   0x00010000

◆ USB_BGR_REG_USBOHCI0_RST_DE_ASSERT

#define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT   0b1

◆ USB_BGR_REG_USBOHCI0_RST_OFFSET

#define USB_BGR_REG_USBOHCI0_RST_OFFSET   16

◆ USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK   0x00000100

◆ USB_BGR_REG_USBOTG0_GATING_MASK

#define USB_BGR_REG_USBOTG0_GATING_MASK   0b0

◆ USB_BGR_REG_USBOTG0_GATING_OFFSET

#define USB_BGR_REG_USBOTG0_GATING_OFFSET   8

◆ USB_BGR_REG_USBOTG0_GATING_PASS

#define USB_BGR_REG_USBOTG0_GATING_PASS   0b1

◆ USB_BGR_REG_USBOTG0_RST_ASSERT

#define USB_BGR_REG_USBOTG0_RST_ASSERT   0b0

◆ USB_BGR_REG_USBOTG0_RST_CLEAR_MASK

#define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK   0x01000000

◆ USB_BGR_REG_USBOTG0_RST_DE_ASSERT

#define USB_BGR_REG_USBOTG0_RST_DE_ASSERT   0b1

◆ USB_BGR_REG_USBOTG0_RST_OFFSET

#define USB_BGR_REG_USBOTG0_RST_OFFSET   24

◆ VE_BGR_REG

#define VE_BGR_REG   0x0000069c

◆ VE_BGR_REG_VE_GATING_CLEAR_MASK

#define VE_BGR_REG_VE_GATING_CLEAR_MASK   0x00000001

◆ VE_BGR_REG_VE_GATING_MASK

#define VE_BGR_REG_VE_GATING_MASK   0b0

◆ VE_BGR_REG_VE_GATING_OFFSET

#define VE_BGR_REG_VE_GATING_OFFSET   0

◆ VE_BGR_REG_VE_GATING_PASS

#define VE_BGR_REG_VE_GATING_PASS   0b1

◆ VE_BGR_REG_VE_RST_ASSERT

#define VE_BGR_REG_VE_RST_ASSERT   0b0

◆ VE_BGR_REG_VE_RST_CLEAR_MASK

#define VE_BGR_REG_VE_RST_CLEAR_MASK   0x00010000

◆ VE_BGR_REG_VE_RST_DE_ASSERT

#define VE_BGR_REG_VE_RST_DE_ASSERT   0b1

◆ VE_BGR_REG_VE_RST_OFFSET

#define VE_BGR_REG_VE_RST_OFFSET   16

◆ VE_CLK_REG

#define VE_CLK_REG   0x00000690

◆ VE_CLK_REG_CLK_SRC_SEL_AUDIOPLL_DIV3

#define VE_CLK_REG_CLK_SRC_SEL_AUDIOPLL_DIV3   0b110

◆ VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VE_CLK_REG_CLK_SRC_SEL_CSIPLL4X

#define VE_CLK_REG_CLK_SRC_SEL_CSIPLL4X   0b101

◆ VE_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VE_CLK_REG_CLK_SRC_SEL_PERI_300M

#define VE_CLK_REG_CLK_SRC_SEL_PERI_300M   0b000

◆ VE_CLK_REG_CLK_SRC_SEL_PERI_400M

#define VE_CLK_REG_CLK_SRC_SEL_PERI_400M   0b001

◆ VE_CLK_REG_CLK_SRC_SEL_PERI_480M

#define VE_CLK_REG_CLK_SRC_SEL_PERI_480M   0b010

◆ VE_CLK_REG_CLK_SRC_SEL_PERI_600M

#define VE_CLK_REG_CLK_SRC_SEL_PERI_600M   0b011

◆ VE_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X

#define VE_CLK_REG_CLK_SRC_SEL_VIDEOPLL4X   0b100

◆ VE_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VE_CLK_REG_FACTOR_M_OFFSET

#define VE_CLK_REG_FACTOR_M_OFFSET   0

◆ VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK

#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK   0x80000000

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF   0b0

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON   0b1

◆ VE_CLK_REG_VE_CLK_GATING_OFFSET

#define VE_CLK_REG_VE_CLK_GATING_OFFSET   31

◆ VIDEOPLL_GATE_EN_REG

#define VIDEOPLL_GATE_EN_REG   0x00000e18

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_AUTO_GATE_EN_OFFSET   0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL1X_GATE_SW_CFG_OFFSET   16

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_AUTO_GATE_EN_OFFSET   1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL2X_GATE_SW_CFG_OFFSET   17

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_AUTO   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_CLEAR_MASK   0x00000004

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_NO_AUTO

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_NO_AUTO   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_AUTO_GATE_EN_OFFSET   2

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_CLEAR_MASK

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_DISABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_DISABLE   0b0

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_ENABLE

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_ENABLE   0b1

◆ VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_OFFSET

#define VIDEOPLL_GATE_EN_REG_VIDEOPLL4X_GATE_SW_CFG_OFFSET   18

◆ VIDEOPLL_GATE_STAT_REG

#define VIDEOPLL_GATE_STAT_REG   0x00000e30

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_CLEAR_MASK   0x00010000

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL1X_GATE_STAT_OFFSET   16

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_CLEAR_MASK   0x00020000

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL2X_GATE_STAT_OFFSET   17

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_CLEAR_MASK

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_CLEAR_MASK   0x00040000

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_DISABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_DISABLE   0b0

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_ENABLE

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_ENABLE   0b1

◆ VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_OFFSET

#define VIDEOPLL_GATE_STAT_REG_VIDEOPLL4X_GATE_STAT_OFFSET   18
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