This graph shows which files directly or indirectly include this file:

Macros
#define	SUNXI_FIXS_BROM_BASE 0x00000000

#define	SUNXI_HS_BROM_BASE 0x00010000

#define	SUNXI_NS_BROM_BASE 0x00015000

#define	SUNXI_SRAM_C_BASE 0x00040000

#define	SUNXI_DE_SHARE_SRAM_BASE 0x00068000

#define	SUNXI_CCMU_BASE 0x02002000

#define	SUNXI_SPC_BASE 0x02006000

#define	SUNXI_WDG_BASE 0x02050000

#define	SUNXI_IRTX_BASE 0x02080000

#define	SUNXI_IRRX0_BASE 0x02081000

#define	SUNXI_IRRX1_BASE 0x02082000

#define	SUNXI_IRRX2_BASE 0x02083000

#define	SUNXI_IRRX3_BASE 0x02084000

#define	SUNXI_LEDC_BASE 0x02085000

#define	SUNXI_THS_BASE 0x02086000

#define	SUNXI_GPADC0_BASE 0x02087000

#define	SUNXI_GPADC1_BASE 0x02088000

#define	SUNXI_GPADC2_BASE 0x02089000

#define	SUNXI_GPADC3_BASE 0x0208A000

#define	SUNXI_TPADC_BASE 0x0208C000

#define	SUNXI_PWM0_BASE 0x02090000

#define	SUNXI_PWM1_BASE 0x02091000

#define	SUNXI_PWM2_BASE 0x02092000

#define	SUNXI_AXI_MONITOR_RISCV_BASE 0x02093000

#define	SUNXI_AHB_MONITOR_CPU_BASE 0x02094000

#define	SUNXI_AHB_MONITOR_DCU_BASE 0x02095000

#define	SUNXI_ADDA_BASE 0x02030000

#define	SUNXI_DMIC_BASE 0x02031000

#define	SUNXI_I2S0_BASE 0x02032000

#define	SUNXI_I2S1_BASE 0x02033000

#define	SUNXI_I2S2_BASE 0x02034000

#define	SUNXI_OWA_BASE 0x02036000

#define	SUNXI_TWI0_BASE 0x02510000

#define	SUNXI_TWI1_BASE 0x02511000

#define	SUNXI_TWI2_BASE 0x02512000

#define	SUNXI_TWI3_BASE 0x02513000

#define	SUNXI_TWI4_BASE 0x02514000

#define	SUNXI_TWI5_BASE 0x02515000

#define	SUNXI_UART0_BASE 0x02600000

#define	SUNXI_UART1_BASE 0x02601000

#define	SUNXI_UART2_BASE 0x02602000

#define	SUNXI_UART3_BASE 0x02603000

#define	SUNXI_UART4_BASE 0x02604000

#define	SUNXI_UART5_BASE 0x02605000

#define	SUNXI_UART6_BASE 0x02606000

#define	SUNXI_UART7_BASE 0x02607000

#define	SUNXI_UART8_BASE 0x02608000

#define	SUNXI_UART9_BASE 0x02609000

#define	SUNXI_SYSCTRL_BASE 0x03000000

#define	SUNXI_DMAC0_BASE 0x03001000

#define	SUNXI_CPUX_MSGBOX_BASE 0x03003000

#define	SUNXI_SPINLOCK_BASE 0x03005000

#define	SUNXI_SID_BASE 0x03006000

#define	SUNXI_SID_BASE 0x03006000

#define	SUNXI_SECURE_DEBUG_CFG_BASE 0x03006800

#define	SUNXI_TIMER_BASE 0x03008000

#define	SUNXI_DCU_BASE 0x03010000

#define	SUNXI_CE_BASE 0x03040000

#define	SUNXI_CE_NS_BASE 0x03040000

#define	SUNXI_CE_S_BASE 0x03040800

#define	SUNXI_MEMC_BASE 0x03102000

#define	SUNXI_MEMC_COMMON_BASE 0x03110000

#define	SUNXI_MEMC_DDRC_BASE 0x03120000

#define	SUNXI_MEMC_PHY_BASE 0x03130000

#define	SUNXI_CPU_GIC400_BASE 0x03400000

#define	SUNXI_MBOX_CORE0_BASE 0x03600000

#define	SUNXI_MBOX_CORE1_BASE 0x03601000

#define	SUNXI_MBOX_CORE2_BASE 0x03602000

#define	SUNXI_MBOX_CORE3_BASE 0x03603000

#define	SUNXI_GPIO_BASE 0x03604000

#define	SUNXI_MSI_BASE 0x03606000

#define	SUNXI_SMC_BASE 0x03607000

#define	SUNXI_DMAC1_BASE 0x04000000

#define	SUNXI_SMHC0_BASE 0x04020000

#define	SUNXI_SMHC1_BASE 0x04021000

#define	SUNXI_SMHC2_BASE 0x04022000

#define	SUNXI_SMHC3_BASE 0x04023000

#define	SUNXI_SPI0_BASE 0x04025000

#define	SUNXI_SPI1_BASE 0x04026000

#define	SUNXI_SPI2_BASE 0x04027000

#define	SUNXI_SPI3_BASE 0x04028000

#define	SUNXI_USB0_BASE 0x04200000

#define	SUNXI_USB1_BASE 0x04300000

#define	SUNXI_GMAC0_BASE 0x04500000

#define	SUNXI_GMAC1_BASE 0x04510000

#define	SUNXI_GMAC2_BASE 0x04520000

#define	SUNXI_DE_BASE 0x05000000

#define	SUNXI_G2D_TOP_BASE 0x05000000

#define	SUNXI_MIXER_GLB_BASE 0x05000100

#define	SUNXI_BLD_BASE 0x05000400

#define	SUNXI_LAY0_V_CH0_BASE 0x05000800

#define	SUNXI_LAY0_UI_CH1_BASE 0x05001000

#define	SUNXI_LAY0_UI_CH2_BASE 0x05001800

#define	SUNXI_LAY0_UI_CH3_BASE 0x05002000

#define	SUNXI_WB_BASE 0x05003000

#define	SUNXI_VIDEO_SCALER_CH0_BASE 0x05008000

#define	SUNXI_ROTATE_BASE 0x05028000

#define	SUNXI_UI_SCALER1_CH1_BASE 0x05030000

#define	SUNXI_G2D_BASE 0x05440000

#define	SUNXI_DISPLAY_TOP_BASE 0x05500000

#define	SUNXI_TCON_LCD0_BASE 0x05501000

#define	SUNXI_DSI0_BASE 0x05506000

#define	SUNXI_CSI_BASE 0x05800000

#define	SUNXI_CSIC_CCU_BASE 0x05800000

#define	SUNXI_CSIC_TOP_BASE 0x05800800

#define	SUNXI_CSIC_PARSER0_BASE 0x05820000

#define	SUNXI_CSIC_PARSER1_BASE 0x05821000

#define	SUNXI_CSIC_PARSER2_BASE 0x05822000

#define	SUNXI_CSIC_DMA0_BASE 0x05830000

#define	SUNXI_CSIC_DMA1_BASE 0x05831000

#define	SUNXI_CSIC_DMA2_BASE 0x05832000

#define	SUNXI_ISP_BASE 0x05900000

#define	SUNXI_RESERVE_BASE 0x05A00000

#define	SUNXI_LOCALBUS_REG_BASE 0x02810000

#define	SUNXI_LOCALBUS_DAT_BASE 0x10000000

#define	SUNXI_R_SPC_BASE 0x07002000

#define	SUNXI_R_PRCM_BASE 0x07010000

#define	SUNXI_R_TWD_BASE 0x07022000

#define	SUNXI_CPUIDLE_BASE 0x07050000

#define	SUNXI_PCK600_QCHANNEL_BASE 0x07060000

#define	SUNXI_R_GPIO_BASE 0x07096000

#define	SUNXI_RTC_BASE 0x07090000

#define	SUNXI_CPU_CS_BASE 0x08000000

#define	SUNXI_CPU_SUBSYS_CTRL_BASE 0x08100000

#define	SUNXI_TIMESTAMP_STA_BASE 0x08110000

#define	SUNXI_TIMESTAMP_CTRL_BASE 0x08120000

#define	SUNXI_CPU_IDC_BASE 0x08130000

#define	SUNXI_CPUX_PLL_CFG_BASE 0x08140000

#define	SUNXI_C0_CPUX_CFG_BASE 0x09010000

#define	SUNXI_CLUSTER0_MBIST_BASE 0x09020000

#define	SUNXI_SPI_FLASH_BASE 0x02800000

#define	SUNXI_SPI_FLASH_XIP_BASE 0x0E000000

#define	SUNXI_MCU_CFG_BASE 0x01A00000

#define	SUNXI_MCU_WDG_BASE 0x01A02000

#define	SUNXI_MCU_LCNT_BASE 0x01A04000

#define	SUNXI_MCU_MBOX_BASE 0x01A06000

#define	SUNXI_MCU_TIMER_BASE 0x01A08000

#define	SUNXI_MCU_CLINT_BASE 0x30000000

#define	SUNXI_MCU_CLIC_BASE 0x30800000

#define	SUNXI_MCU_SYSMAP_BASE 0x3FFFF000

#define	SUNXI_PIO_BASE (SUNXI_GPIO_BASE)

#define	SUNXI_RPIO_BASE (SUNXI_R_GPIO_BASE)

#define	SUNXI_CCM_BASE (SUNXI_CCMU_BASE)

#define	SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)

#define	SUNXI_DMA_BASE (SUNXI_DMAC0_BASE)

#define	SUNXI_GPADC_BASE (SUNXI_GPADC0_BASE)

#define	SUNXI_SS_BASE (SUNXI_CE_BASE)

#define	SUNXI_WDOG_BASE (SUNXI_WDG_BASE)

#define	SUNXI_RTWI_BASE (SUNXI_TWI0_BASE)

#define	SUNXI_RTWI_BRG_REG (SUNXI_CCMU_BASE + 0x0E80)

#define	VCC33_DET_CTRL_REG (0x1f4)

#define	VCCIO_THRESHOLD_MASK (0xff)

#define	VCCIO_THRESHOLD_VOLTAGE_2_5 (0 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_6 (1 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_7 (2 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_8 (3 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_2_9 (3 << 4)

#define	VCCIO_THRESHOLD_VOLTAGE_3_0 (4 << 4)

#define	FORCE_DETECTER_OUTPUT (1 << 7)

#define	VCCIO_DET_BYPASS_EN (1 << 0)

#define	CCM_UART_PLATFORM_ADDR_OFFSET (SUNXI_UART1_BASE - SUNXI_UART0_BASE)

#define	SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)

Macro Definition Documentation

◆ CCM_UART_PLATFORM_ADDR_OFFSET

#define CCM_UART_PLATFORM_ADDR_OFFSET (SUNXI_UART1_BASE - SUNXI_UART0_BASE)

◆ FORCE_DETECTER_OUTPUT

#define FORCE_DETECTER_OUTPUT (1 << 7)

◆ SUNXI_ADDA_BASE

#define SUNXI_ADDA_BASE 0x02030000

◆ SUNXI_AHB_MONITOR_CPU_BASE

#define SUNXI_AHB_MONITOR_CPU_BASE 0x02094000

◆ SUNXI_AHB_MONITOR_DCU_BASE

#define SUNXI_AHB_MONITOR_DCU_BASE 0x02095000

◆ SUNXI_AXI_MONITOR_RISCV_BASE

#define SUNXI_AXI_MONITOR_RISCV_BASE 0x02093000

◆ SUNXI_BLD_BASE

#define SUNXI_BLD_BASE 0x05000400

◆ SUNXI_C0_CPUX_CFG_BASE

#define SUNXI_C0_CPUX_CFG_BASE 0x09010000

◆ SUNXI_CCM_BASE

#define SUNXI_CCM_BASE (SUNXI_CCMU_BASE)

◆ SUNXI_CCMU_BASE

#define SUNXI_CCMU_BASE 0x02002000

◆ SUNXI_CE_BASE

#define SUNXI_CE_BASE 0x03040000

◆ SUNXI_CE_NS_BASE

#define SUNXI_CE_NS_BASE 0x03040000

◆ SUNXI_CE_S_BASE

#define SUNXI_CE_S_BASE 0x03040800

◆ SUNXI_CLUSTER0_MBIST_BASE

#define SUNXI_CLUSTER0_MBIST_BASE 0x09020000

◆ SUNXI_CPU_CS_BASE

#define SUNXI_CPU_CS_BASE 0x08000000

◆ SUNXI_CPU_GIC400_BASE

#define SUNXI_CPU_GIC400_BASE 0x03400000

◆ SUNXI_CPU_IDC_BASE

#define SUNXI_CPU_IDC_BASE 0x08130000

◆ SUNXI_CPU_SUBSYS_CTRL_BASE

#define SUNXI_CPU_SUBSYS_CTRL_BASE 0x08100000

◆ SUNXI_CPUIDLE_BASE

#define SUNXI_CPUIDLE_BASE 0x07050000

◆ SUNXI_CPUX_MSGBOX_BASE

#define SUNXI_CPUX_MSGBOX_BASE 0x03003000

◆ SUNXI_CPUX_PLL_CFG_BASE

#define SUNXI_CPUX_PLL_CFG_BASE 0x08140000

◆ SUNXI_CSI_BASE

#define SUNXI_CSI_BASE 0x05800000

◆ SUNXI_CSIC_CCU_BASE

#define SUNXI_CSIC_CCU_BASE 0x05800000

◆ SUNXI_CSIC_DMA0_BASE

#define SUNXI_CSIC_DMA0_BASE 0x05830000

◆ SUNXI_CSIC_DMA1_BASE

#define SUNXI_CSIC_DMA1_BASE 0x05831000

◆ SUNXI_CSIC_DMA2_BASE

#define SUNXI_CSIC_DMA2_BASE 0x05832000

◆ SUNXI_CSIC_PARSER0_BASE

#define SUNXI_CSIC_PARSER0_BASE 0x05820000

◆ SUNXI_CSIC_PARSER1_BASE

#define SUNXI_CSIC_PARSER1_BASE 0x05821000

◆ SUNXI_CSIC_PARSER2_BASE

#define SUNXI_CSIC_PARSER2_BASE 0x05822000

◆ SUNXI_CSIC_TOP_BASE

#define SUNXI_CSIC_TOP_BASE 0x05800800

◆ SUNXI_DCU_BASE

#define SUNXI_DCU_BASE 0x03010000

◆ SUNXI_DE_BASE

#define SUNXI_DE_BASE 0x05000000

◆ SUNXI_DE_SHARE_SRAM_BASE

#define SUNXI_DE_SHARE_SRAM_BASE 0x00068000

◆ SUNXI_DISPLAY_TOP_BASE

#define SUNXI_DISPLAY_TOP_BASE 0x05500000

◆ SUNXI_DMA_BASE

#define SUNXI_DMA_BASE (SUNXI_DMAC0_BASE)

◆ SUNXI_DMAC0_BASE

#define SUNXI_DMAC0_BASE 0x03001000

◆ SUNXI_DMAC1_BASE

#define SUNXI_DMAC1_BASE 0x04000000

◆ SUNXI_DMIC_BASE

#define SUNXI_DMIC_BASE 0x02031000

◆ SUNXI_DSI0_BASE

#define SUNXI_DSI0_BASE 0x05506000

◆ SUNXI_FIXS_BROM_BASE

#define SUNXI_FIXS_BROM_BASE 0x00000000

◆ SUNXI_G2D_BASE

#define SUNXI_G2D_BASE 0x05440000

◆ SUNXI_G2D_TOP_BASE

#define SUNXI_G2D_TOP_BASE 0x05000000

◆ SUNXI_GMAC0_BASE

#define SUNXI_GMAC0_BASE 0x04500000

◆ SUNXI_GMAC1_BASE

#define SUNXI_GMAC1_BASE 0x04510000

◆ SUNXI_GMAC2_BASE

#define SUNXI_GMAC2_BASE 0x04520000

◆ SUNXI_GPADC0_BASE

#define SUNXI_GPADC0_BASE 0x02087000

◆ SUNXI_GPADC1_BASE

#define SUNXI_GPADC1_BASE 0x02088000

◆ SUNXI_GPADC2_BASE

#define SUNXI_GPADC2_BASE 0x02089000

◆ SUNXI_GPADC3_BASE

#define SUNXI_GPADC3_BASE 0x0208A000

◆ SUNXI_GPADC_BASE

#define SUNXI_GPADC_BASE (SUNXI_GPADC0_BASE)

◆ SUNXI_GPIO_BASE

#define SUNXI_GPIO_BASE 0x03604000

◆ SUNXI_HS_BROM_BASE

#define SUNXI_HS_BROM_BASE 0x00010000

◆ SUNXI_I2S0_BASE

#define SUNXI_I2S0_BASE 0x02032000

◆ SUNXI_I2S1_BASE

#define SUNXI_I2S1_BASE 0x02033000

◆ SUNXI_I2S2_BASE

#define SUNXI_I2S2_BASE 0x02034000

◆ SUNXI_IRRX0_BASE

#define SUNXI_IRRX0_BASE 0x02081000

◆ SUNXI_IRRX1_BASE

#define SUNXI_IRRX1_BASE 0x02082000

◆ SUNXI_IRRX2_BASE

#define SUNXI_IRRX2_BASE 0x02083000

◆ SUNXI_IRRX3_BASE

#define SUNXI_IRRX3_BASE 0x02084000

◆ SUNXI_IRTX_BASE

#define SUNXI_IRTX_BASE 0x02080000

◆ SUNXI_ISP_BASE

#define SUNXI_ISP_BASE 0x05900000

◆ SUNXI_LAY0_UI_CH1_BASE

#define SUNXI_LAY0_UI_CH1_BASE 0x05001000

◆ SUNXI_LAY0_UI_CH2_BASE

#define SUNXI_LAY0_UI_CH2_BASE 0x05001800

◆ SUNXI_LAY0_UI_CH3_BASE

#define SUNXI_LAY0_UI_CH3_BASE 0x05002000

◆ SUNXI_LAY0_V_CH0_BASE

#define SUNXI_LAY0_V_CH0_BASE 0x05000800

◆ SUNXI_LEDC_BASE

#define SUNXI_LEDC_BASE 0x02085000

◆ SUNXI_LOCALBUS_DAT_BASE

#define SUNXI_LOCALBUS_DAT_BASE 0x10000000

◆ SUNXI_LOCALBUS_REG_BASE

#define SUNXI_LOCALBUS_REG_BASE 0x02810000

◆ SUNXI_MBOX_CORE0_BASE

#define SUNXI_MBOX_CORE0_BASE 0x03600000

◆ SUNXI_MBOX_CORE1_BASE

#define SUNXI_MBOX_CORE1_BASE 0x03601000

◆ SUNXI_MBOX_CORE2_BASE

#define SUNXI_MBOX_CORE2_BASE 0x03602000

◆ SUNXI_MBOX_CORE3_BASE

#define SUNXI_MBOX_CORE3_BASE 0x03603000

◆ SUNXI_MCU_CFG_BASE

#define SUNXI_MCU_CFG_BASE 0x01A00000

◆ SUNXI_MCU_CLIC_BASE

#define SUNXI_MCU_CLIC_BASE 0x30800000

◆ SUNXI_MCU_CLINT_BASE

#define SUNXI_MCU_CLINT_BASE 0x30000000

◆ SUNXI_MCU_LCNT_BASE

#define SUNXI_MCU_LCNT_BASE 0x01A04000

◆ SUNXI_MCU_MBOX_BASE

#define SUNXI_MCU_MBOX_BASE 0x01A06000

◆ SUNXI_MCU_SYSMAP_BASE

#define SUNXI_MCU_SYSMAP_BASE 0x3FFFF000

◆ SUNXI_MCU_TIMER_BASE

#define SUNXI_MCU_TIMER_BASE 0x01A08000

◆ SUNXI_MCU_WDG_BASE

#define SUNXI_MCU_WDG_BASE 0x01A02000

◆ SUNXI_MEMC_BASE

#define SUNXI_MEMC_BASE 0x03102000

◆ SUNXI_MEMC_COMMON_BASE

#define SUNXI_MEMC_COMMON_BASE 0x03110000

◆ SUNXI_MEMC_DDRC_BASE

#define SUNXI_MEMC_DDRC_BASE 0x03120000

◆ SUNXI_MEMC_PHY_BASE

#define SUNXI_MEMC_PHY_BASE 0x03130000

◆ SUNXI_MIXER_GLB_BASE

#define SUNXI_MIXER_GLB_BASE 0x05000100

◆ SUNXI_MSI_BASE

#define SUNXI_MSI_BASE 0x03606000

◆ SUNXI_NS_BROM_BASE

#define SUNXI_NS_BROM_BASE 0x00015000

◆ SUNXI_OWA_BASE

#define SUNXI_OWA_BASE 0x02036000

◆ SUNXI_PCK600_QCHANNEL_BASE

#define SUNXI_PCK600_QCHANNEL_BASE 0x07060000

◆ SUNXI_PIO_BASE

#define SUNXI_PIO_BASE (SUNXI_GPIO_BASE)

◆ SUNXI_PWM0_BASE

#define SUNXI_PWM0_BASE 0x02090000

◆ SUNXI_PWM1_BASE

#define SUNXI_PWM1_BASE 0x02091000

◆ SUNXI_PWM2_BASE

#define SUNXI_PWM2_BASE 0x02092000

◆ SUNXI_R_GPIO_BASE

#define SUNXI_R_GPIO_BASE 0x07096000

◆ SUNXI_R_PRCM_BASE

#define SUNXI_R_PRCM_BASE 0x07010000

◆ SUNXI_R_SPC_BASE

#define SUNXI_R_SPC_BASE 0x07002000

◆ SUNXI_R_TWD_BASE

#define SUNXI_R_TWD_BASE 0x07022000

◆ SUNXI_RESERVE_BASE

#define SUNXI_RESERVE_BASE 0x05A00000

◆ SUNXI_ROTATE_BASE

#define SUNXI_ROTATE_BASE 0x05028000

◆ SUNXI_RPIO_BASE

#define SUNXI_RPIO_BASE (SUNXI_R_GPIO_BASE)

◆ SUNXI_RTC_BASE

#define SUNXI_RTC_BASE 0x07090000

◆ SUNXI_RTC_DATA_BASE

#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)

◆ SUNXI_RTWI_BASE

#define SUNXI_RTWI_BASE (SUNXI_TWI0_BASE)

◆ SUNXI_RTWI_BRG_REG

#define SUNXI_RTWI_BRG_REG (SUNXI_CCMU_BASE + 0x0E80)

◆ SUNXI_SECURE_DEBUG_CFG_BASE

#define SUNXI_SECURE_DEBUG_CFG_BASE 0x03006800

◆ SUNXI_SID_BASE [1/2]

#define SUNXI_SID_BASE 0x03006000

◆ SUNXI_SID_BASE [2/2]

#define SUNXI_SID_BASE 0x03006000

◆ SUNXI_SID_SRAM_BASE

#define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)

◆ SUNXI_SMC_BASE

#define SUNXI_SMC_BASE 0x03607000

◆ SUNXI_SMHC0_BASE

#define SUNXI_SMHC0_BASE 0x04020000

◆ SUNXI_SMHC1_BASE

#define SUNXI_SMHC1_BASE 0x04021000

◆ SUNXI_SMHC2_BASE

#define SUNXI_SMHC2_BASE 0x04022000

◆ SUNXI_SMHC3_BASE

#define SUNXI_SMHC3_BASE 0x04023000

◆ SUNXI_SPC_BASE

#define SUNXI_SPC_BASE 0x02006000

◆ SUNXI_SPI0_BASE

#define SUNXI_SPI0_BASE 0x04025000

◆ SUNXI_SPI1_BASE

#define SUNXI_SPI1_BASE 0x04026000

◆ SUNXI_SPI2_BASE

#define SUNXI_SPI2_BASE 0x04027000

◆ SUNXI_SPI3_BASE

#define SUNXI_SPI3_BASE 0x04028000

◆ SUNXI_SPI_FLASH_BASE

#define SUNXI_SPI_FLASH_BASE 0x02800000

◆ SUNXI_SPI_FLASH_XIP_BASE

#define SUNXI_SPI_FLASH_XIP_BASE 0x0E000000

◆ SUNXI_SPINLOCK_BASE

#define SUNXI_SPINLOCK_BASE 0x03005000

◆ SUNXI_SRAM_C_BASE

#define SUNXI_SRAM_C_BASE 0x00040000

◆ SUNXI_SS_BASE

#define SUNXI_SS_BASE (SUNXI_CE_BASE)

◆ SUNXI_SYSCTRL_BASE

#define SUNXI_SYSCTRL_BASE 0x03000000

◆ SUNXI_TCON_LCD0_BASE

#define SUNXI_TCON_LCD0_BASE 0x05501000

◆ SUNXI_THS_BASE

#define SUNXI_THS_BASE 0x02086000

◆ SUNXI_TIMER_BASE

#define SUNXI_TIMER_BASE 0x03008000

◆ SUNXI_TIMESTAMP_CTRL_BASE

#define SUNXI_TIMESTAMP_CTRL_BASE 0x08120000

◆ SUNXI_TIMESTAMP_STA_BASE

#define SUNXI_TIMESTAMP_STA_BASE 0x08110000

◆ SUNXI_TPADC_BASE

#define SUNXI_TPADC_BASE 0x0208C000

◆ SUNXI_TWI0_BASE

#define SUNXI_TWI0_BASE 0x02510000

◆ SUNXI_TWI1_BASE

#define SUNXI_TWI1_BASE 0x02511000

◆ SUNXI_TWI2_BASE

#define SUNXI_TWI2_BASE 0x02512000

◆ SUNXI_TWI3_BASE

#define SUNXI_TWI3_BASE 0x02513000

◆ SUNXI_TWI4_BASE

#define SUNXI_TWI4_BASE 0x02514000

◆ SUNXI_TWI5_BASE

#define SUNXI_TWI5_BASE 0x02515000

◆ SUNXI_UART0_BASE

#define SUNXI_UART0_BASE 0x02600000

◆ SUNXI_UART1_BASE

#define SUNXI_UART1_BASE 0x02601000

◆ SUNXI_UART2_BASE

#define SUNXI_UART2_BASE 0x02602000

◆ SUNXI_UART3_BASE

#define SUNXI_UART3_BASE 0x02603000

◆ SUNXI_UART4_BASE

#define SUNXI_UART4_BASE 0x02604000

◆ SUNXI_UART5_BASE

#define SUNXI_UART5_BASE 0x02605000

◆ SUNXI_UART6_BASE

#define SUNXI_UART6_BASE 0x02606000

◆ SUNXI_UART7_BASE

#define SUNXI_UART7_BASE 0x02607000

◆ SUNXI_UART8_BASE

#define SUNXI_UART8_BASE 0x02608000

◆ SUNXI_UART9_BASE

#define SUNXI_UART9_BASE 0x02609000

◆ SUNXI_UI_SCALER1_CH1_BASE

#define SUNXI_UI_SCALER1_CH1_BASE 0x05030000

◆ SUNXI_USB0_BASE

#define SUNXI_USB0_BASE 0x04200000

◆ SUNXI_USB1_BASE

#define SUNXI_USB1_BASE 0x04300000

◆ SUNXI_VIDEO_SCALER_CH0_BASE

#define SUNXI_VIDEO_SCALER_CH0_BASE 0x05008000

◆ SUNXI_WB_BASE

#define SUNXI_WB_BASE 0x05003000

◆ SUNXI_WDG_BASE

#define SUNXI_WDG_BASE 0x02050000

◆ SUNXI_WDOG_BASE

#define SUNXI_WDOG_BASE (SUNXI_WDG_BASE)

◆ VCC33_DET_CTRL_REG

#define VCC33_DET_CTRL_REG (0x1f4)

◆ VCCIO_DET_BYPASS_EN

#define VCCIO_DET_BYPASS_EN (1 << 0)

◆ VCCIO_THRESHOLD_MASK

#define VCCIO_THRESHOLD_MASK (0xff)

◆ VCCIO_THRESHOLD_VOLTAGE_2_5

#define VCCIO_THRESHOLD_VOLTAGE_2_5 (0 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_6

#define VCCIO_THRESHOLD_VOLTAGE_2_6 (1 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_7

#define VCCIO_THRESHOLD_VOLTAGE_2_7 (2 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_8

#define VCCIO_THRESHOLD_VOLTAGE_2_8 (3 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_2_9

#define VCCIO_THRESHOLD_VOLTAGE_2_9 (3 << 4)

◆ VCCIO_THRESHOLD_VOLTAGE_3_0

#define VCCIO_THRESHOLD_VOLTAGE_3_0 (4 << 4)

Macros