SyterKit 0.4.0.x
SyterKit is a bare-metal framework
Loading...
Searching...
No Matches
Macros
reg-ccu.h File Reference
#include <reg-ncat.h>
Include dependency graph for reg-ccu.h:

Go to the source code of this file.

Macros

#define PLL_CPU0_CTRL_REG   0x00000000
 
#define PLL_CPU0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CPU0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU0_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_CPU0_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_CPU0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CPU0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CPU0_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_CPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_OFFSET   24
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000
 
#define PLL_CPU0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_CPU0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_CPU0_CTRL_REG_PLL_M_OFFSET   0
 
#define PLL_CPU0_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003
 
#define PLL_CPU1_CTRL_REG   0x00000004
 
#define PLL_CPU1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CPU1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU1_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_CPU1_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_CPU1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CPU1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CPU1_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_CPU1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_OFFSET   24
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000
 
#define PLL_CPU1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_CPU1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_CPU1_CTRL_REG_PLL_M_OFFSET   0
 
#define PLL_CPU1_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003
 
#define PLL_CPU2_CTRL_REG   0x00000008
 
#define PLL_CPU2_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CPU2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU2_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_CPU2_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_CPU2_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CPU2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CPU2_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_CPU2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_OFFSET   24
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000
 
#define PLL_CPU2_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_CPU2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_CPU2_CTRL_REG_PLL_M_OFFSET   0
 
#define PLL_CPU2_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003
 
#define PLL_CPU3_CTRL_REG   0x00000008
 
#define PLL_CPU3_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_CPU3_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_CPU3_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_CPU3_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_CPU3_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_CPU3_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_CPU3_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_CPU3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_OFFSET   24
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000
 
#define PLL_CPU3_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_CPU3_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_CPU3_CTRL_REG_PLL_M_OFFSET   0
 
#define PLL_DDR_CTRL_REG   0x00000010
 
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_PERI0_CTRL_REG   0x00000020
 
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_PERI1_CTRL_REG   0x00000028
 
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET   20
 
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000
 
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET   16
 
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000
 
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET   2
 
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_GPU_CTRL_REG   0x00000030
 
#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_GPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_GPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO0_CTRL_REG   0x00000040
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO1_CTRL_REG   0x00000048
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO2_CTRL_REG   0x00000050
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VE_CTRL_REG   0x00000058
 
#define PLL_VE_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VE_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_VE_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_VE_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VE_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_VE_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_VIDEO3_CTRL_REG   0x00000068
 
#define PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_AUDIO_CTRL_REG   0x00000078
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_AUDIO_CTRL_REG_PLL_P_OFFSET   16
 
#define PLL_AUDIO_CTRL_REG_PLL_P_CLEAR_MASK   0x003f0000
 
#define PLL_AUDIO_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_AUDIO_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_NPU_CTRL_REG   0x00000080
 
#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31
 
#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000
 
#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0x0
 
#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0x1
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0x0
 
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0x1
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0x0
 
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0x1
 
#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28
 
#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000
 
#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0x0
 
#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET   24
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE   0x0
 
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE   0x1
 
#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8
 
#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01
 
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0
 
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1
 
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0
 
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001
 
#define PLL_DDR_PAT0_CTRL_REG   0x00000110
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_DDR_PAT1_CTRL_REG   0x00000114
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI0_PAT0_CTRL_REG   0x00000120
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI0_PAT1_CTRL_REG   0x00000124
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI1_PAT0_CTRL_REG   0x00000128
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_PERI1_PAT1_CTRL_REG   0x0000012c
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_GPU_PAT0_CTRL_REG   0x00000130
 
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_GPU_PAT1_CTRL_REG   0x00000134
 
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000140
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO0_PAT1_CTRL_REG   0x00000144
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000150
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO2_PAT1_CTRL_REG   0x00000154
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VE_PAT0_CTRL_REG   0x00000158
 
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VE_PAT1_CTRL_REG   0x0000015c
 
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO3_PAT0_CTRL_REG   0x00000168
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_VIDEO3_PAT1_CTRL_REG   0x0000016c
 
#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO_PAT0_CTRL_REG   0x00000178
 
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_AUDIO_PAT1_CTRL_REG   0x0000017c
 
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_NPU_PAT0_CTRL_REG   0x00000180
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31
 
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10
 
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0
 
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0x01
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10
 
#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0x11
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0
 
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff
 
#define PLL_NPU_PAT1_CTRL_REG   0x00000184
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24
 
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0
 
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff
 
#define PLL_CPU0_BIAS_REG   0x00000300
 
#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31
 
#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000
 
#define PLL_CPU0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_CPU0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_CPU1_BIAS_REG   0x00000308
 
#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31
 
#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000
 
#define PLL_CPU1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_CPU1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_CPU2_BIAS_REG   0x0000030c
 
#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31
 
#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000
 
#define PLL_CPU2_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_CPU2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_DDR_BIAS_REG   0x00000310
 
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_PERI0_BIAS_REG   0x00000320
 
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_PERI1_BIAS_REG   0x00000328
 
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_GPU_BIAS_REG   0x00000330
 
#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO0_BIAS_REG   0x00000340
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO1_BIAS_REG   0x00000348
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO2_BIAS_REG   0x00000350
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VE_BIAS_REG   0x00000358
 
#define PLL_VE_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_VIDEO3_BIAS_REG   0x00000368
 
#define PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_AUDIO_BIAS_REG   0x00000378
 
#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_NPU_BIAS_REG   0x00000380
 
#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16
 
#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000
 
#define PLL_CPU0_TUN_REG   0x00000400
 
#define PLL_CPU0_TUN_REG_PLL_VCO_OFFSET   28
 
#define PLL_CPU0_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000
 
#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_OFFSET   24
 
#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000
 
#define PLL_CPU0_TUN_REG_PLL_CNT_INT_OFFSET   16
 
#define PLL_CPU0_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000
 
#define PLL_CPU0_TUN_REG_PLL_REG_OD_OFFSET   15
 
#define PLL_CPU0_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000
 
#define PLL_CPU0_TUN_REG_PLL_B_IN_OFFSET   8
 
#define PLL_CPU0_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00
 
#define PLL_CPU0_TUN_REG_PLL_REG_OD1_OFFSET   7
 
#define PLL_CPU0_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080
 
#define PLL_CPU0_TUN_REG_PLL_B_OUT_OFFSET   0
 
#define PLL_CPU0_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f
 
#define PLL_CPU1_TUN_REG   0x00000408
 
#define PLL_CPU1_TUN_REG_PLL_VCO_OFFSET   28
 
#define PLL_CPU1_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000
 
#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_OFFSET   24
 
#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000
 
#define PLL_CPU1_TUN_REG_PLL_CNT_INT_OFFSET   16
 
#define PLL_CPU1_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000
 
#define PLL_CPU1_TUN_REG_PLL_REG_OD_OFFSET   15
 
#define PLL_CPU1_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000
 
#define PLL_CPU1_TUN_REG_PLL_B_IN_OFFSET   8
 
#define PLL_CPU1_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00
 
#define PLL_CPU1_TUN_REG_PLL_REG_OD1_OFFSET   7
 
#define PLL_CPU1_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080
 
#define PLL_CPU1_TUN_REG_PLL_B_OUT_OFFSET   0
 
#define PLL_CPU1_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f
 
#define PLL_CPU2_TUN_REG   0x0000040c
 
#define PLL_CPU2_TUN_REG_PLL_VCO_OFFSET   28
 
#define PLL_CPU2_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000
 
#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_OFFSET   24
 
#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000
 
#define PLL_CPU2_TUN_REG_PLL_CNT_INT_OFFSET   16
 
#define PLL_CPU2_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000
 
#define PLL_CPU2_TUN_REG_PLL_REG_OD_OFFSET   15
 
#define PLL_CPU2_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000
 
#define PLL_CPU2_TUN_REG_PLL_B_IN_OFFSET   8
 
#define PLL_CPU2_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00
 
#define PLL_CPU2_TUN_REG_PLL_REG_OD1_OFFSET   7
 
#define PLL_CPU2_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080
 
#define PLL_CPU2_TUN_REG_PLL_B_OUT_OFFSET   0
 
#define PLL_CPU2_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f
 
#define CPU_CLK_REG   0x00000500
 
#define CPU_CLK_REG_CPU_CLK_SEL_OFFSET   24
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK   0x07000000
 
#define CPU_CLK_REG_CPU_CLK_SEL_HOSC   0x000
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLK32K   0x001
 
#define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC   0x010
 
#define CPU_CLK_REG_CPU_CLK_SEL_CPU0PLL_P   0x011
 
#define CPU_CLK_REG_CPU_CLK_SEL_PERI0_600M   0x100
 
#define CPU_CLK_REG_CPU_CLK_SEL_CPU2PLL   0x101
 
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_OFFSET   16
 
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_CLEAR_MASK   0x00030000
 
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_1   0x00
 
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_2   0x01
 
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_4   0x10
 
#define CPU_CLK_REG_CPU_APB_DIV_CFG_OFFSET   8
 
#define CPU_CLK_REG_CPU_APB_DIV_CFG_CLEAR_MASK   0x00000300
 
#define CPU_CLK_REG_CPU_PERI_DIV_CFG_OFFSET   2
 
#define CPU_CLK_REG_CPU_PERI_DIV_CFG_CLEAR_MASK   0x0000000c
 
#define CPU_CLK_REG_CPU_PERI_DIV_CFG__M__FACTOR_M1__1   0x1
 
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET   0
 
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK   0x00000003
 
#define CPU_GATING_REG   0x00000504
 
#define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET   16
 
#define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK   0xffff0000
 
#define CPU_GATING_REG_CPU_GATING_FIELD_0_SIGNAL   0x15
 
#define CPU_GATING_REG_DSU_CLK_GATING_OFFSET   1
 
#define CPU_GATING_REG_DSU_CLK_GATING_CLEAR_MASK   0x00000002
 
#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CPU_GATING_REG_CPU0_CLK_GATING_OFFSET   0
 
#define CPU_GATING_REG_CPU0_CLK_GATING_CLEAR_MASK   0x00000001
 
#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define TRACE_CLK_REG   0x00000508
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET   31
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON   0x1
 
#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TRACE_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K   0x001
 
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x010
 
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x011
 
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x100
 
#define TRACE_CLK_REG_FACTOR_M_OFFSET   0
 
#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DSU_CLK_REG   0x0000050c
 
#define DSU_CLK_REG_DSU_CLK_SEL_OFFSET   24
 
#define DSU_CLK_REG_DSU_CLK_SEL_CLEAR_MASK   0x07000000
 
#define DSU_CLK_REG_DSU_CLK_SEL_HOSC   0x000
 
#define DSU_CLK_REG_DSU_CLK_SEL_CLK32K   0x001
 
#define DSU_CLK_REG_DSU_CLK_SEL_CLK16M_RC   0x010
 
#define DSU_CLK_REG_DSU_CLK_SEL_CPU1PLL_P   0x011
 
#define DSU_CLK_REG_DSU_CLK_SEL_PERI0PLL2X   0x100
 
#define DSU_CLK_REG_DSU_CLK_SEL_PERI0_600M   0x101
 
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_OFFSET   16
 
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_CLEAR_MASK   0x00030000
 
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_1   0x00
 
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_2   0x01
 
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_4   0x10
 
#define AHB_CLK_REG   0x00000510
 
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define AHB_CLK_REG_CLK_SRC_SEL_HOSC   0x00
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0x01
 
#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10
 
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11
 
#define AHB_CLK_REG_FACTOR_M_OFFSET   0
 
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB0_CLK_REG   0x00000520
 
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB0_CLK_REG_CLK_SRC_SEL_HOSC   0x00
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0x01
 
#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10
 
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11
 
#define APB0_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define APB1_CLK_REG   0x00000524
 
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define APB1_CLK_REG_CLK_SRC_SEL_HOSC   0x00
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0x01
 
#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10
 
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11
 
#define APB1_CLK_REG_FACTOR_M_OFFSET   0
 
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define MBUS_CLK_REG   0x00000540
 
#define MBUS_CLK_REG_SCLK_GATING_OFFSET   31
 
#define MBUS_CLK_REG_SCLK_GATING_CLEAR_MASK   0x80000000
 
#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_OFF   0x0
 
#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_ON   0x1
 
#define MBUS_CLK_REG_MBUS_RST_OFFSET   30
 
#define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK   0x40000000
 
#define MBUS_CLK_REG_MBUS_RST_ASSERT   0x0
 
#define MBUS_CLK_REG_MBUS_RST_DE_ASSERT   0x1
 
#define MBUS_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define MBUS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define MBUS_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define MBUS_CLK_REG_CLK_SRC_SEL_DDRPLL   0x001
 
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010
 
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x011
 
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x100
 
#define MBUS_CLK_REG_FACTOR_M_OFFSET   0
 
#define MBUS_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define NSI_BGR_REG   0x0000054c
 
#define NSI_BGR_REG_NSI_RST_OFFSET   16
 
#define NSI_BGR_REG_NSI_RST_CLEAR_MASK   0x00010000
 
#define NSI_BGR_REG_NSI_RST_ASSERT   0x0
 
#define NSI_BGR_REG_NSI_RST_DE_ASSERT   0x1
 
#define NSI_BGR_REG_NSI_GATING_OFFSET   0
 
#define NSI_BGR_REG_NSI_GATING_CLEAR_MASK   0x00000001
 
#define NSI_BGR_REG_NSI_GATING_MASK   0x0
 
#define NSI_BGR_REG_NSI_GATING_PASS   0x1
 
#define GIC_CLK_REG   0x00000550
 
#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET   31
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON   0x1
 
#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000
 
#define GIC_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K   0x001
 
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010
 
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x011
 
#define GIC_CLK_REG_FACTOR_M_OFFSET   0
 
#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DE0_CLK_REG   0x00000600
 
#define DE0_CLK_REG_DE_CLK_GATING_OFFSET   31
 
#define DE0_CLK_REG_DE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000
 
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100
 
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x101
 
#define DE0_CLK_REG_FACTOR_M_OFFSET   0
 
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DE_BGR_REG   0x0000060c
 
#define DE_BGR_REG_DE0_RST_OFFSET   16
 
#define DE_BGR_REG_DE0_RST_CLEAR_MASK   0x00010000
 
#define DE_BGR_REG_DE0_RST_ASSERT   0x0
 
#define DE_BGR_REG_DE0_RST_DE_ASSERT   0x1
 
#define DE_BGR_REG_DE0_GATING_OFFSET   0
 
#define DE_BGR_REG_DE0_GATING_CLEAR_MASK   0x00000001
 
#define DE_BGR_REG_DE0_GATING_MASK   0x0
 
#define DE_BGR_REG_DE0_GATING_PASS   0x1
 
#define DI_CLK_REG   0x00000620
 
#define DI_CLK_REG_DI_CLK_GATING_OFFSET   31
 
#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x000
 
#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define DI_CLK_REG_FACTOR_M_OFFSET   0
 
#define DI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DI_BGR_REG   0x0000062c
 
#define DI_BGR_REG_DI_RST_OFFSET   16
 
#define DI_BGR_REG_DI_RST_CLEAR_MASK   0x00010000
 
#define DI_BGR_REG_DI_RST_ASSERT   0x0
 
#define DI_BGR_REG_DI_RST_DE_ASSERT   0x1
 
#define DI_BGR_REG_DI_GATING_OFFSET   0
 
#define DI_BGR_REG_DI_GATING_CLEAR_MASK   0x00000001
 
#define DI_BGR_REG_DI_GATING_MASK   0x0
 
#define DI_BGR_REG_DI_GATING_PASS   0x1
 
#define G2D_CLK_REG   0x00000630
 
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0x1
 
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x000
 
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001
 
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define G2D_CLK_REG_FACTOR_M_OFFSET   0
 
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define G2D_BGR_REG   0x0000063c
 
#define G2D_BGR_REG_G2D_RST_OFFSET   16
 
#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   0x00010000
 
#define G2D_BGR_REG_G2D_RST_ASSERT   0x0
 
#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0x1
 
#define G2D_BGR_REG_G2D_GATING_OFFSET   0
 
#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   0x00000001
 
#define G2D_BGR_REG_G2D_GATING_MASK   0x0
 
#define G2D_BGR_REG_G2D_GATING_PASS   0x1
 
#define GPU_CORE_CLK_REG   0x00000670
 
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_OFFSET   31
 
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_ON   0x1
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_GPUPLL   0x000
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x001
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x011
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x100
 
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x101
 
#define GPU_CORE_CLK_REG_FACTOR_M_OFFSET   0
 
#define GPU_CORE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f
 
#define GPU_CORE_CLK_REG_FACTOR_M_NOT_MASK   0x000
 
#define GPU_CORE_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES   0x001
 
#define GPU_CORE_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES   0x010
 
#define GPU_GATING_REG   0x0000067c
 
#define GPU_GATING_REG_GPU_RST_OFFSET   16
 
#define GPU_GATING_REG_GPU_RST_CLEAR_MASK   0x00010000
 
#define GPU_GATING_REG_GPU_RST_ASSERT   0x0
 
#define GPU_GATING_REG_GPU_RST_DE_ASSERT   0x1
 
#define GPU_GATING_REG_GPU_GATING_OFFSET   0
 
#define GPU_GATING_REG_GPU_GATING_CLEAR_MASK   0x00000001
 
#define GPU_GATING_REG_GPU_GATING_MASK   0x0
 
#define GPU_GATING_REG_GPU_GATING_PASS   0x1
 
#define CE_CLK_REG   0x00000680
 
#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31
 
#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CE_CLK_REG_CLK_SRC_SEL_HOSC   0b0
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b1
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b10
 
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b11
 
#define CE_CLK_REG_FACTOR_M_OFFSET   0
 
#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CE_BGR_REG   0x0000068c
 
#define CE_BGR_REG_CE_SYS_RST_OFFSET   17
 
#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   0x00020000
 
#define CE_BGR_REG_CE_SYS_RST_ASSERT   0x0
 
#define CE_BGR_REG_CE_SYS_RST_DE_ASSERT   0x1
 
#define CE_BGR_REG_CE_RST_OFFSET   16
 
#define CE_BGR_REG_CE_RST_CLEAR_MASK   0x00010000
 
#define CE_BGR_REG_CE_RST_ASSERT   0x0
 
#define CE_BGR_REG_CE_RST_DE_ASSERT   0x1
 
#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1
 
#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   0x00000002
 
#define CE_BGR_REG_CE_SYS_GATING_MASK   0x0
 
#define CE_BGR_REG_CE_SYS_GATING_PASS   0x1
 
#define CE_BGR_REG_CE_GATING_OFFSET   0
 
#define CE_BGR_REG_CE_GATING_CLEAR_MASK   0x00000001
 
#define CE_BGR_REG_CE_GATING_MASK   0x0
 
#define CE_BGR_REG_CE_GATING_PASS   0x1
 
#define VE_CLK_REG   0x00000690
 
#define VE_CLK_REG_VE_CLK_GATING_OFFSET   31
 
#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON   0x1
 
#define VE_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VE_CLK_REG_CLK_SRC_SEL_VEPLL   0x000
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x001
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x010
 
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x011
 
#define VE_CLK_REG_FACTOR_M_OFFSET   0
 
#define VE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VE_BGR_REG   0x0000069c
 
#define VE_BGR_REG_VE_RST_OFFSET   16
 
#define VE_BGR_REG_VE_RST_CLEAR_MASK   0x00010000
 
#define VE_BGR_REG_VE_RST_ASSERT   0x0
 
#define VE_BGR_REG_VE_RST_DE_ASSERT   0x1
 
#define VE_BGR_REG_VE_GATING_OFFSET   0
 
#define VE_BGR_REG_VE_GATING_CLEAR_MASK   0x00000001
 
#define VE_BGR_REG_VE_GATING_MASK   0x0
 
#define VE_BGR_REG_VE_GATING_PASS   0x1
 
#define NPU_CLK_REG   0x000006e0
 
#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   0x80000000
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0x1
 
#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x000
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x001
 
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x010
 
#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X   0x011
 
#define NPU_CLK_REG_FACTOR_M_OFFSET   0
 
#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DMA_BGR_REG   0x0000070c
 
#define DMA_BGR_REG_DMA_RST_OFFSET   16
 
#define DMA_BGR_REG_DMA_RST_CLEAR_MASK   0x00010000
 
#define DMA_BGR_REG_DMA_RST_ASSERT   0x0
 
#define DMA_BGR_REG_DMA_RST_DE_ASSERT   0x1
 
#define DMA_BGR_REG_DMA_GATING_OFFSET   0
 
#define DMA_BGR_REG_DMA_GATING_CLEAR_MASK   0x00000001
 
#define DMA_BGR_REG_DMA_GATING_MASK   0x0
 
#define DMA_BGR_REG_DMA_GATING_PASS   0x1
 
#define MSGBOX_BGR_REG   0x0000071c
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET   17
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK   0x00020000
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT   0x0
 
#define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT   0x1
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET   16
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK   0x00010000
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT   0x0
 
#define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT   0x1
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET   1
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK   0x00000002
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK   0x0
 
#define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS   0x1
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET   0
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   0x00000001
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK   0x0
 
#define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS   0x1
 
#define SPINLOCK_BGR_REG   0x0000072c
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   0x00010000
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0x0
 
#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0x1
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   0x00000001
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0x0
 
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0x1
 
#define TIMER0_CLK_REG   0x00000730
 
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET   31
 
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE   0x0
 
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE   0x1
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER0_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER0_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER0_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER0_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER0_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER0_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER0_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER0_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER0_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER1_CLK_REG   0x00000734
 
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET   31
 
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE   0x0
 
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE   0x1
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER1_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER1_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER1_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER1_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER1_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER1_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER1_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER1_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER1_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER2_CLK_REG   0x00000738
 
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET   31
 
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE   0x0
 
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE   0x1
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC   0x00
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER2_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER2_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER2_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER2_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER2_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER2_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER2_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER2_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER2_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER3_CLK_REG   0x0000073c
 
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET   31
 
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE   0x0
 
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE   0x1
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER3_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER3_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER3_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER3_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER3_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER3_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER3_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER3_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER3_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER4_CLK_REG   0x00000740
 
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET   31
 
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE   0x0
 
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE   0x1
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER4_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER4_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER4_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER4_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER4_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER4_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER4_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER4_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER4_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER5_CLK_REG   0x00000744
 
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET   31
 
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE   0x0
 
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE   0x1
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K   0x010
 
#define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011
 
#define TIMER5_CLK_REG_FACTOR_M_OFFSET   0
 
#define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007
 
#define TIMER5_CLK_REG_FACTOR_M__1   0x000
 
#define TIMER5_CLK_REG_FACTOR_M__2   0x001
 
#define TIMER5_CLK_REG_FACTOR_M__4   0x010
 
#define TIMER5_CLK_REG_FACTOR_M__8   0x011
 
#define TIMER5_CLK_REG_FACTOR_M__16   0x100
 
#define TIMER5_CLK_REG_FACTOR_M__32   0x101
 
#define TIMER5_CLK_REG_FACTOR_M__64   0x110
 
#define TIMER5_CLK_REG_FACTOR_M__128   0x111
 
#define TIMER_BGR_REG   0x0000074c
 
#define TIMER_BGR_REG_TIMER_RST_OFFSET   16
 
#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK   0x00010000
 
#define TIMER_BGR_REG_TIMER_RST_ASSERT   0x0
 
#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT   0x1
 
#define TIMER_BGR_REG_TIMER_GATING_OFFSET   0
 
#define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK   0x00000001
 
#define TIMER_BGR_REG_TIMER_GATING_MASK   0x0
 
#define TIMER_BGR_REG_TIMER_GATING_PASS   0x1
 
#define AVS_CLK_REG   0x00000750
 
#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   0x80000000
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DBGSYS_BGR_REG   0x0000078c
 
#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16
 
#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   0x00010000
 
#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0x0
 
#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0x1
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   0x00000001
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0x0
 
#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0x1
 
#define PWM_BGR_REG   0x000007ac
 
#define PWM_BGR_REG_PWM_RST_OFFSET   16
 
#define PWM_BGR_REG_PWM_RST_CLEAR_MASK   0x00010000
 
#define PWM_BGR_REG_PWM_RST_ASSERT   0x0
 
#define PWM_BGR_REG_PWM_RST_DE_ASSERT   0x1
 
#define PWM_BGR_REG_PWM_GATING_OFFSET   0
 
#define PWM_BGR_REG_PWM_GATING_CLEAR_MASK   0x00000001
 
#define PWM_BGR_REG_PWM_GATING_MASK   0x0
 
#define PWM_BGR_REG_PWM_GATING_PASS   0x1
 
#define IOMMU_BGR_REG   0x000007bc
 
#define IOMMU_BGR_REG_IOMMU_GATING_OFFSET   0
 
#define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK   0x00000001
 
#define IOMMU_BGR_REG_IOMMU_GATING_MASK   0x0
 
#define IOMMU_BGR_REG_IOMMU_GATING_PASS   0x1
 
#define DRAM_CLK_REG   0x00000800
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET   31
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DRAM_CLK_REG_DRAM_UPD_OFFSET   27
 
#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK   0x08000000
 
#define DRAM_CLK_REG_DRAM_UPD_INVALID   0x0
 
#define DRAM_CLK_REG_DRAM_UPD_VALID   0x1
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET   24
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK   0x07000000
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL   0x000
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M   0x001
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M   0x010
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_400M   0x011
 
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_150M   0x100
 
#define DRAM_CLK_REG_DRAM_DIV1_OFFSET   0
 
#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK   0x0000001f
 
#define MBUS_MAT_CLK_GATING_REG   0x00000804
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET   22
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   21
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00200000
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   20
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET   19
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET   18
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET   17
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET   16
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE   0x0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE   0x1
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET   9
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK   0x00000200
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET   8
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK   0x00000100
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_OFFSET   6
 
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_CLEAR_MASK   0x00000040
 
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET   5
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK   0x00000020
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET   2
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK   0x00000004
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET   1
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK   0x00000002
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS   0x1
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET   0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK   0x00000001
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK   0x0
 
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS   0x1
 
#define DRAM_BGR_REG   0x0000080c
 
#define DRAM_BGR_REG_DRAM_RST_OFFSET   16
 
#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK   0x00010000
 
#define DRAM_BGR_REG_DRAM_RST_ASSERT   0x0
 
#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT   0x1
 
#define DRAM_BGR_REG_DRAM_GATING_OFFSET   0
 
#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK   0x00000001
 
#define DRAM_BGR_REG_DRAM_GATING_MASK   0x0
 
#define DRAM_BGR_REG_DRAM_GATING_PASS   0x1
 
#define NAND0_CLK0_CLK_REG   0x00000810
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET   31
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011
 
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100
 
#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET   0
 
#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define NAND0_CLK1_CLK_REG   0x00000814
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET   31
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011
 
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100
 
#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET   0
 
#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define NAND_BGR_REG   0x0000082c
 
#define NAND_BGR_REG_NAND0_RST_OFFSET   16
 
#define NAND_BGR_REG_NAND0_RST_CLEAR_MASK   0x00010000
 
#define NAND_BGR_REG_NAND0_RST_ASSERT   0x0
 
#define NAND_BGR_REG_NAND0_RST_DE_ASSERT   0x1
 
#define NAND_BGR_REG_NAND0_GATING_OFFSET   0
 
#define NAND_BGR_REG_NAND0_GATING_CLEAR_MASK   0x00000001
 
#define NAND_BGR_REG_NAND0_GATING_MASK   0x0
 
#define NAND_BGR_REG_NAND0_GATING_PASS   0x1
 
#define SMHC0_CLK_REG   0x00000830
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011
 
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100
 
#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC1_CLK_REG   0x00000834
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011
 
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100
 
#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC2_CLK_REG   0x00000838
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x001
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0x011
 
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0x100
 
#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8
 
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SMHC_BGR_REG   0x0000084c
 
#define SMHC_BGR_REG_SMHC2_RST_OFFSET   18
 
#define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK   0x00040000
 
#define SMHC_BGR_REG_SMHC2_RST_ASSERT   0x0
 
#define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT   0x1
 
#define SMHC_BGR_REG_SMHC1_RST_OFFSET   17
 
#define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK   0x00020000
 
#define SMHC_BGR_REG_SMHC1_RST_ASSERT   0x0
 
#define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT   0x1
 
#define SMHC_BGR_REG_SMHC0_RST_OFFSET   16
 
#define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK   0x00010000
 
#define SMHC_BGR_REG_SMHC0_RST_ASSERT   0x0
 
#define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT   0x1
 
#define SMHC_BGR_REG_SMHC2_GATING_OFFSET   2
 
#define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK   0x00000004
 
#define SMHC_BGR_REG_SMHC2_GATING_MASK   0x0
 
#define SMHC_BGR_REG_SMHC2_GATING_PASS   0x1
 
#define SMHC_BGR_REG_SMHC1_GATING_OFFSET   1
 
#define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK   0x00000002
 
#define SMHC_BGR_REG_SMHC1_GATING_MASK   0x0
 
#define SMHC_BGR_REG_SMHC1_GATING_PASS   0x1
 
#define SMHC_BGR_REG_SMHC0_GATING_OFFSET   0
 
#define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK   0x00000001
 
#define SMHC_BGR_REG_SMHC0_GATING_MASK   0x0
 
#define SMHC_BGR_REG_SMHC0_GATING_PASS   0x1
 
#define SYSDAP_BGR_REG   0x0000088c
 
#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET   16
 
#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK   0x00010000
 
#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT   0x0
 
#define SYSDAP_BGR_REG_SYSDAP_RST_DE_ASSERT   0x1
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET   0
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK   0x00000001
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK   0x0
 
#define SYSDAP_BGR_REG_SYSDAP_GATING_PASS   0x1
 
#define UART_BGR_REG   0x0000090c
 
#define UART_BGR_REG_UART7_RST_OFFSET   23
 
#define UART_BGR_REG_UART7_RST_CLEAR_MASK   0x00800000
 
#define UART_BGR_REG_UART7_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART7_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART6_RST_OFFSET   22
 
#define UART_BGR_REG_UART6_RST_CLEAR_MASK   0x00400000
 
#define UART_BGR_REG_UART6_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART6_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART5_RST_OFFSET   21
 
#define UART_BGR_REG_UART5_RST_CLEAR_MASK   0x00200000
 
#define UART_BGR_REG_UART5_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART5_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART4_RST_OFFSET   20
 
#define UART_BGR_REG_UART4_RST_CLEAR_MASK   0x00100000
 
#define UART_BGR_REG_UART4_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART4_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART3_RST_OFFSET   19
 
#define UART_BGR_REG_UART3_RST_CLEAR_MASK   0x00080000
 
#define UART_BGR_REG_UART3_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART3_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART2_RST_OFFSET   18
 
#define UART_BGR_REG_UART2_RST_CLEAR_MASK   0x00040000
 
#define UART_BGR_REG_UART2_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART2_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART1_RST_OFFSET   17
 
#define UART_BGR_REG_UART1_RST_CLEAR_MASK   0x00020000
 
#define UART_BGR_REG_UART1_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART1_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART0_RST_OFFSET   16
 
#define UART_BGR_REG_UART0_RST_CLEAR_MASK   0x00010000
 
#define UART_BGR_REG_UART0_RST_ASSERT   0x0
 
#define UART_BGR_REG_UART0_RST_DE_ASSERT   0x1
 
#define UART_BGR_REG_UART7_GATING_OFFSET   7
 
#define UART_BGR_REG_UART7_GATING_CLEAR_MASK   0x00000080
 
#define UART_BGR_REG_UART7_GATING_MASK   0x0
 
#define UART_BGR_REG_UART7_GATING_PASS   0x1
 
#define UART_BGR_REG_UART6_GATING_OFFSET   6
 
#define UART_BGR_REG_UART6_GATING_CLEAR_MASK   0x00000040
 
#define UART_BGR_REG_UART6_GATING_MASK   0x0
 
#define UART_BGR_REG_UART6_GATING_PASS   0x1
 
#define UART_BGR_REG_UART5_GATING_OFFSET   5
 
#define UART_BGR_REG_UART5_GATING_CLEAR_MASK   0x00000020
 
#define UART_BGR_REG_UART5_GATING_MASK   0x0
 
#define UART_BGR_REG_UART5_GATING_PASS   0x1
 
#define UART_BGR_REG_UART4_GATING_OFFSET   4
 
#define UART_BGR_REG_UART4_GATING_CLEAR_MASK   0x00000010
 
#define UART_BGR_REG_UART4_GATING_MASK   0x0
 
#define UART_BGR_REG_UART4_GATING_PASS   0x1
 
#define UART_BGR_REG_UART3_GATING_OFFSET   3
 
#define UART_BGR_REG_UART3_GATING_CLEAR_MASK   0x00000008
 
#define UART_BGR_REG_UART3_GATING_MASK   0x0
 
#define UART_BGR_REG_UART3_GATING_PASS   0x1
 
#define UART_BGR_REG_UART2_GATING_OFFSET   2
 
#define UART_BGR_REG_UART2_GATING_CLEAR_MASK   0x00000004
 
#define UART_BGR_REG_UART2_GATING_MASK   0x0
 
#define UART_BGR_REG_UART2_GATING_PASS   0x1
 
#define UART_BGR_REG_UART1_GATING_OFFSET   1
 
#define UART_BGR_REG_UART1_GATING_CLEAR_MASK   0x00000002
 
#define UART_BGR_REG_UART1_GATING_MASK   0x0
 
#define UART_BGR_REG_UART1_GATING_PASS   0x1
 
#define UART_BGR_REG_UART0_GATING_OFFSET   0
 
#define UART_BGR_REG_UART0_GATING_CLEAR_MASK   0x00000001
 
#define UART_BGR_REG_UART0_GATING_MASK   0x0
 
#define UART_BGR_REG_UART0_GATING_PASS   0x1
 
#define TWI_BGR_REG   0x0000091c
 
#define TWI_BGR_REG_TWI5_RST_OFFSET   21
 
#define TWI_BGR_REG_TWI5_RST_CLEAR_MASK   0x00200000
 
#define TWI_BGR_REG_TWI5_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI5_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI4_RST_OFFSET   20
 
#define TWI_BGR_REG_TWI4_RST_CLEAR_MASK   0x00100000
 
#define TWI_BGR_REG_TWI4_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI4_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI3_RST_OFFSET   19
 
#define TWI_BGR_REG_TWI3_RST_CLEAR_MASK   0x00080000
 
#define TWI_BGR_REG_TWI3_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI3_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI2_RST_OFFSET   18
 
#define TWI_BGR_REG_TWI2_RST_CLEAR_MASK   0x00040000
 
#define TWI_BGR_REG_TWI2_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI2_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI1_RST_OFFSET   17
 
#define TWI_BGR_REG_TWI1_RST_CLEAR_MASK   0x00020000
 
#define TWI_BGR_REG_TWI1_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI1_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI0_RST_OFFSET   16
 
#define TWI_BGR_REG_TWI0_RST_CLEAR_MASK   0x00010000
 
#define TWI_BGR_REG_TWI0_RST_ASSERT   0x0
 
#define TWI_BGR_REG_TWI0_RST_DE_ASSERT   0x1
 
#define TWI_BGR_REG_TWI5_GATING_OFFSET   5
 
#define TWI_BGR_REG_TWI5_GATING_CLEAR_MASK   0x00000020
 
#define TWI_BGR_REG_TWI5_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI5_GATING_PASS   0x1
 
#define TWI_BGR_REG_TWI4_GATING_OFFSET   4
 
#define TWI_BGR_REG_TWI4_GATING_CLEAR_MASK   0x00000010
 
#define TWI_BGR_REG_TWI4_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI4_GATING_PASS   0x1
 
#define TWI_BGR_REG_TWI3_GATING_OFFSET   3
 
#define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK   0x00000008
 
#define TWI_BGR_REG_TWI3_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI3_GATING_PASS   0x1
 
#define TWI_BGR_REG_TWI2_GATING_OFFSET   2
 
#define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK   0x00000004
 
#define TWI_BGR_REG_TWI2_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI2_GATING_PASS   0x1
 
#define TWI_BGR_REG_TWI1_GATING_OFFSET   1
 
#define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK   0x00000002
 
#define TWI_BGR_REG_TWI1_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI1_GATING_PASS   0x1
 
#define TWI_BGR_REG_TWI0_GATING_OFFSET   0
 
#define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK   0x00000001
 
#define TWI_BGR_REG_TWI0_GATING_MASK   0x0
 
#define TWI_BGR_REG_TWI0_GATING_PASS   0x1
 
#define CAN_BGR_REG   0x0000092c
 
#define CAN_BGR_REG_CAN0_RST_OFFSET   16
 
#define CAN_BGR_REG_CAN0_RST_CLEAR_MASK   0x00010000
 
#define CAN_BGR_REG_CAN0_RST_ASSERT   0x0
 
#define CAN_BGR_REG_CAN0_RST_DE_ASSERT   0x1
 
#define CAN_BGR_REG_CAN0_GATING_OFFSET   0
 
#define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK   0x00000001
 
#define CAN_BGR_REG_CAN0_GATING_MASK   0x0
 
#define CAN_BGR_REG_CAN0_GATING_PASS   0x1
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011
 
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100
 
#define SPI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI1_CLK_REG   0x00000944
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011
 
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100
 
#define SPI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI2_CLK_REG   0x00000948
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011
 
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100
 
#define SPI2_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPIF_CLK_REG   0x00000950
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0x1
 
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x011
 
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100
 
#define SPIF_CLK_REG_FACTOR_N_OFFSET   8
 
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define SPIF_CLK_REG_FACTOR_M_OFFSET   0
 
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define SPI_BGR_REG   0x0000096c
 
#define SPI_BGR_REG_SPIF_RST_OFFSET   19
 
#define SPI_BGR_REG_SPIF_RST_CLEAR_MASK   0x00080000
 
#define SPI_BGR_REG_SPIF_RST_ASSERT   0x0
 
#define SPI_BGR_REG_SPIF_RST_DE_ASSERT   0x1
 
#define SPI_BGR_REG_SPI2_RST_OFFSET   18
 
#define SPI_BGR_REG_SPI2_RST_CLEAR_MASK   0x00040000
 
#define SPI_BGR_REG_SPI2_RST_ASSERT   0x0
 
#define SPI_BGR_REG_SPI2_RST_DE_ASSERT   0x1
 
#define SPI_BGR_REG_SPI1_RST_OFFSET   17
 
#define SPI_BGR_REG_SPI1_RST_CLEAR_MASK   0x00020000
 
#define SPI_BGR_REG_SPI1_RST_ASSERT   0x0
 
#define SPI_BGR_REG_SPI1_RST_DE_ASSERT   0x1
 
#define SPI_BGR_REG_SPI0_RST_OFFSET   16
 
#define SPI_BGR_REG_SPI0_RST_CLEAR_MASK   0x00010000
 
#define SPI_BGR_REG_SPI0_RST_ASSERT   0x0
 
#define SPI_BGR_REG_SPI0_RST_DE_ASSERT   0x1
 
#define SPI_BGR_REG_SPIF_GATING_OFFSET   3
 
#define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK   0x00000008
 
#define SPI_BGR_REG_SPIF_GATING_MASK   0x0
 
#define SPI_BGR_REG_SPIF_GATING_PASS   0x1
 
#define SPI_BGR_REG_SPI2_GATING_OFFSET   2
 
#define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK   0x00000004
 
#define SPI_BGR_REG_SPI2_GATING_MASK   0x0
 
#define SPI_BGR_REG_SPI2_GATING_PASS   0x1
 
#define SPI_BGR_REG_SPI1_GATING_OFFSET   1
 
#define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK   0x00000002
 
#define SPI_BGR_REG_SPI1_GATING_MASK   0x0
 
#define SPI_BGR_REG_SPI1_GATING_PASS   0x1
 
#define SPI_BGR_REG_SPI0_GATING_OFFSET   0
 
#define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK   0x00000001
 
#define SPI_BGR_REG_SPI0_GATING_MASK   0x0
 
#define SPI_BGR_REG_SPI0_GATING_PASS   0x1
 
#define GMAC0_25M_CLK_REG   0x00000970
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_OFFSET   31
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_ON   0x1
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_OFFSET   30
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0x0
 
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_ON   0x1
 
#define GMAC1_25M_CLK_REG   0x00000974
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_OFFSET   31
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_ON   0x1
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_OFFSET   30
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0x0
 
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_ON   0x1
 
#define GMAC_BGR_REG   0x0000097c
 
#define GMAC_BGR_REG_GMAC1_RST_OFFSET   17
 
#define GMAC_BGR_REG_GMAC1_RST_CLEAR_MASK   0x00020000
 
#define GMAC_BGR_REG_GMAC1_RST_ASSERT   0x0
 
#define GMAC_BGR_REG_GMAC1_RST_DE_ASSERT   0x1
 
#define GMAC_BGR_REG_GMAC0_RST_OFFSET   16
 
#define GMAC_BGR_REG_GMAC0_RST_CLEAR_MASK   0x00010000
 
#define GMAC_BGR_REG_GMAC0_RST_ASSERT   0x0
 
#define GMAC_BGR_REG_GMAC0_RST_DE_ASSERT   0x1
 
#define GMAC_BGR_REG_GMAC1_GATING_OFFSET   1
 
#define GMAC_BGR_REG_GMAC1_GATING_CLEAR_MASK   0x00000002
 
#define GMAC_BGR_REG_GMAC1_GATING_MASKS   0x0
 
#define GMAC_BGR_REG_GMAC1_GATING_PASS   0x1
 
#define GMAC_BGR_REG_GMAC0_GATING_OFFSET   0
 
#define GMAC_BGR_REG_GMAC0_GATING_CLEAR_MASK   0x00000001
 
#define GMAC_BGR_REG_GMAC0_GATING_MASK   0x0
 
#define GMAC_BGR_REG_GMAC0_GATING_PASS   0x1
 
#define IRRX_CLK_REG   0x00000990
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET   31
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON   0x1
 
#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K   0x0
 
#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC   0x1
 
#define IRRX_CLK_REG_FACTOR_M_OFFSET   0
 
#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define IRRX_BGR_REG   0x0000099c
 
#define IRRX_BGR_REG_IRRX_RST_OFFSET   16
 
#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK   0x00010000
 
#define IRRX_BGR_REG_IRRX_RST_ASSERT   0x0
 
#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT   0x1
 
#define IRRX_BGR_REG_IRRX_GATING_OFFSET   0
 
#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK   0x00000001
 
#define IRRX_BGR_REG_IRRX_GATING_MASK   0x0
 
#define IRRX_BGR_REG_IRRX_GATING_PASS   0x1
 
#define IRTX_CLK_REG   0x000009c0
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET   31
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON   0x1
 
#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC   0x0
 
#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0x1
 
#define IRTX_CLK_REG_FACTOR_M_OFFSET   0
 
#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define IRTX_BGR_REG   0x000009cc
 
#define IRTX_BGR_REG_IRTX_RST_OFFSET   16
 
#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK   0x00010000
 
#define IRTX_BGR_REG_IRTX_RST_ASSERT   0x0
 
#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT   0x1
 
#define IRTX_BGR_REG_IRTX_GATING_OFFSET   0
 
#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK   0x00000001
 
#define IRTX_BGR_REG_IRTX_GATING_MASK   0x0
 
#define IRTX_BGR_REG_IRTX_GATING_PASS   0x1
 
#define GPADC_24M_CLK_REG   0x000009e0
 
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_OFFSET   31
 
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLEAR_MASK   0x80000000
 
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_ON   0x1
 
#define GPADC_24M_CLK_REG_FACTOR_M_OFFSET   0
 
#define GPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define GPADC_BGR_REG   0x000009ec
 
#define GPADC_BGR_REG_GPADC_RST_OFFSET   16
 
#define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK   0x00010000
 
#define GPADC_BGR_REG_GPADC_RST_ASSERT   0x0
 
#define GPADC_BGR_REG_GPADC_RST_DE_ASSERT   0x1
 
#define GPADC_BGR_REG_GPADC_GATING_OFFSET   0
 
#define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK   0x00000001
 
#define GPADC_BGR_REG_GPADC_GATING_MASK   0x0
 
#define GPADC_BGR_REG_GPADC_GATING_PASS   0x1
 
#define THS_BGR_REG   0x000009fc
 
#define THS_BGR_REG_THS_RST_OFFSET   16
 
#define THS_BGR_REG_THS_RST_CLEAR_MASK   0x00010000
 
#define THS_BGR_REG_THS_RST_ASSERT   0x0
 
#define THS_BGR_REG_THS_RST_DE_ASSERT   0x1
 
#define THS_BGR_REG_THS_GATING_OFFSET   0
 
#define THS_BGR_REG_THS_GATING_CLEAR_MASK   0x00000001
 
#define THS_BGR_REG_THS_GATING_MASK   0x0
 
#define THS_BGR_REG_THS_GATING_PASS   0x1
 
#define USB0_CLK_REG   0x00000a70
 
#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31
 
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0x0
 
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0x1
 
#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET   30
 
#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK   0x40000000
 
#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT   0x0
 
#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT   0x1
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0x00
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0x01
 
#define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K   0x10
 
#define USB1_CLK_REG   0x00000a74
 
#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31
 
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   0x80000000
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0x0
 
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0x1
 
#define USB1_CLK_REG_USBPHY1_RSTN_OFFSET   30
 
#define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK   0x40000000
 
#define USB1_CLK_REG_USBPHY1_RSTN_ASSERT   0x0
 
#define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT   0x1
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   0x03000000
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0x00
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0x01
 
#define USB1_CLK_REG_USB1_CLK12M_SEL_RTC_32K   0x10
 
#define USB2_REF_CLK_REG   0x00000a78
 
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET   31
 
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON   0x1
 
#define USB2_SUSPEND_CLK_REG   0x00000a7c
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   0x80000000
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0x1
 
#define USB_BGR_REG   0x00000a8c
 
#define USB_BGR_REG_USB2_PHY_RST_OFFSET   26
 
#define USB_BGR_REG_USB2_PHY_RST_CLEAR_MASK   0x04000000
 
#define USB_BGR_REG_USB2_PHY_RST_ASSERT   0x0
 
#define USB_BGR_REG_USB2_PHY_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USB2_RST_OFFSET   25
 
#define USB_BGR_REG_USB2_RST_CLEAR_MASK   0x02000000
 
#define USB_BGR_REG_USB2_RST_ASSERT   0x0
 
#define USB_BGR_REG_USB2_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USBOTG0_RST_OFFSET   24
 
#define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK   0x01000000
 
#define USB_BGR_REG_USBOTG0_RST_ASSERT   0x0
 
#define USB_BGR_REG_USBOTG0_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USBEHCI1_RST_OFFSET   21
 
#define USB_BGR_REG_USBEHCI1_RST_CLEAR_MASK   0x00200000
 
#define USB_BGR_REG_USBEHCI1_RST_ASSERT   0x0
 
#define USB_BGR_REG_USBEHCI1_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USBEHCI0_RST_OFFSET   20
 
#define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK   0x00100000
 
#define USB_BGR_REG_USBEHCI0_RST_ASSERT   0x0
 
#define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USBOHCI1_RST_OFFSET   17
 
#define USB_BGR_REG_USBOHCI1_RST_CLEAR_MASK   0x00020000
 
#define USB_BGR_REG_USBOHCI1_RST_ASSERT   0x0
 
#define USB_BGR_REG_USBOHCI1_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USBOHCI0_RST_OFFSET   16
 
#define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK   0x00010000
 
#define USB_BGR_REG_USBOHCI0_RST_ASSERT   0x0
 
#define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT   0x1
 
#define USB_BGR_REG_USB2_GATING_OFFSET   9
 
#define USB_BGR_REG_USB2_GATING_CLEAR_MASK   0x00000200
 
#define USB_BGR_REG_USB2_GATING_MASK   0x0
 
#define USB_BGR_REG_USB2_GATING_PASS   0x1
 
#define USB_BGR_REG_USBOTG0_GATING_OFFSET   8
 
#define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK   0x00000100
 
#define USB_BGR_REG_USBOTG0_GATING_MASK   0x0
 
#define USB_BGR_REG_USBOTG0_GATING_PASS   0x1
 
#define USB_BGR_REG_USBEHCI1_GATING_OFFSET   5
 
#define USB_BGR_REG_USBEHCI1_GATING_CLEAR_MASK   0x00000020
 
#define USB_BGR_REG_USBEHCI1_GATING_MASK   0x0
 
#define USB_BGR_REG_USBEHCI1_GATING_PASS   0x1
 
#define USB_BGR_REG_USBEHCI0_GATING_OFFSET   4
 
#define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK   0x00000010
 
#define USB_BGR_REG_USBEHCI0_GATING_MASK   0x0
 
#define USB_BGR_REG_USBEHCI0_GATING_PASS   0x1
 
#define USB_BGR_REG_USBOHCI1_GATING_OFFSET   1
 
#define USB_BGR_REG_USBOHCI1_GATING_CLEAR_MASK   0x00000002
 
#define USB_BGR_REG_USBOHCI1_GATING_MASK   0x0
 
#define USB_BGR_REG_USBOHCI1_GATING_PASS   0x1
 
#define USB_BGR_REG_USBOHCI0_GATING_OFFSET   0
 
#define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK   0x00000001
 
#define USB_BGR_REG_USBOHCI0_GATING_MASK   0x0
 
#define USB_BGR_REG_USBOHCI0_GATING_PASS   0x1
 
#define LRADC_BGR_REG   0x00000a9c
 
#define LRADC_BGR_REG_LRADC_RST_OFFSET   16
 
#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK   0x00010000
 
#define LRADC_BGR_REG_LRADC_RST_ASSERT   0x0
 
#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT   0x1
 
#define LRADC_BGR_REG_LRADC_GATING_OFFSET   0
 
#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK   0x00000001
 
#define LRADC_BGR_REG_LRADC_GATING_MASK   0x0
 
#define LRADC_BGR_REG_LRADC_GATING_PASS   0x1
 
#define PCIE_AUX_CLK_REG   0x00000aa0
 
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET   31
 
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON   0x1
 
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC   0x0
 
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K   0x1
 
#define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET   0
 
#define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define PCIE_REF_CLK_REG   0x00000aa4
 
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_OFFSET   31
 
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLEAR_MASK   0x80000000
 
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_ON   0x1
 
#define PCIE_BGR_REG   0x00000aac
 
#define PCIE_BGR_REG_PCIE_PE_RST_OFFSET   18
 
#define PCIE_BGR_REG_PCIE_PE_RST_CLEAR_MASK   0x00040000
 
#define PCIE_BGR_REG_PCIE_PE_RST_ASSERT   0x0
 
#define PCIE_BGR_REG_PCIE_PE_RST_DE_ASSERT   0x1
 
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_OFFSET   17
 
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_CLEAR_MASK   0x00020000
 
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_ASSERT   0x0
 
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_DE_ASSERT   0x1
 
#define PCIE_BGR_REG_PCIE_RST_OFFSET   16
 
#define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK   0x00010000
 
#define PCIE_BGR_REG_PCIE_RST_ASSERT   0x0
 
#define PCIE_BGR_REG_PCIE_RST_DE_ASSERT   0x1
 
#define PCIE_BGR_REG_PCIE_GATING_OFFSET   0
 
#define PCIE_BGR_REG_PCIE_GATING_CLEAR_MASK   0x00000001
 
#define PCIE_BGR_REG_PCIE_GATING_MASK   0x0
 
#define PCIE_BGR_REG_PCIE_GATING_PASS   0x1
 
#define DPSS_TOP0_BGR_REG   0x00000abc
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET   16
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK   0x00010000
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT   0x0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT   0x1
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET   0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK   0x00000001
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK   0x0
 
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS   0x1
 
#define DPSS_TOP1_BGR_REG   0x00000acc
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET   16
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK   0x00010000
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT   0x0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT   0x1
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET   0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK   0x00000001
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK   0x0
 
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS   0x1
 
#define HDMI_24M_CLK_REG   0x00000b04
 
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_OFFSET   31
 
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLEAR_MASK   0x80000000
 
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_ON   0x1
 
#define HDMI_CEC_CLK_REG   0x00000b10
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET   31
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON   0x1
 
#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET   30
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK   0x40000000
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF   0x0
 
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON   0x1
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K   0x0
 
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K__PLL_PERI_2X__36621___32_768KHZ   0x1
 
#define HDMI_BGR_REG   0x00000b1c
 
#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET   17
 
#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK   0x00020000
 
#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT   0x0
 
#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT   0x1
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET   16
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK   0x00010000
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT   0x0
 
#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT   0x1
 
#define HDMI_BGR_REG_HDMI_GATING_OFFSET   0
 
#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK   0x00000001
 
#define HDMI_BGR_REG_HDMI_GATING_MASK   0x0
 
#define HDMI_BGR_REG_HDMI_GATING_PASS   0x1
 
#define DSI0_CLK_REG   0x00000b24
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET   31
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DSI0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001
 
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M   0x010
 
#define DSI0_CLK_REG_FACTOR_M_OFFSET   0
 
#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DSI1_CLK_REG   0x00000b28
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET   31
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DSI1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001
 
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M   0x010
 
#define DSI1_CLK_REG_FACTOR_M_OFFSET   0
 
#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define DSI_BGR_REG   0x00000b4c
 
#define DSI_BGR_REG_DSI1_RST_OFFSET   17
 
#define DSI_BGR_REG_DSI1_RST_CLEAR_MASK   0x00020000
 
#define DSI_BGR_REG_DSI1_RST_ASSERT   0x0
 
#define DSI_BGR_REG_DSI1_RST_DE_ASSERT   0x1
 
#define DSI_BGR_REG_DSI0_RST_OFFSET   16
 
#define DSI_BGR_REG_DSI0_RST_CLEAR_MASK   0x00010000
 
#define DSI_BGR_REG_DSI0_RST_ASSERT   0x0
 
#define DSI_BGR_REG_DSI0_RST_DE_ASSERT   0x1
 
#define DSI_BGR_REG_DSI1_GATING_OFFSET   1
 
#define DSI_BGR_REG_DSI1_GATING_CLEAR_MASK   0x00000002
 
#define DSI_BGR_REG_DSI1_GATING_MASK   0x0
 
#define DSI_BGR_REG_DSI1_GATING_PASS   0x1
 
#define DSI_BGR_REG_DSI0_GATING_OFFSET   0
 
#define DSI_BGR_REG_DSI0_GATING_CLEAR_MASK   0x00000001
 
#define DSI_BGR_REG_DSI0_GATING_MASK   0x0
 
#define DSI_BGR_REG_DSI0_GATING_PASS   0x1
 
#define VO0_TCONLCD0_CLK_REG   0x00000b60
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET   31
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VO0_TCONLCD1_CLK_REG   0x00000b64
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET   31
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define VO1_TCONLCD0_CLK_REG   0x00000b68
 
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_OFFSET   31
 
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define VO1_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0
 
#define VO1_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define COMBPHY0_CLK_REG   0x00000b6c
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET   31
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET   0
 
#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define COMBPHY1_CLK_REG   0x00000b70
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET   31
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET   0
 
#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define TCONLCD_BGR_REG   0x00000b7c
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_OFFSET   18
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_CLEAR_MASK   0x00040000
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_ASSERT   0x0
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_DE_ASSERT   0x1
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_OFFSET   17
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK   0x00020000
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_ASSERT   0x0
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT   0x1
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_OFFSET   16
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK   0x00010000
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_ASSERT   0x0
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT   0x1
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_OFFSET   2
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_CLEAR_MASK   0x00000004
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_MASK   0x0
 
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_PASS   0x1
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_OFFSET   1
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK   0x00000002
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_MASK   0x0
 
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_PASS   0x1
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_OFFSET   0
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK   0x00000001
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_MASK   0x0
 
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_PASS   0x1
 
#define TCONTV_CLK_REG   0x00000b80
 
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_OFFSET   31
 
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLEAR_MASK   0x80000000
 
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_ON   0x1
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define TCONTV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100
 
#define TCONTV_CLK_REG_FACTOR_M_OFFSET   0
 
#define TCONTV_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define TCONTV_BGR_REG   0x00000b9c
 
#define TCONTV_BGR_REG_TCONTV_RST_OFFSET   16
 
#define TCONTV_BGR_REG_TCONTV_RST_CLEAR_MASK   0x00010000
 
#define TCONTV_BGR_REG_TCONTV_RST_ASSERT   0x0
 
#define TCONTV_BGR_REG_TCONTV_RST_DE_ASSERT   0x1
 
#define TCONTV_BGR_REG_TCONTV_GATING_OFFSET   0
 
#define TCONTV_BGR_REG_TCONTV_GATING_CLEAR_MASK   0x00000001
 
#define TCONTV_BGR_REG_TCONTV_GATING_MASK   0x0
 
#define TCONTV_BGR_REG_TCONTV_GATING_PASS   0x1
 
#define LVDS_BGR_REG   0x00000bac
 
#define LVDS_BGR_REG_LVDS1_RST_OFFSET   17
 
#define LVDS_BGR_REG_LVDS1_RST_CLEAR_MASK   0x00020000
 
#define LVDS_BGR_REG_LVDS1_RST_ASSERT   0x0
 
#define LVDS_BGR_REG_LVDS1_RST_DE_ASSERT   0x1
 
#define LVDS_BGR_REG_LVDS0_RST_OFFSET   16
 
#define LVDS_BGR_REG_LVDS0_RST_CLEAR_MASK   0x00010000
 
#define LVDS_BGR_REG_LVDS0_RST_ASSERT   0x0
 
#define LVDS_BGR_REG_LVDS0_RST_DE_ASSERT   0x1
 
#define LEDC_CLK_REG   0x00000bf0
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   0x80000000
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0x1
 
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000
 
#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x001
 
#define LEDC_CLK_REG_FACTOR_M_OFFSET   0
 
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define LEDC_BGR_REG   0x00000bfc
 
#define LEDC_BGR_REG_LEDC_RST_OFFSET   16
 
#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK   0x00010000
 
#define LEDC_BGR_REG_LEDC_RST_ASSERT   0x0
 
#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT   0x1
 
#define LEDC_BGR_REG_LEDC_GATING_OFFSET   0
 
#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK   0x00000001
 
#define LEDC_BGR_REG_LEDC_GATING_MASK   0x0
 
#define LEDC_BGR_REG_LEDC_GATING_PASS   0x1
 
#define CSI_CLK_REG   0x00000c04
 
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x010
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x011
 
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x100
 
#define CSI_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER0_CLK_REG   0x00000c08
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011
 
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER1_CLK_REG   0x00000c0c
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011
 
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER2_CLK_REG   0x00000c10
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011
 
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_MASTER3_CLK_REG   0x00000c14
 
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET   31
 
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK   0x80000000
 
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON   0x1
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011
 
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100
 
#define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET   8
 
#define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00
 
#define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET   0
 
#define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define CSI_BGR_REG   0x00000c1c
 
#define CSI_BGR_REG_CSI_RST_OFFSET   16
 
#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   0x00010000
 
#define CSI_BGR_REG_CSI_RST_ASSERT   0x0
 
#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0x1
 
#define CSI_BGR_REG_CSI_GATING_OFFSET   0
 
#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   0x00000001
 
#define CSI_BGR_REG_CSI_GATING_MASK   0x0
 
#define CSI_BGR_REG_CSI_GATING_PASS   0x1
 
#define ISP_CLK_REG   0x00000c20
 
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   0x80000000
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0x1
 
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000
 
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010
 
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011
 
#define ISP_CLK_REG_FACTOR_M_OFFSET   0
 
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define ISP_BGR_REG   0x00000c2c
 
#define ISP_BGR_REG_ISP_RST_OFFSET   16
 
#define ISP_BGR_REG_ISP_RST_CLEAR_MASK   0x00010000
 
#define ISP_BGR_REG_ISP_RST_ASSERT   0x0
 
#define ISP_BGR_REG_ISP_RST_DE_ASSERT   0x1
 
#define DSP_CLK_REG   0x00000c70
 
#define DSP_CLK_REG_DSP_CLK_GATING_OFFSET   31
 
#define DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK   0x80000000
 
#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF   0x0
 
#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON   0x1
 
#define DSP_CLK_REG_CLK_SRC_SEL_OFFSET   24
 
#define DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000
 
#define DSP_CLK_REG_CLK_SRC_SEL_HOSC   0x000
 
#define DSP_CLK_REG_CLK_SRC_SEL_CLK32K   0x001
 
#define DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x010
 
#define DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x011
 
#define DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x100
 
#define DSP_CLK_REG_FACTOR_M_OFFSET   0
 
#define DSP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f
 
#define AHB_GATE_EN_REG   0x00000e04
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0x0
 
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0x1
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0x0
 
#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0x1
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   0x10000000
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET   22
 
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_OFFSET   21
 
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00200000
 
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_OFFSET   20
 
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET   19
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET   18
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00040000
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET   17
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET   16
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET   9
 
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000200
 
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET   8
 
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100
 
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   7
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   6
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000040
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   5
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000020
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET   4
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000010
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET   3
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET   1
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET   0
 
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000001
 
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE   0x0
 
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG   0x00000e08
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0x0
 
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0x1
 
#define CLK24M_GATE_EN_REG   0x00000e0c
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   0x00000008
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0x0
 
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0x1
 
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_OFFSET   1
 
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_CLEAR_MASK   0x00000002
 
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_DISABLE   0x0
 
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_ENABLE   0x1
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET   0
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK   0x00000001
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE   0x0
 
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE   0x1
 
#define CCU_SEC_SWITCH_REG   0x00000f00
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0x0
 
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0x1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0x0
 
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0x1
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0x0
 
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0x1
 
#define PLL_LOCK_DBG_CTRL_REG   0x00000f04
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   0x80000000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0x0
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0x1
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   0x00700000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPUPLL   0x000
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL   0x001
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERIPLL2X   0x010
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL4X   0x011
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CSIPLL4X   0x100
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIOPLL4X   0x110
 
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL   0x111
 
#define SYSDAP_REQ_CTRL_REG   0x00000f08
 
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET   0
 
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK   0x00000001
 
#define CCU_FAN_GATE_REG   0x00000f30
 
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0x1
 
#define CLK27M_FAN_REG   0x00000f34
 
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31
 
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0x0
 
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0x1
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL1X   0x000
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL1X   0x001
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL1X   0x010
 
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL1X   0x011
 
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8
 
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00001f00
 
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0
 
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f
 
#define CLK_FAN_REG   0x00000f38
 
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0x0
 
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0x1
 
#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5
 
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0
 
#define CLK_FAN_REG_PCLK_DIV_OFFSET   0
 
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f
 
#define CCU_FAN_REG   0x00000f3c
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   0x00800000
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   0x00400000
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   0x00200000
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0x0
 
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0x1
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   0x000001c0
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2   0x001
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10   0x010
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO   0x011
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6   0x100
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0x101
 
#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0x110
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   0x00000038
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2   0x001
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10   0x010
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO   0x011
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6   0x100
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0x101
 
#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0x110
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   0x00000007
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2   0x001
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10   0x010
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO   0x011
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6   0x100
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0x101
 
#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0x110
 
#define PLL_CFG0_REG   0x00000f40
 
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0
 
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   0xffffffff
 
#define PLL_CFG1_REG   0x00000f44
 
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0
 
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   0xffffffff
 
#define PLL_CFG2_REG   0x00000f48
 
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0
 
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   0xffffffff
 
#define CCU_VERSION_REG   0x00000ff0
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16
 
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0
 
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff
 
#define CCU_BASE   SUNXI_CCMU_BASE
 
#define APB2_CLK_SRC_OSC24M   (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_OSC32K   (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_PSI   (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_SRC_PLL6   (APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define APB2_CLK_RATE_N_1   (0x0 << 8)
 
#define APB2_CLK_RATE_N_2   (0x1 << 8)
 
#define APB2_CLK_RATE_N_4   (0x2 << 8)
 
#define APB2_CLK_RATE_N_8   (0x3 << 8)
 
#define APB2_CLK_RATE_N_MASK   (3 << 8)
 
#define APB2_CLK_RATE_M(m)   (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)
 
#define CCU_MMC_CTRL_M(x)   ((x) -1)
 
#define CCU_MMC_CTRL_N(x)   ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
 
#define CCU_MMC_CTRL_OSCM24   (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PLL6X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_PLL_PERIPH2X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CCU_MMC_CTRL_ENABLE   (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
 
#define CCU_MMC_CTRL_OCLK_DLY(a)   ((void) (a), 0)
 
#define CCU_MMC_CTRL_SCLK_DLY(a)   ((void) (a), 0)
 
#define CCU_MMC_BGR_SMHC0_GATE   (1 << 0)
 
#define CCU_MMC_BGR_SMHC1_GATE   (1 << 1)
 
#define CCU_MMC_BGR_SMHC2_GATE   (1 << 2)
 
#define CCU_MMC_BGR_SMHC0_RST   (1 << 16)
 
#define CCU_MMC_BGR_SMHC1_RST   (1 << 17)
 
#define CCU_MMC_BGR_SMHC2_RST   (1 << 18)
 
#define RESET_SHIFT   (16)
 
#define GATING_SHIFT   (0)
 
#define CCU_PLL_CPU0_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000)
 
#define CCU_PLL_CPU1_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x04)
 
#define CCU_PLL_CPU2_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x08)
 
#define CCU_PLL_CPU3_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x0c)
 
#define CCU_PLL_DDR0_CTRL_REG   (PLL_DDR_CTRL_REG)
 
#define CCU_PLL_DDR1_CTRL_REG   (0x18)
 
#define CCU_PLL_PERI0_CTRL_REG   (PLL_PERI0_CTRL_REG)
 
#define CCU_PLL_PERI1_CTRL_REG   (PLL_PERI1_CTRL_REG)
 
#define CCU_PLL_GPU_CTRL_REG   (PLL_GPU_CTRL_REG)
 
#define CCU_PLL_VIDE00_CTRL_REG   (PLL_VIDEO0_CTRL_REG)
 
#define CCU_PLL_VIDE01_CTRL_REG   (PLL_VIDEO1_CTRL_REG)
 
#define CCU_PLL_VIDE02_CTRL_REG   (PLL_VIDEO2_CTRL_REG)
 
#define CCU_PLL_VIDE03_CTRL_REG   (PLL_VIDEO3_CTRL_REG)
 
#define CCU_PLL_VE_CTRL_REG   (PLL_VE_CTRL_REG)
 
#define CCU_PLL_CPUA_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x60)
 
#define CCU_PLL_CPUB_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x64)
 
#define CCU_PLL_CPU_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x68)
 
#define CCU_PLL_DSU_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x6C)
 
#define CCU_PLL_AUDIO_CTRL_REG   (PLL_AUDIO_CTRL_REG)
 
#define CCU_PLL_HSIC_CTRL_REG   (0x70)
 
#define CCU_CPUX_AXI_CFG_REG   (CPU_CLK_REG)
 
#define CCU_AHB0_CFG_REG   (0x510)
 
#define CCU_APB0_CFG_REG   (0x520)
 
#define CCU_APB1_CFG_REG   (0x524)
 
#define CCU_MBUS_CFG_REG   (0x540)
 
#define CCU_CE_CLK_REG   (0x680)
 
#define CCU_CE_BGR_REG   (0x68C)
 
#define CCU_VE_CLK_REG   (0x690)
 
#define CCU_VE_BGR_REG   (0x69C)
 
#define CCU_DMA_BGR_REG   (0x70C)
 
#define CCU_AVS_CLK_REG   (0x750)
 
#define CCU_AVS_BGR_REG   (0x74C)
 
#define CCU_IOMMU_BGR_REG   (0x7bc)
 
#define IOMMU_AUTO_GATING_REG   (SUNXI_IOMMU_BASE + 0X40)
 
#define CCU_DRAM_CLK_REG   (0x800)
 
#define CCU_MBUS_MAT_CLK_GATING_REG   (0x804)
 
#define CCU_PLL_DDR_AUX_REG   (0x808)
 
#define CCU_DRAM_BGR_REG   (0x80C)
 
#define CCU_NAND_CLK_REG   (0x810)
 
#define CCU_NAND_BGR_REG   (0x82C)
 
#define CCU_SMHC0_CLK_REG   (0x830)
 
#define CCU_SMHC1_CLK_REG   (0x834)
 
#define CCU_SMHC2_CLK_REG   (0x838)
 
#define CCU_SMHC_BGR_REG   (0x84c)
 
#define CCU_UART_BGR_REG   (0x90C)
 
#define CCU_TWI_BGR_REG   (0x91C)
 
#define CCU_SCR_BGR_REG   (0x93C)
 
#define CCU_SPI0_CLK_REG   (0x940)
 
#define CCU_SPI1_CLK_REG   (0x944)
 
#define CCU_SPI_BGR_REG   (0x96C)
 
#define CCU_USB0_CLK_REG   (0xA70)
 
#define CCU_USB_BGR_REG   (0xA8C)
 
#define DMA_GATING_BASE   CCU_DMA_BGR_REG
 
#define DMA_GATING_PASS   (1)
 
#define DMA_GATING_BIT   (0)
 
#define CE_CLK_SRC_MASK   (0x7)
 
#define CE_CLK_SRC_SEL_BIT   (CE_CLK_REG_CLK_SRC_SEL_OFFSET)
 
#define CE_CLK_SRC   (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)
 
#define CE_CLK_DIV_RATION_N_BIT   (0)
 
#define CE_CLK_DIV_RATION_N_MASK   (0x0)
 
#define CE_CLK_DIV_RATION_N   (0)
 
#define CE_CLK_DIV_RATION_M_BIT   (CE_CLK_REG_FACTOR_M_OFFSET)
 
#define CE_CLK_DIV_RATION_M_MASK   (CE_CLK_REG_FACTOR_M_CLEAR_MASK)
 
#define CE_CLK_DIV_RATION_M   (0)
 
#define CE_SCLK_ONOFF_BIT   (31)
 
#define CE_SCLK_ON   (1)
 
#define CE_GATING_BASE   CCU_CE_BGR_REG
 
#define CE_GATING_PASS   (1)
 
#define CE_GATING_BIT   (0)
 
#define CE_RST_REG_BASE   CCU_CE_BGR_REG
 
#define CE_SYS_RST_BIT   (CE_BGR_REG_CE_SYS_RST_OFFSET)
 
#define CE_RST_BIT   (CE_BGR_REG_CE_RST_OFFSET)
 
#define CE_DEASSERT   (CE_BGR_REG_CE_SYS_RST_DE_ASSERT)
 
#define CE_SYS_GATING_BIT   (CE_BGR_REG_CE_SYS_GATING_OFFSET)
 
#define CCU_GPADC_BGR_REG   (0x09EC)
 
#define CCU_GPADC_CLK_REG   (0x09E0)
 
#define CCU_LRADC_BGR_REG   (0x0A9C)
 
#define BUS_CLK_GATING_REG   0x60
 
#define BUS_SOFTWARE_RESET_REG   0x2c0
 
#define USBPHY_CONFIG_REG   0xcc
 
#define USBEHCI0_RST_BIT   24
 
#define USBEHCI0_GATIING_BIT   24
 
#define USBPHY0_RST_BIT   0
 
#define USBPHY0_SCLK_GATING_BIT   8
 
#define USBEHCI1_RST_BIT   25
 
#define USBEHCI1_GATIING_BIT   25
 
#define USBPHY1_RST_BIT   1
 
#define USBPHY1_SCLK_GATING_BIT   9
 
#define CCM_SPIF_CTRL_M(x)   ((x) -1)
 
#define CCM_SPIF_CTRL_N(x)   ((x) << 8)
 
#define CCM_SPIF_CTRL_HOSC   (0x0 << 24)
 
#define CCM_SPIF_CTRL_PERI400M   (0x1 << 24)
 
#define CCM_SPIF_CTRL_PERI300M   (0x2 << 24)
 
#define CCM_SPIF_CTRL_ENABLE   (0x1 << 31)
 
#define GET_SPIF_CLK_SOURECS(x)   (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)
 
#define CCM_SPIF_CTRL_PERI   CCM_SPIF_CTRL_PERI400M
 
#define SPIF_RESET_SHIFT   (19)
 
#define SPIF_GATING_SHIFT   (3)
 
#define RISCV_PUBSRAM_CFG_REG   (SUNXI_DSP_PRCM_BASE + 0x0114)
 
#define RISCV_PUBSRAM_RST   (0x1 << 16)
 
#define RISCV_PUBSRAM_GATING   (0x1 << 0)
 
#define RISCV_CLK_REG   (SUNXI_DSP_PRCM_BASE + 0x0120)
 
#define RISCV_CLK_GATING   (0x1 << 31)
 
#define RISCV_CFG_BGR_REG   (SUNXI_DSP_PRCM_BASE + 0x0124)
 
#define RISCV_CORE_RST   (0x1 << 18)
 
#define RISCV_APB_DB_RST   (0x1 << 17)
 
#define RISCV_CFG_RST   (0x1 << 16)
 
#define RISCV_CFG_GATING   (0x1 << 0)
 
#define RISCV_CFG_BASE   (0x07130000)
 
#define RISCV_STA_ADD_REG   (RISCV_CFG_BASE + 0x0204)
 

Macro Definition Documentation

◆ AHB_CLK_REG

#define AHB_CLK_REG   0x00000510

◆ AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10

◆ AHB_CLK_REG_CLK_SRC_SEL_CLK32K

#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K   0x01

◆ AHB_CLK_REG_CLK_SRC_SEL_HOSC

#define AHB_CLK_REG_CLK_SRC_SEL_HOSC   0x00

◆ AHB_CLK_REG_CLK_SRC_SEL_OFFSET

#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11

◆ AHB_CLK_REG_FACTOR_M_CLEAR_MASK

#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ AHB_CLK_REG_FACTOR_M_OFFSET

#define AHB_CLK_REG_FACTOR_M_OFFSET   0

◆ AHB_GATE_EN_REG

#define AHB_GATE_EN_REG   0x00000e04

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK   0x80000000

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0x0

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0x1

◆ AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET   31

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK   0x10000000

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET   28

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000100

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET   8

◆ AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_OFFSET   20

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000200

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET   9

◆ AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00200000

◆ AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_OFFSET   21

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000001

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET   0

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK

#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK   0x20000000

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE   0x0

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE

#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE   0x1

◆ AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET

#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET   29

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000020

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET   5

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET   17

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000040

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET   6

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET   18

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000080

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET   7

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET   19

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET   22

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000010

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET   4

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET   16

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000002

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET   1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000004

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET   2

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK   0x00000008

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE   0x0

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE   0x1

◆ AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET

#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET   3

◆ APB0_CLK_REG

#define APB0_CLK_REG   0x00000520

◆ APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10

◆ APB0_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K   0x01

◆ APB0_CLK_REG_CLK_SRC_SEL_HOSC

#define APB0_CLK_REG_CLK_SRC_SEL_HOSC   0x00

◆ APB0_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11

◆ APB0_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB0_CLK_REG_FACTOR_M_OFFSET

#define APB0_CLK_REG_FACTOR_M_OFFSET   0

◆ APB1_CLK_REG

#define APB1_CLK_REG   0x00000524

◆ APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x10

◆ APB1_CLK_REG_CLK_SRC_SEL_CLK32K

#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K   0x01

◆ APB1_CLK_REG_CLK_SRC_SEL_HOSC

#define APB1_CLK_REG_CLK_SRC_SEL_HOSC   0x00

◆ APB1_CLK_REG_CLK_SRC_SEL_OFFSET

#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS

#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS   0x11

◆ APB1_CLK_REG_FACTOR_M_CLEAR_MASK

#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ APB1_CLK_REG_FACTOR_M_OFFSET

#define APB1_CLK_REG_FACTOR_M_OFFSET   0

◆ APB2_CLK_RATE_M

#define APB2_CLK_RATE_M (   m)    (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_M_MASK

#define APB2_CLK_RATE_M_MASK   (3 << APB1_CLK_REG_FACTOR_M_OFFSET)

◆ APB2_CLK_RATE_N_1

#define APB2_CLK_RATE_N_1   (0x0 << 8)

◆ APB2_CLK_RATE_N_2

#define APB2_CLK_RATE_N_2   (0x1 << 8)

◆ APB2_CLK_RATE_N_4

#define APB2_CLK_RATE_N_4   (0x2 << 8)

◆ APB2_CLK_RATE_N_8

#define APB2_CLK_RATE_N_8   (0x3 << 8)

◆ APB2_CLK_RATE_N_MASK

#define APB2_CLK_RATE_N_MASK   (3 << 8)

◆ APB2_CLK_SRC_OSC24M

#define APB2_CLK_SRC_OSC24M   (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB2_CLK_SRC_OSC32K

#define APB2_CLK_SRC_OSC32K   (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB2_CLK_SRC_PLL6

#define APB2_CLK_SRC_PLL6   (APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ APB2_CLK_SRC_PSI

#define APB2_CLK_SRC_PSI   (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ AVS_CLK_REG

#define AVS_CLK_REG   0x00000750

◆ AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK

#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK   0x80000000

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF   0x0

◆ AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON

#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON   0x1

◆ AVS_CLK_REG_AVS_CLK_GATING_OFFSET

#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET   31

◆ BUS_CLK_GATING_REG

#define BUS_CLK_GATING_REG   0x60

◆ BUS_SOFTWARE_RESET_REG

#define BUS_SOFTWARE_RESET_REG   0x2c0

◆ CAN_BGR_REG

#define CAN_BGR_REG   0x0000092c

◆ CAN_BGR_REG_CAN0_GATING_CLEAR_MASK

#define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK   0x00000001

◆ CAN_BGR_REG_CAN0_GATING_MASK

#define CAN_BGR_REG_CAN0_GATING_MASK   0x0

◆ CAN_BGR_REG_CAN0_GATING_OFFSET

#define CAN_BGR_REG_CAN0_GATING_OFFSET   0

◆ CAN_BGR_REG_CAN0_GATING_PASS

#define CAN_BGR_REG_CAN0_GATING_PASS   0x1

◆ CAN_BGR_REG_CAN0_RST_ASSERT

#define CAN_BGR_REG_CAN0_RST_ASSERT   0x0

◆ CAN_BGR_REG_CAN0_RST_CLEAR_MASK

#define CAN_BGR_REG_CAN0_RST_CLEAR_MASK   0x00010000

◆ CAN_BGR_REG_CAN0_RST_DE_ASSERT

#define CAN_BGR_REG_CAN0_RST_DE_ASSERT   0x1

◆ CAN_BGR_REG_CAN0_RST_OFFSET

#define CAN_BGR_REG_CAN0_RST_OFFSET   16

◆ CCM_SPIF_CTRL_ENABLE

#define CCM_SPIF_CTRL_ENABLE   (0x1 << 31)

◆ CCM_SPIF_CTRL_HOSC

#define CCM_SPIF_CTRL_HOSC   (0x0 << 24)

◆ CCM_SPIF_CTRL_M

#define CCM_SPIF_CTRL_M (   x)    ((x) -1)

◆ CCM_SPIF_CTRL_N

#define CCM_SPIF_CTRL_N (   x)    ((x) << 8)

◆ CCM_SPIF_CTRL_PERI

#define CCM_SPIF_CTRL_PERI   CCM_SPIF_CTRL_PERI400M

◆ CCM_SPIF_CTRL_PERI300M

#define CCM_SPIF_CTRL_PERI300M   (0x2 << 24)

◆ CCM_SPIF_CTRL_PERI400M

#define CCM_SPIF_CTRL_PERI400M   (0x1 << 24)

◆ CCU_AHB0_CFG_REG

#define CCU_AHB0_CFG_REG   (0x510)

◆ CCU_APB0_CFG_REG

#define CCU_APB0_CFG_REG   (0x520)

◆ CCU_APB1_CFG_REG

#define CCU_APB1_CFG_REG   (0x524)

◆ CCU_AVS_BGR_REG

#define CCU_AVS_BGR_REG   (0x74C)

◆ CCU_AVS_CLK_REG

#define CCU_AVS_CLK_REG   (0x750)

◆ CCU_BASE

#define CCU_BASE   SUNXI_CCMU_BASE

◆ CCU_CE_BGR_REG

#define CCU_CE_BGR_REG   (0x68C)

◆ CCU_CE_CLK_REG

#define CCU_CE_CLK_REG   (0x680)

◆ CCU_CPUX_AXI_CFG_REG

#define CCU_CPUX_AXI_CFG_REG   (CPU_CLK_REG)

◆ CCU_DMA_BGR_REG

#define CCU_DMA_BGR_REG   (0x70C)

◆ CCU_DRAM_BGR_REG

#define CCU_DRAM_BGR_REG   (0x80C)

◆ CCU_DRAM_CLK_REG

#define CCU_DRAM_CLK_REG   (0x800)

◆ CCU_FAN_GATE_REG

#define CCU_FAN_GATE_REG   0x00000f30

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK   0x00000002

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_GATE_REG_CLK12M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET   1

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK   0x00000004

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_GATE_REG_CLK16M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET   2

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK   0x00000001

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_GATE_REG_CLK24M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET   0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK

#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK   0x00000008

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON

#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_GATE_REG_CLK25M_EN_OFFSET

#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET   3

◆ CCU_FAN_REG

#define CCU_FAN_REG   0x00000f3c

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK   0x00200000

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET   21

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK   0x00000007

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2   0x001

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10   0x010

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO   0x011

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6   0x100

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M   0x101

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET   0

◆ CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK   0x110

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK   0x00400000

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET   22

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK   0x00000038

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2   0x001

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10   0x010

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO   0x011

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6   0x100

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M   0x101

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET   3

◆ CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK   0x110

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK   0x00800000

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF   0x0

◆ CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON

#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON   0x1

◆ CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET   23

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK   0x000001c0

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2   0x001

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10   0x010

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO   0x011

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6   0x100

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M   0x101

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC

#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC   0x000

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET

#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET   6

◆ CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK

#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK   0x110

◆ CCU_GPADC_BGR_REG

#define CCU_GPADC_BGR_REG   (0x09EC)

◆ CCU_GPADC_CLK_REG

#define CCU_GPADC_CLK_REG   (0x09E0)

◆ CCU_IOMMU_BGR_REG

#define CCU_IOMMU_BGR_REG   (0x7bc)

◆ CCU_LRADC_BGR_REG

#define CCU_LRADC_BGR_REG   (0x0A9C)

◆ CCU_MBUS_CFG_REG

#define CCU_MBUS_CFG_REG   (0x540)

◆ CCU_MBUS_MAT_CLK_GATING_REG

#define CCU_MBUS_MAT_CLK_GATING_REG   (0x804)

◆ CCU_MMC_BGR_SMHC0_GATE

#define CCU_MMC_BGR_SMHC0_GATE   (1 << 0)

◆ CCU_MMC_BGR_SMHC0_RST

#define CCU_MMC_BGR_SMHC0_RST   (1 << 16)

◆ CCU_MMC_BGR_SMHC1_GATE

#define CCU_MMC_BGR_SMHC1_GATE   (1 << 1)

◆ CCU_MMC_BGR_SMHC1_RST

#define CCU_MMC_BGR_SMHC1_RST   (1 << 17)

◆ CCU_MMC_BGR_SMHC2_GATE

#define CCU_MMC_BGR_SMHC2_GATE   (1 << 2)

◆ CCU_MMC_BGR_SMHC2_RST

#define CCU_MMC_BGR_SMHC2_RST   (1 << 18)

◆ CCU_MMC_CTRL_ENABLE

#define CCU_MMC_CTRL_ENABLE   (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)

◆ CCU_MMC_CTRL_M

#define CCU_MMC_CTRL_M (   x)    ((x) -1)

◆ CCU_MMC_CTRL_N

#define CCU_MMC_CTRL_N (   x)    ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)

◆ CCU_MMC_CTRL_OCLK_DLY

#define CCU_MMC_CTRL_OCLK_DLY (   a)    ((void) (a), 0)

◆ CCU_MMC_CTRL_OSCM24

#define CCU_MMC_CTRL_OSCM24   (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PLL6X2

#define CCU_MMC_CTRL_PLL6X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_PLL_PERIPH2X2

#define CCU_MMC_CTRL_PLL_PERIPH2X2   (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CCU_MMC_CTRL_SCLK_DLY

#define CCU_MMC_CTRL_SCLK_DLY (   a)    ((void) (a), 0)

◆ CCU_NAND_BGR_REG

#define CCU_NAND_BGR_REG   (0x82C)

◆ CCU_NAND_CLK_REG

#define CCU_NAND_CLK_REG   (0x810)

◆ CCU_PLL_AUDIO_CTRL_REG

#define CCU_PLL_AUDIO_CTRL_REG   (PLL_AUDIO_CTRL_REG)

◆ CCU_PLL_CPU0_CTRL_REG

#define CCU_PLL_CPU0_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000)

◆ CCU_PLL_CPU1_CTRL_REG

#define CCU_PLL_CPU1_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x04)

◆ CCU_PLL_CPU2_CTRL_REG

#define CCU_PLL_CPU2_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x08)

◆ CCU_PLL_CPU3_CTRL_REG

#define CCU_PLL_CPU3_CTRL_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x0c)

◆ CCU_PLL_CPU_CLK_REG

#define CCU_PLL_CPU_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x68)

◆ CCU_PLL_CPUA_CLK_REG

#define CCU_PLL_CPUA_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x60)

◆ CCU_PLL_CPUB_CLK_REG

#define CCU_PLL_CPUB_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x64)

◆ CCU_PLL_DDR0_CTRL_REG

#define CCU_PLL_DDR0_CTRL_REG   (PLL_DDR_CTRL_REG)

◆ CCU_PLL_DDR1_CTRL_REG

#define CCU_PLL_DDR1_CTRL_REG   (0x18)

◆ CCU_PLL_DDR_AUX_REG

#define CCU_PLL_DDR_AUX_REG   (0x808)

◆ CCU_PLL_DSU_CLK_REG

#define CCU_PLL_DSU_CLK_REG   (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x6C)

◆ CCU_PLL_GPU_CTRL_REG

#define CCU_PLL_GPU_CTRL_REG   (PLL_GPU_CTRL_REG)

◆ CCU_PLL_HSIC_CTRL_REG

#define CCU_PLL_HSIC_CTRL_REG   (0x70)

◆ CCU_PLL_PERI0_CTRL_REG

#define CCU_PLL_PERI0_CTRL_REG   (PLL_PERI0_CTRL_REG)

◆ CCU_PLL_PERI1_CTRL_REG

#define CCU_PLL_PERI1_CTRL_REG   (PLL_PERI1_CTRL_REG)

◆ CCU_PLL_VE_CTRL_REG

#define CCU_PLL_VE_CTRL_REG   (PLL_VE_CTRL_REG)

◆ CCU_PLL_VIDE00_CTRL_REG

#define CCU_PLL_VIDE00_CTRL_REG   (PLL_VIDEO0_CTRL_REG)

◆ CCU_PLL_VIDE01_CTRL_REG

#define CCU_PLL_VIDE01_CTRL_REG   (PLL_VIDEO1_CTRL_REG)

◆ CCU_PLL_VIDE02_CTRL_REG

#define CCU_PLL_VIDE02_CTRL_REG   (PLL_VIDEO2_CTRL_REG)

◆ CCU_PLL_VIDE03_CTRL_REG

#define CCU_PLL_VIDE03_CTRL_REG   (PLL_VIDEO3_CTRL_REG)

◆ CCU_SCR_BGR_REG

#define CCU_SCR_BGR_REG   (0x93C)

◆ CCU_SEC_SWITCH_REG

#define CCU_SEC_SWITCH_REG   0x00000f00

◆ CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK   0x00000002

◆ CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE   0x1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET   1

◆ CCU_SEC_SWITCH_REG_BUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE   0x0

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK   0x00000004

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE   0x1

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET   2

◆ CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE

#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE   0x0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK

#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK   0x00000001

◆ CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE   0x1

◆ CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET

#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET   0

◆ CCU_SEC_SWITCH_REG_PLL_SEC_SECURE

#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE   0x0

◆ CCU_SMHC0_CLK_REG

#define CCU_SMHC0_CLK_REG   (0x830)

◆ CCU_SMHC1_CLK_REG

#define CCU_SMHC1_CLK_REG   (0x834)

◆ CCU_SMHC2_CLK_REG

#define CCU_SMHC2_CLK_REG   (0x838)

◆ CCU_SMHC_BGR_REG

#define CCU_SMHC_BGR_REG   (0x84c)

◆ CCU_SPI0_CLK_REG

#define CCU_SPI0_CLK_REG   (0x940)

◆ CCU_SPI1_CLK_REG

#define CCU_SPI1_CLK_REG   (0x944)

◆ CCU_SPI_BGR_REG

#define CCU_SPI_BGR_REG   (0x96C)

◆ CCU_TWI_BGR_REG

#define CCU_TWI_BGR_REG   (0x91C)

◆ CCU_UART_BGR_REG

#define CCU_UART_BGR_REG   (0x90C)

◆ CCU_USB0_CLK_REG

#define CCU_USB0_CLK_REG   (0xA70)

◆ CCU_USB_BGR_REG

#define CCU_USB_BGR_REG   (0xA8C)

◆ CCU_VE_BGR_REG

#define CCU_VE_BGR_REG   (0x69C)

◆ CCU_VE_CLK_REG

#define CCU_VE_CLK_REG   (0x690)

◆ CCU_VERSION_REG

#define CCU_VERSION_REG   0x00000ff0

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK   0xffff0000

◆ CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET   16

◆ CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK

#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK   0x0000ffff

◆ CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET

#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET   0

◆ CE_BGR_REG

#define CE_BGR_REG   0x0000068c

◆ CE_BGR_REG_CE_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_GATING_CLEAR_MASK   0x00000001

◆ CE_BGR_REG_CE_GATING_MASK

#define CE_BGR_REG_CE_GATING_MASK   0x0

◆ CE_BGR_REG_CE_GATING_OFFSET

#define CE_BGR_REG_CE_GATING_OFFSET   0

◆ CE_BGR_REG_CE_GATING_PASS

#define CE_BGR_REG_CE_GATING_PASS   0x1

◆ CE_BGR_REG_CE_RST_ASSERT

#define CE_BGR_REG_CE_RST_ASSERT   0x0

◆ CE_BGR_REG_CE_RST_CLEAR_MASK

#define CE_BGR_REG_CE_RST_CLEAR_MASK   0x00010000

◆ CE_BGR_REG_CE_RST_DE_ASSERT

#define CE_BGR_REG_CE_RST_DE_ASSERT   0x1

◆ CE_BGR_REG_CE_RST_OFFSET

#define CE_BGR_REG_CE_RST_OFFSET   16

◆ CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK   0x00000002

◆ CE_BGR_REG_CE_SYS_GATING_MASK

#define CE_BGR_REG_CE_SYS_GATING_MASK   0x0

◆ CE_BGR_REG_CE_SYS_GATING_OFFSET

#define CE_BGR_REG_CE_SYS_GATING_OFFSET   1

◆ CE_BGR_REG_CE_SYS_GATING_PASS

#define CE_BGR_REG_CE_SYS_GATING_PASS   0x1

◆ CE_BGR_REG_CE_SYS_RST_ASSERT

#define CE_BGR_REG_CE_SYS_RST_ASSERT   0x0

◆ CE_BGR_REG_CE_SYS_RST_CLEAR_MASK

#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK   0x00020000

◆ CE_BGR_REG_CE_SYS_RST_DE_ASSERT

#define CE_BGR_REG_CE_SYS_RST_DE_ASSERT   0x1

◆ CE_BGR_REG_CE_SYS_RST_OFFSET

#define CE_BGR_REG_CE_SYS_RST_OFFSET   17

◆ CE_CLK_DIV_RATION_M

#define CE_CLK_DIV_RATION_M   (0)

◆ CE_CLK_DIV_RATION_M_BIT

#define CE_CLK_DIV_RATION_M_BIT   (CE_CLK_REG_FACTOR_M_OFFSET)

◆ CE_CLK_DIV_RATION_M_MASK

#define CE_CLK_DIV_RATION_M_MASK   (CE_CLK_REG_FACTOR_M_CLEAR_MASK)

◆ CE_CLK_DIV_RATION_N

#define CE_CLK_DIV_RATION_N   (0)

◆ CE_CLK_DIV_RATION_N_BIT

#define CE_CLK_DIV_RATION_N_BIT   (0)

◆ CE_CLK_DIV_RATION_N_MASK

#define CE_CLK_DIV_RATION_N_MASK   (0x0)

◆ CE_CLK_REG

#define CE_CLK_REG   0x00000680

◆ CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK

#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK   0x80000000

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON

#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON   0x1

◆ CE_CLK_REG_CE_CLK_GATING_OFFSET

#define CE_CLK_REG_CE_CLK_GATING_OFFSET   31

◆ CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CE_CLK_REG_CLK_SRC_SEL_HOSC

#define CE_CLK_REG_CLK_SRC_SEL_HOSC   0b0

◆ CE_CLK_REG_CLK_SRC_SEL_OFFSET

#define CE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0b11

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0b10

◆ CE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0b1

◆ CE_CLK_REG_FACTOR_M_CLEAR_MASK

#define CE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CE_CLK_REG_FACTOR_M_OFFSET

#define CE_CLK_REG_FACTOR_M_OFFSET   0

◆ CE_CLK_SRC

#define CE_CLK_SRC   (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)

◆ CE_CLK_SRC_MASK

#define CE_CLK_SRC_MASK   (0x7)

◆ CE_CLK_SRC_SEL_BIT

#define CE_CLK_SRC_SEL_BIT   (CE_CLK_REG_CLK_SRC_SEL_OFFSET)

◆ CE_DEASSERT

#define CE_DEASSERT   (CE_BGR_REG_CE_SYS_RST_DE_ASSERT)

◆ CE_GATING_BASE

#define CE_GATING_BASE   CCU_CE_BGR_REG

◆ CE_GATING_BIT

#define CE_GATING_BIT   (0)

◆ CE_GATING_PASS

#define CE_GATING_PASS   (1)

◆ CE_RST_BIT

#define CE_RST_BIT   (CE_BGR_REG_CE_RST_OFFSET)

◆ CE_RST_REG_BASE

#define CE_RST_REG_BASE   CCU_CE_BGR_REG

◆ CE_SCLK_ON

#define CE_SCLK_ON   (1)

◆ CE_SCLK_ONOFF_BIT

#define CE_SCLK_ONOFF_BIT   (31)

◆ CE_SYS_GATING_BIT

#define CE_SYS_GATING_BIT   (CE_BGR_REG_CE_SYS_GATING_OFFSET)

◆ CE_SYS_RST_BIT

#define CE_SYS_RST_BIT   (CE_BGR_REG_CE_SYS_RST_OFFSET)

◆ CLK24M_GATE_EN_REG

#define CLK24M_GATE_EN_REG   0x00000e0c

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK   0x00000008

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE   0x0

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE   0x1

◆ CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET   3

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK   0x00000001

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE   0x0

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE   0x1

◆ CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET   0

◆ CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_CLEAR_MASK

#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_CLEAR_MASK   0x00000002

◆ CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_DISABLE

#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_DISABLE   0x0

◆ CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_ENABLE

#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_ENABLE   0x1

◆ CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_OFFSET

#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_OFFSET   1

◆ CLK27M_FAN_REG

#define CLK27M_FAN_REG   0x00000f34

◆ CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK   0x0000001f

◆ CLK27M_FAN_REG_CLK27M_DIV0_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET   0

◆ CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK   0x00001f00

◆ CLK27M_FAN_REG_CLK27M_DIV1_OFFSET

#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET   8

◆ CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK   0x80000000

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF   0x0

◆ CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON

#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON   0x1

◆ CLK27M_FAN_REG_CLK27M_EN_OFFSET

#define CLK27M_FAN_REG_CLK27M_EN_OFFSET   31

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK   0x03000000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET   24

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL1X   0x000

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL1X   0x001

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL1X   0x010

◆ CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL1X

#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL1X   0x011

◆ CLK_FAN_REG

#define CLK_FAN_REG   0x00000f38

◆ CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK   0x000003e0

◆ CLK_FAN_REG_PCLK_DIV1_OFFSET

#define CLK_FAN_REG_PCLK_DIV1_OFFSET   5

◆ CLK_FAN_REG_PCLK_DIV_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK   0x0000001f

◆ CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK

#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK   0x80000000

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF   0x0

◆ CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON

#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON   0x1

◆ CLK_FAN_REG_PCLK_DIV_EN_OFFSET

#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET   31

◆ CLK_FAN_REG_PCLK_DIV_OFFSET

#define CLK_FAN_REG_PCLK_DIV_OFFSET   0

◆ COMBPHY0_CLK_REG

#define COMBPHY0_CLK_REG   0x00000b6c

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK   0x80000000

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON   0x1

◆ COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET

#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET   31

◆ COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK

#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ COMBPHY0_CLK_REG_FACTOR_M_OFFSET

#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET   0

◆ COMBPHY1_CLK_REG

#define COMBPHY1_CLK_REG   0x00000b70

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK   0x80000000

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON   0x1

◆ COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET

#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET   31

◆ COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK

#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ COMBPHY1_CLK_REG_FACTOR_M_OFFSET

#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET   0

◆ CPU_CLK_REG

#define CPU_CLK_REG   0x00000500

◆ CPU_CLK_REG_CPU_APB_DIV_CFG_CLEAR_MASK

#define CPU_CLK_REG_CPU_APB_DIV_CFG_CLEAR_MASK   0x00000300

◆ CPU_CLK_REG_CPU_APB_DIV_CFG_OFFSET

#define CPU_CLK_REG_CPU_APB_DIV_CFG_OFFSET   8

◆ CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK

#define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK   0x00000003

◆ CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET

#define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET   0

◆ CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK

#define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK   0x07000000

◆ CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC

#define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC   0x010

◆ CPU_CLK_REG_CPU_CLK_SEL_CLK32K

#define CPU_CLK_REG_CPU_CLK_SEL_CLK32K   0x001

◆ CPU_CLK_REG_CPU_CLK_SEL_CPU0PLL_P

#define CPU_CLK_REG_CPU_CLK_SEL_CPU0PLL_P   0x011

◆ CPU_CLK_REG_CPU_CLK_SEL_CPU2PLL

#define CPU_CLK_REG_CPU_CLK_SEL_CPU2PLL   0x101

◆ CPU_CLK_REG_CPU_CLK_SEL_HOSC

#define CPU_CLK_REG_CPU_CLK_SEL_HOSC   0x000

◆ CPU_CLK_REG_CPU_CLK_SEL_OFFSET

#define CPU_CLK_REG_CPU_CLK_SEL_OFFSET   24

◆ CPU_CLK_REG_CPU_CLK_SEL_PERI0_600M

#define CPU_CLK_REG_CPU_CLK_SEL_PERI0_600M   0x100

◆ CPU_CLK_REG_CPU_PERI_DIV_CFG__M__FACTOR_M1__1

#define CPU_CLK_REG_CPU_PERI_DIV_CFG__M__FACTOR_M1__1   0x1

◆ CPU_CLK_REG_CPU_PERI_DIV_CFG_CLEAR_MASK

#define CPU_CLK_REG_CPU_PERI_DIV_CFG_CLEAR_MASK   0x0000000c

◆ CPU_CLK_REG_CPU_PERI_DIV_CFG_OFFSET

#define CPU_CLK_REG_CPU_PERI_DIV_CFG_OFFSET   2

◆ CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_1

#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_1   0x00

◆ CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_2

#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_2   0x01

◆ CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_4

#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_4   0x10

◆ CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_CLEAR_MASK

#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_CLEAR_MASK   0x00030000

◆ CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_OFFSET

#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_OFFSET   16

◆ CPU_GATING_REG

#define CPU_GATING_REG   0x00000504

◆ CPU_GATING_REG_CPU0_CLK_GATING_CLEAR_MASK

#define CPU_GATING_REG_CPU0_CLK_GATING_CLEAR_MASK   0x00000001

◆ CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_OFF

#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_ON

#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_ON   0x1

◆ CPU_GATING_REG_CPU0_CLK_GATING_OFFSET

#define CPU_GATING_REG_CPU0_CLK_GATING_OFFSET   0

◆ CPU_GATING_REG_CPU_GATING_FIELD_0_SIGNAL

#define CPU_GATING_REG_CPU_GATING_FIELD_0_SIGNAL   0x15

◆ CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK

#define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK   0xffff0000

◆ CPU_GATING_REG_CPU_GATING_FIELD_OFFSET

#define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET   16

◆ CPU_GATING_REG_DSU_CLK_GATING_CLEAR_MASK

#define CPU_GATING_REG_DSU_CLK_GATING_CLEAR_MASK   0x00000002

◆ CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_OFF

#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_ON

#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_ON   0x1

◆ CPU_GATING_REG_DSU_CLK_GATING_OFFSET

#define CPU_GATING_REG_DSU_CLK_GATING_OFFSET   1

◆ CSI_BGR_REG

#define CSI_BGR_REG   0x00000c1c

◆ CSI_BGR_REG_CSI_GATING_CLEAR_MASK

#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK   0x00000001

◆ CSI_BGR_REG_CSI_GATING_MASK

#define CSI_BGR_REG_CSI_GATING_MASK   0x0

◆ CSI_BGR_REG_CSI_GATING_OFFSET

#define CSI_BGR_REG_CSI_GATING_OFFSET   0

◆ CSI_BGR_REG_CSI_GATING_PASS

#define CSI_BGR_REG_CSI_GATING_PASS   0x1

◆ CSI_BGR_REG_CSI_RST_ASSERT

#define CSI_BGR_REG_CSI_RST_ASSERT   0x0

◆ CSI_BGR_REG_CSI_RST_CLEAR_MASK

#define CSI_BGR_REG_CSI_RST_CLEAR_MASK   0x00010000

◆ CSI_BGR_REG_CSI_RST_DE_ASSERT

#define CSI_BGR_REG_CSI_RST_DE_ASSERT   0x1

◆ CSI_BGR_REG_CSI_RST_OFFSET

#define CSI_BGR_REG_CSI_RST_OFFSET   16

◆ CSI_CLK_REG

#define CSI_CLK_REG   0x00000c04

◆ CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x010

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x011

◆ CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x100

◆ CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK

#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON

#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON   0x1

◆ CSI_CLK_REG_CSI_CLK_GATING_OFFSET

#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET   31

◆ CSI_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_CLK_REG_FACTOR_M_OFFSET

#define CSI_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG

#define CSI_MASTER0_CLK_REG   0x00000c08

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100

◆ CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON   0x1

◆ CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET

#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET   31

◆ CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER1_CLK_REG

#define CSI_MASTER1_CLK_REG   0x00000c0c

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100

◆ CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON   0x1

◆ CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET

#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET   31

◆ CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER2_CLK_REG

#define CSI_MASTER2_CLK_REG   0x00000c10

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100

◆ CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON   0x1

◆ CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET

#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET   31

◆ CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET   8

◆ CSI_MASTER3_CLK_REG

#define CSI_MASTER3_CLK_REG   0x00000c14

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100

◆ CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x001

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK   0x80000000

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF   0x0

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON   0x1

◆ CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET

#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET   31

◆ CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET

#define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET   0

◆ CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK

#define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET

#define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET   8

◆ DBGSYS_BGR_REG

#define DBGSYS_BGR_REG   0x0000078c

◆ DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK   0x00000001

◆ DBGSYS_BGR_REG_DBGSYS_GATING_MASK

#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK   0x0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET   0

◆ DBGSYS_BGR_REG_DBGSYS_GATING_PASS

#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS   0x1

◆ DBGSYS_BGR_REG_DBGSYS_RST_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT   0x0

◆ DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK

#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK   0x00010000

◆ DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT

#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT   0x1

◆ DBGSYS_BGR_REG_DBGSYS_RST_OFFSET

#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET   16

◆ DE0_CLK_REG

#define DE0_CLK_REG   0x00000600

◆ DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DE0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000

◆ DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x011

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x100

◆ DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x101

◆ DE0_CLK_REG_DE_CLK_GATING_CLEAR_MASK

#define DE0_CLK_REG_DE_CLK_GATING_CLEAR_MASK   0x80000000

◆ DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF

#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON

#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON   0x1

◆ DE0_CLK_REG_DE_CLK_GATING_OFFSET

#define DE0_CLK_REG_DE_CLK_GATING_OFFSET   31

◆ DE0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DE0_CLK_REG_FACTOR_M_OFFSET

#define DE0_CLK_REG_FACTOR_M_OFFSET   0

◆ DE_BGR_REG

#define DE_BGR_REG   0x0000060c

◆ DE_BGR_REG_DE0_GATING_CLEAR_MASK

#define DE_BGR_REG_DE0_GATING_CLEAR_MASK   0x00000001

◆ DE_BGR_REG_DE0_GATING_MASK

#define DE_BGR_REG_DE0_GATING_MASK   0x0

◆ DE_BGR_REG_DE0_GATING_OFFSET

#define DE_BGR_REG_DE0_GATING_OFFSET   0

◆ DE_BGR_REG_DE0_GATING_PASS

#define DE_BGR_REG_DE0_GATING_PASS   0x1

◆ DE_BGR_REG_DE0_RST_ASSERT

#define DE_BGR_REG_DE0_RST_ASSERT   0x0

◆ DE_BGR_REG_DE0_RST_CLEAR_MASK

#define DE_BGR_REG_DE0_RST_CLEAR_MASK   0x00010000

◆ DE_BGR_REG_DE0_RST_DE_ASSERT

#define DE_BGR_REG_DE0_RST_DE_ASSERT   0x1

◆ DE_BGR_REG_DE0_RST_OFFSET

#define DE_BGR_REG_DE0_RST_OFFSET   16

◆ DI_BGR_REG

#define DI_BGR_REG   0x0000062c

◆ DI_BGR_REG_DI_GATING_CLEAR_MASK

#define DI_BGR_REG_DI_GATING_CLEAR_MASK   0x00000001

◆ DI_BGR_REG_DI_GATING_MASK

#define DI_BGR_REG_DI_GATING_MASK   0x0

◆ DI_BGR_REG_DI_GATING_OFFSET

#define DI_BGR_REG_DI_GATING_OFFSET   0

◆ DI_BGR_REG_DI_GATING_PASS

#define DI_BGR_REG_DI_GATING_PASS   0x1

◆ DI_BGR_REG_DI_RST_ASSERT

#define DI_BGR_REG_DI_RST_ASSERT   0x0

◆ DI_BGR_REG_DI_RST_CLEAR_MASK

#define DI_BGR_REG_DI_RST_CLEAR_MASK   0x00010000

◆ DI_BGR_REG_DI_RST_DE_ASSERT

#define DI_BGR_REG_DI_RST_DE_ASSERT   0x1

◆ DI_BGR_REG_DI_RST_OFFSET

#define DI_BGR_REG_DI_RST_OFFSET   16

◆ DI_CLK_REG

#define DI_CLK_REG   0x00000620

◆ DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DI_CLK_REG_CLK_SRC_SEL_OFFSET

#define DI_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DI_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x000

◆ DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK

#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK   0x80000000

◆ DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON

#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON   0x1

◆ DI_CLK_REG_DI_CLK_GATING_OFFSET

#define DI_CLK_REG_DI_CLK_GATING_OFFSET   31

◆ DI_CLK_REG_FACTOR_M_CLEAR_MASK

#define DI_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DI_CLK_REG_FACTOR_M_OFFSET

#define DI_CLK_REG_FACTOR_M_OFFSET   0

◆ DMA_BGR_REG

#define DMA_BGR_REG   0x0000070c

◆ DMA_BGR_REG_DMA_GATING_CLEAR_MASK

#define DMA_BGR_REG_DMA_GATING_CLEAR_MASK   0x00000001

◆ DMA_BGR_REG_DMA_GATING_MASK

#define DMA_BGR_REG_DMA_GATING_MASK   0x0

◆ DMA_BGR_REG_DMA_GATING_OFFSET

#define DMA_BGR_REG_DMA_GATING_OFFSET   0

◆ DMA_BGR_REG_DMA_GATING_PASS

#define DMA_BGR_REG_DMA_GATING_PASS   0x1

◆ DMA_BGR_REG_DMA_RST_ASSERT

#define DMA_BGR_REG_DMA_RST_ASSERT   0x0

◆ DMA_BGR_REG_DMA_RST_CLEAR_MASK

#define DMA_BGR_REG_DMA_RST_CLEAR_MASK   0x00010000

◆ DMA_BGR_REG_DMA_RST_DE_ASSERT

#define DMA_BGR_REG_DMA_RST_DE_ASSERT   0x1

◆ DMA_BGR_REG_DMA_RST_OFFSET

#define DMA_BGR_REG_DMA_RST_OFFSET   16

◆ DMA_GATING_BASE

#define DMA_GATING_BASE   CCU_DMA_BGR_REG

◆ DMA_GATING_BIT

#define DMA_GATING_BIT   (0)

◆ DMA_GATING_PASS

#define DMA_GATING_PASS   (1)

◆ DPSS_TOP0_BGR_REG

#define DPSS_TOP0_BGR_REG   0x00000abc

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK   0x00000001

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK   0x0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET   0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS   0x1

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT   0x0

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK   0x00010000

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT   0x1

◆ DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET

#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET   16

◆ DPSS_TOP1_BGR_REG

#define DPSS_TOP1_BGR_REG   0x00000acc

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK   0x00000001

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK   0x0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET   0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS   0x1

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT   0x0

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK   0x00010000

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT   0x1

◆ DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET

#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET   16

◆ DRAM_BGR_REG

#define DRAM_BGR_REG   0x0000080c

◆ DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK   0x00000001

◆ DRAM_BGR_REG_DRAM_GATING_MASK

#define DRAM_BGR_REG_DRAM_GATING_MASK   0x0

◆ DRAM_BGR_REG_DRAM_GATING_OFFSET

#define DRAM_BGR_REG_DRAM_GATING_OFFSET   0

◆ DRAM_BGR_REG_DRAM_GATING_PASS

#define DRAM_BGR_REG_DRAM_GATING_PASS   0x1

◆ DRAM_BGR_REG_DRAM_RST_ASSERT

#define DRAM_BGR_REG_DRAM_RST_ASSERT   0x0

◆ DRAM_BGR_REG_DRAM_RST_CLEAR_MASK

#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK   0x00010000

◆ DRAM_BGR_REG_DRAM_RST_DE_ASSERT

#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT   0x1

◆ DRAM_BGR_REG_DRAM_RST_OFFSET

#define DRAM_BGR_REG_DRAM_RST_OFFSET   16

◆ DRAM_CLK_REG

#define DRAM_CLK_REG   0x00000800

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK   0x80000000

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON

#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON   0x1

◆ DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET   31

◆ DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK   0x07000000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL

#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL   0x000

◆ DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET

#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET   24

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_150M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_150M   0x100

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_400M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_400M   0x011

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M   0x010

◆ DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M

#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M   0x001

◆ DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK   0x0000001f

◆ DRAM_CLK_REG_DRAM_DIV1_OFFSET

#define DRAM_CLK_REG_DRAM_DIV1_OFFSET   0

◆ DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK

#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK   0x08000000

◆ DRAM_CLK_REG_DRAM_UPD_INVALID

#define DRAM_CLK_REG_DRAM_UPD_INVALID   0x0

◆ DRAM_CLK_REG_DRAM_UPD_OFFSET

#define DRAM_CLK_REG_DRAM_UPD_OFFSET   27

◆ DRAM_CLK_REG_DRAM_UPD_VALID

#define DRAM_CLK_REG_DRAM_UPD_VALID   0x1

◆ DSI0_CLK_REG

#define DSI0_CLK_REG   0x00000b24

◆ DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DSI0_CLK_REG_CLK_SRC_SEL_HOSC

#define DSI0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ DSI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M   0x010

◆ DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK   0x80000000

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON

#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON   0x1

◆ DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET

#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET   31

◆ DSI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DSI0_CLK_REG_FACTOR_M_OFFSET

#define DSI0_CLK_REG_FACTOR_M_OFFSET   0

◆ DSI1_CLK_REG

#define DSI1_CLK_REG   0x00000b28

◆ DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DSI1_CLK_REG_CLK_SRC_SEL_HOSC

#define DSI1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ DSI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M   0x010

◆ DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK   0x80000000

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON

#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON   0x1

◆ DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET

#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET   31

◆ DSI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DSI1_CLK_REG_FACTOR_M_OFFSET

#define DSI1_CLK_REG_FACTOR_M_OFFSET   0

◆ DSI_BGR_REG

#define DSI_BGR_REG   0x00000b4c

◆ DSI_BGR_REG_DSI0_GATING_CLEAR_MASK

#define DSI_BGR_REG_DSI0_GATING_CLEAR_MASK   0x00000001

◆ DSI_BGR_REG_DSI0_GATING_MASK

#define DSI_BGR_REG_DSI0_GATING_MASK   0x0

◆ DSI_BGR_REG_DSI0_GATING_OFFSET

#define DSI_BGR_REG_DSI0_GATING_OFFSET   0

◆ DSI_BGR_REG_DSI0_GATING_PASS

#define DSI_BGR_REG_DSI0_GATING_PASS   0x1

◆ DSI_BGR_REG_DSI0_RST_ASSERT

#define DSI_BGR_REG_DSI0_RST_ASSERT   0x0

◆ DSI_BGR_REG_DSI0_RST_CLEAR_MASK

#define DSI_BGR_REG_DSI0_RST_CLEAR_MASK   0x00010000

◆ DSI_BGR_REG_DSI0_RST_DE_ASSERT

#define DSI_BGR_REG_DSI0_RST_DE_ASSERT   0x1

◆ DSI_BGR_REG_DSI0_RST_OFFSET

#define DSI_BGR_REG_DSI0_RST_OFFSET   16

◆ DSI_BGR_REG_DSI1_GATING_CLEAR_MASK

#define DSI_BGR_REG_DSI1_GATING_CLEAR_MASK   0x00000002

◆ DSI_BGR_REG_DSI1_GATING_MASK

#define DSI_BGR_REG_DSI1_GATING_MASK   0x0

◆ DSI_BGR_REG_DSI1_GATING_OFFSET

#define DSI_BGR_REG_DSI1_GATING_OFFSET   1

◆ DSI_BGR_REG_DSI1_GATING_PASS

#define DSI_BGR_REG_DSI1_GATING_PASS   0x1

◆ DSI_BGR_REG_DSI1_RST_ASSERT

#define DSI_BGR_REG_DSI1_RST_ASSERT   0x0

◆ DSI_BGR_REG_DSI1_RST_CLEAR_MASK

#define DSI_BGR_REG_DSI1_RST_CLEAR_MASK   0x00020000

◆ DSI_BGR_REG_DSI1_RST_DE_ASSERT

#define DSI_BGR_REG_DSI1_RST_DE_ASSERT   0x1

◆ DSI_BGR_REG_DSI1_RST_OFFSET

#define DSI_BGR_REG_DSI1_RST_OFFSET   17

◆ DSP_CLK_REG

#define DSP_CLK_REG   0x00000c70

◆ DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x010

◆ DSP_CLK_REG_CLK_SRC_SEL_CLK32K

#define DSP_CLK_REG_CLK_SRC_SEL_CLK32K   0x001

◆ DSP_CLK_REG_CLK_SRC_SEL_HOSC

#define DSP_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ DSP_CLK_REG_CLK_SRC_SEL_OFFSET

#define DSP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x100

◆ DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x011

◆ DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK

#define DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK   0x80000000

◆ DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF

#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF   0x0

◆ DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON

#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON   0x1

◆ DSP_CLK_REG_DSP_CLK_GATING_OFFSET

#define DSP_CLK_REG_DSP_CLK_GATING_OFFSET   31

◆ DSP_CLK_REG_FACTOR_M_CLEAR_MASK

#define DSP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ DSP_CLK_REG_FACTOR_M_OFFSET

#define DSP_CLK_REG_FACTOR_M_OFFSET   0

◆ DSU_CLK_REG

#define DSU_CLK_REG   0x0000050c

◆ DSU_CLK_REG_DSU_CLK_SEL_CLEAR_MASK

#define DSU_CLK_REG_DSU_CLK_SEL_CLEAR_MASK   0x07000000

◆ DSU_CLK_REG_DSU_CLK_SEL_CLK16M_RC

#define DSU_CLK_REG_DSU_CLK_SEL_CLK16M_RC   0x010

◆ DSU_CLK_REG_DSU_CLK_SEL_CLK32K

#define DSU_CLK_REG_DSU_CLK_SEL_CLK32K   0x001

◆ DSU_CLK_REG_DSU_CLK_SEL_CPU1PLL_P

#define DSU_CLK_REG_DSU_CLK_SEL_CPU1PLL_P   0x011

◆ DSU_CLK_REG_DSU_CLK_SEL_HOSC

#define DSU_CLK_REG_DSU_CLK_SEL_HOSC   0x000

◆ DSU_CLK_REG_DSU_CLK_SEL_OFFSET

#define DSU_CLK_REG_DSU_CLK_SEL_OFFSET   24

◆ DSU_CLK_REG_DSU_CLK_SEL_PERI0_600M

#define DSU_CLK_REG_DSU_CLK_SEL_PERI0_600M   0x101

◆ DSU_CLK_REG_DSU_CLK_SEL_PERI0PLL2X

#define DSU_CLK_REG_DSU_CLK_SEL_PERI0PLL2X   0x100

◆ DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_1

#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_1   0x00

◆ DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_2

#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_2   0x01

◆ DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_4

#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_4   0x10

◆ DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_CLEAR_MASK

#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_CLEAR_MASK   0x00030000

◆ DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_OFFSET

#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_OFFSET   16

◆ G2D_BGR_REG

#define G2D_BGR_REG   0x0000063c

◆ G2D_BGR_REG_G2D_GATING_CLEAR_MASK

#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK   0x00000001

◆ G2D_BGR_REG_G2D_GATING_MASK

#define G2D_BGR_REG_G2D_GATING_MASK   0x0

◆ G2D_BGR_REG_G2D_GATING_OFFSET

#define G2D_BGR_REG_G2D_GATING_OFFSET   0

◆ G2D_BGR_REG_G2D_GATING_PASS

#define G2D_BGR_REG_G2D_GATING_PASS   0x1

◆ G2D_BGR_REG_G2D_RST_ASSERT

#define G2D_BGR_REG_G2D_RST_ASSERT   0x0

◆ G2D_BGR_REG_G2D_RST_CLEAR_MASK

#define G2D_BGR_REG_G2D_RST_CLEAR_MASK   0x00010000

◆ G2D_BGR_REG_G2D_RST_DE_ASSERT

#define G2D_BGR_REG_G2D_RST_DE_ASSERT   0x1

◆ G2D_BGR_REG_G2D_RST_OFFSET

#define G2D_BGR_REG_G2D_RST_OFFSET   16

◆ G2D_CLK_REG

#define G2D_CLK_REG   0x00000630

◆ G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ G2D_CLK_REG_CLK_SRC_SEL_OFFSET

#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001

◆ G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x000

◆ G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ G2D_CLK_REG_FACTOR_M_CLEAR_MASK

#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ G2D_CLK_REG_FACTOR_M_OFFSET

#define G2D_CLK_REG_FACTOR_M_OFFSET   0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK

#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK   0x80000000

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF   0x0

◆ G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON

#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON   0x1

◆ G2D_CLK_REG_G2D_CLK_GATING_OFFSET

#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET   31

◆ GATING_SHIFT

#define GATING_SHIFT   (0)

◆ GET_SPIF_CLK_SOURECS

#define GET_SPIF_CLK_SOURECS (   x)    (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)

◆ GIC_CLK_REG

#define GIC_CLK_REG   0x00000550

◆ GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x03000000

◆ GIC_CLK_REG_CLK_SRC_SEL_CLK32K

#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K   0x001

◆ GIC_CLK_REG_CLK_SRC_SEL_HOSC

#define GIC_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ GIC_CLK_REG_CLK_SRC_SEL_OFFSET

#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x011

◆ GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010

◆ GIC_CLK_REG_FACTOR_M_CLEAR_MASK

#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ GIC_CLK_REG_FACTOR_M_OFFSET

#define GIC_CLK_REG_FACTOR_M_OFFSET   0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK

#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK   0x80000000

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF   0x0

◆ GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON

#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON   0x1

◆ GIC_CLK_REG_GIC_CLK_GATING_OFFSET

#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET   31

◆ GMAC0_25M_CLK_REG

#define GMAC0_25M_CLK_REG   0x00000970

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLEAR_MASK

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLEAR_MASK   0x80000000

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_OFF

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_OFF   0x0

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_ON

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_ON   0x1

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_OFFSET

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_OFFSET   31

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLEAR_MASK

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_OFF

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0x0

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_ON

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_ON   0x1

◆ GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_OFFSET

#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_OFFSET   30

◆ GMAC1_25M_CLK_REG

#define GMAC1_25M_CLK_REG   0x00000974

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLEAR_MASK

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLEAR_MASK   0x80000000

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_OFF

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_OFF   0x0

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_ON

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_ON   0x1

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_OFFSET

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_OFFSET   31

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLEAR_MASK

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLEAR_MASK   0x40000000

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_OFF

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_OFF   0x0

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_ON

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_ON   0x1

◆ GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_OFFSET

#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_OFFSET   30

◆ GMAC_BGR_REG

#define GMAC_BGR_REG   0x0000097c

◆ GMAC_BGR_REG_GMAC0_GATING_CLEAR_MASK

#define GMAC_BGR_REG_GMAC0_GATING_CLEAR_MASK   0x00000001

◆ GMAC_BGR_REG_GMAC0_GATING_MASK

#define GMAC_BGR_REG_GMAC0_GATING_MASK   0x0

◆ GMAC_BGR_REG_GMAC0_GATING_OFFSET

#define GMAC_BGR_REG_GMAC0_GATING_OFFSET   0

◆ GMAC_BGR_REG_GMAC0_GATING_PASS

#define GMAC_BGR_REG_GMAC0_GATING_PASS   0x1

◆ GMAC_BGR_REG_GMAC0_RST_ASSERT

#define GMAC_BGR_REG_GMAC0_RST_ASSERT   0x0

◆ GMAC_BGR_REG_GMAC0_RST_CLEAR_MASK

#define GMAC_BGR_REG_GMAC0_RST_CLEAR_MASK   0x00010000

◆ GMAC_BGR_REG_GMAC0_RST_DE_ASSERT

#define GMAC_BGR_REG_GMAC0_RST_DE_ASSERT   0x1

◆ GMAC_BGR_REG_GMAC0_RST_OFFSET

#define GMAC_BGR_REG_GMAC0_RST_OFFSET   16

◆ GMAC_BGR_REG_GMAC1_GATING_CLEAR_MASK

#define GMAC_BGR_REG_GMAC1_GATING_CLEAR_MASK   0x00000002

◆ GMAC_BGR_REG_GMAC1_GATING_MASKS

#define GMAC_BGR_REG_GMAC1_GATING_MASKS   0x0

◆ GMAC_BGR_REG_GMAC1_GATING_OFFSET

#define GMAC_BGR_REG_GMAC1_GATING_OFFSET   1

◆ GMAC_BGR_REG_GMAC1_GATING_PASS

#define GMAC_BGR_REG_GMAC1_GATING_PASS   0x1

◆ GMAC_BGR_REG_GMAC1_RST_ASSERT

#define GMAC_BGR_REG_GMAC1_RST_ASSERT   0x0

◆ GMAC_BGR_REG_GMAC1_RST_CLEAR_MASK

#define GMAC_BGR_REG_GMAC1_RST_CLEAR_MASK   0x00020000

◆ GMAC_BGR_REG_GMAC1_RST_DE_ASSERT

#define GMAC_BGR_REG_GMAC1_RST_DE_ASSERT   0x1

◆ GMAC_BGR_REG_GMAC1_RST_OFFSET

#define GMAC_BGR_REG_GMAC1_RST_OFFSET   17

◆ GPADC_24M_CLK_REG

#define GPADC_24M_CLK_REG   0x000009e0

◆ GPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ GPADC_24M_CLK_REG_FACTOR_M_OFFSET

#define GPADC_24M_CLK_REG_FACTOR_M_OFFSET   0

◆ GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLEAR_MASK

#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLEAR_MASK   0x80000000

◆ GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_OFF

#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_OFF   0x0

◆ GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_ON

#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_ON   0x1

◆ GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_OFFSET

#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_OFFSET   31

◆ GPADC_BGR_REG

#define GPADC_BGR_REG   0x000009ec

◆ GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK

#define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK   0x00000001

◆ GPADC_BGR_REG_GPADC_GATING_MASK

#define GPADC_BGR_REG_GPADC_GATING_MASK   0x0

◆ GPADC_BGR_REG_GPADC_GATING_OFFSET

#define GPADC_BGR_REG_GPADC_GATING_OFFSET   0

◆ GPADC_BGR_REG_GPADC_GATING_PASS

#define GPADC_BGR_REG_GPADC_GATING_PASS   0x1

◆ GPADC_BGR_REG_GPADC_RST_ASSERT

#define GPADC_BGR_REG_GPADC_RST_ASSERT   0x0

◆ GPADC_BGR_REG_GPADC_RST_CLEAR_MASK

#define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK   0x00010000

◆ GPADC_BGR_REG_GPADC_RST_DE_ASSERT

#define GPADC_BGR_REG_GPADC_RST_DE_ASSERT   0x1

◆ GPADC_BGR_REG_GPADC_RST_OFFSET

#define GPADC_BGR_REG_GPADC_RST_OFFSET   16

◆ GPU_CORE_CLK_REG

#define GPU_CORE_CLK_REG   0x00000670

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_GPUPLL

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_GPUPLL   0x000

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_OFFSET

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x101

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x100

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x011

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010

◆ GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x001

◆ GPU_CORE_CLK_REG_FACTOR_M_CLEAR_MASK

#define GPU_CORE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000000f

◆ GPU_CORE_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES

#define GPU_CORE_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES   0x001

◆ GPU_CORE_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES

#define GPU_CORE_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES   0x010

◆ GPU_CORE_CLK_REG_FACTOR_M_NOT_MASK

#define GPU_CORE_CLK_REG_FACTOR_M_NOT_MASK   0x000

◆ GPU_CORE_CLK_REG_FACTOR_M_OFFSET

#define GPU_CORE_CLK_REG_FACTOR_M_OFFSET   0

◆ GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLEAR_MASK

#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLEAR_MASK   0x80000000

◆ GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_OFF

#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_OFF   0x0

◆ GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_ON

#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_ON   0x1

◆ GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_OFFSET

#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_OFFSET   31

◆ GPU_GATING_REG

#define GPU_GATING_REG   0x0000067c

◆ GPU_GATING_REG_GPU_GATING_CLEAR_MASK

#define GPU_GATING_REG_GPU_GATING_CLEAR_MASK   0x00000001

◆ GPU_GATING_REG_GPU_GATING_MASK

#define GPU_GATING_REG_GPU_GATING_MASK   0x0

◆ GPU_GATING_REG_GPU_GATING_OFFSET

#define GPU_GATING_REG_GPU_GATING_OFFSET   0

◆ GPU_GATING_REG_GPU_GATING_PASS

#define GPU_GATING_REG_GPU_GATING_PASS   0x1

◆ GPU_GATING_REG_GPU_RST_ASSERT

#define GPU_GATING_REG_GPU_RST_ASSERT   0x0

◆ GPU_GATING_REG_GPU_RST_CLEAR_MASK

#define GPU_GATING_REG_GPU_RST_CLEAR_MASK   0x00010000

◆ GPU_GATING_REG_GPU_RST_DE_ASSERT

#define GPU_GATING_REG_GPU_RST_DE_ASSERT   0x1

◆ GPU_GATING_REG_GPU_RST_OFFSET

#define GPU_GATING_REG_GPU_RST_OFFSET   16

◆ HDMI_24M_CLK_REG

#define HDMI_24M_CLK_REG   0x00000b04

◆ HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLEAR_MASK

#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLEAR_MASK   0x80000000

◆ HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_OFF

#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_OFF   0x0

◆ HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_ON

#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_ON   0x1

◆ HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_OFFSET

#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_OFFSET   31

◆ HDMI_BGR_REG

#define HDMI_BGR_REG   0x00000b1c

◆ HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK   0x00000001

◆ HDMI_BGR_REG_HDMI_GATING_MASK

#define HDMI_BGR_REG_HDMI_GATING_MASK   0x0

◆ HDMI_BGR_REG_HDMI_GATING_OFFSET

#define HDMI_BGR_REG_HDMI_GATING_OFFSET   0

◆ HDMI_BGR_REG_HDMI_GATING_PASS

#define HDMI_BGR_REG_HDMI_GATING_PASS   0x1

◆ HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT

#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT   0x0

◆ HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK   0x00010000

◆ HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT

#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT   0x1

◆ HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET

#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET   16

◆ HDMI_BGR_REG_HDMI_SUB_RST_ASSERT

#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT   0x0

◆ HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK

#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK   0x00020000

◆ HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT

#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT   0x1

◆ HDMI_BGR_REG_HDMI_SUB_RST_OFFSET

#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET   17

◆ HDMI_CEC_CLK_REG

#define HDMI_CEC_CLK_REG   0x00000b10

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K   0x0

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K__PLL_PERI_2X__36621___32_768KHZ

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K__PLL_PERI_2X__36621___32_768KHZ   0x1

◆ HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET

#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK   0x80000000

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF   0x0

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON   0x1

◆ HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET

#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET   31

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK

#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK   0x40000000

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF   0x0

◆ HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON

#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON   0x1

◆ HDMI_CEC_CLK_REG_PERI_GATING_OFFSET

#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET   30

◆ IOMMU_AUTO_GATING_REG

#define IOMMU_AUTO_GATING_REG   (SUNXI_IOMMU_BASE + 0X40)

◆ IOMMU_BGR_REG

#define IOMMU_BGR_REG   0x000007bc

◆ IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK

#define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK   0x00000001

◆ IOMMU_BGR_REG_IOMMU_GATING_MASK

#define IOMMU_BGR_REG_IOMMU_GATING_MASK   0x0

◆ IOMMU_BGR_REG_IOMMU_GATING_OFFSET

#define IOMMU_BGR_REG_IOMMU_GATING_OFFSET   0

◆ IOMMU_BGR_REG_IOMMU_GATING_PASS

#define IOMMU_BGR_REG_IOMMU_GATING_PASS   0x1

◆ IRRX_BGR_REG

#define IRRX_BGR_REG   0x0000099c

◆ IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK

#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK   0x00000001

◆ IRRX_BGR_REG_IRRX_GATING_MASK

#define IRRX_BGR_REG_IRRX_GATING_MASK   0x0

◆ IRRX_BGR_REG_IRRX_GATING_OFFSET

#define IRRX_BGR_REG_IRRX_GATING_OFFSET   0

◆ IRRX_BGR_REG_IRRX_GATING_PASS

#define IRRX_BGR_REG_IRRX_GATING_PASS   0x1

◆ IRRX_BGR_REG_IRRX_RST_ASSERT

#define IRRX_BGR_REG_IRRX_RST_ASSERT   0x0

◆ IRRX_BGR_REG_IRRX_RST_CLEAR_MASK

#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK   0x00010000

◆ IRRX_BGR_REG_IRRX_RST_DE_ASSERT

#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT   0x1

◆ IRRX_BGR_REG_IRRX_RST_OFFSET

#define IRRX_BGR_REG_IRRX_RST_OFFSET   16

◆ IRRX_CLK_REG

#define IRRX_CLK_REG   0x00000990

◆ IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ IRRX_CLK_REG_CLK_SRC_SEL_CLK32K

#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K   0x0

◆ IRRX_CLK_REG_CLK_SRC_SEL_HOSC

#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC   0x1

◆ IRRX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IRRX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ IRRX_CLK_REG_FACTOR_M_OFFSET

#define IRRX_CLK_REG_FACTOR_M_OFFSET   0

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK   0x80000000

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF   0x0

◆ IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON

#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON   0x1

◆ IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET

#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET   31

◆ IRTX_BGR_REG

#define IRTX_BGR_REG   0x000009cc

◆ IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK   0x00000001

◆ IRTX_BGR_REG_IRTX_GATING_MASK

#define IRTX_BGR_REG_IRTX_GATING_MASK   0x0

◆ IRTX_BGR_REG_IRTX_GATING_OFFSET

#define IRTX_BGR_REG_IRTX_GATING_OFFSET   0

◆ IRTX_BGR_REG_IRTX_GATING_PASS

#define IRTX_BGR_REG_IRTX_GATING_PASS   0x1

◆ IRTX_BGR_REG_IRTX_RST_ASSERT

#define IRTX_BGR_REG_IRTX_RST_ASSERT   0x0

◆ IRTX_BGR_REG_IRTX_RST_CLEAR_MASK

#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK   0x00010000

◆ IRTX_BGR_REG_IRTX_RST_DE_ASSERT

#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT   0x1

◆ IRTX_BGR_REG_IRTX_RST_OFFSET

#define IRTX_BGR_REG_IRTX_RST_OFFSET   16

◆ IRTX_CLK_REG

#define IRTX_CLK_REG   0x000009c0

◆ IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ IRTX_CLK_REG_CLK_SRC_SEL_HOSC

#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC   0x0

◆ IRTX_CLK_REG_CLK_SRC_SEL_OFFSET

#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M   0x1

◆ IRTX_CLK_REG_FACTOR_M_CLEAR_MASK

#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ IRTX_CLK_REG_FACTOR_M_OFFSET

#define IRTX_CLK_REG_FACTOR_M_OFFSET   0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK   0x80000000

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF   0x0

◆ IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON

#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON   0x1

◆ IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET

#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET   31

◆ ISP_BGR_REG

#define ISP_BGR_REG   0x00000c2c

◆ ISP_BGR_REG_ISP_RST_ASSERT

#define ISP_BGR_REG_ISP_RST_ASSERT   0x0

◆ ISP_BGR_REG_ISP_RST_CLEAR_MASK

#define ISP_BGR_REG_ISP_RST_CLEAR_MASK   0x00010000

◆ ISP_BGR_REG_ISP_RST_DE_ASSERT

#define ISP_BGR_REG_ISP_RST_DE_ASSERT   0x1

◆ ISP_BGR_REG_ISP_RST_OFFSET

#define ISP_BGR_REG_ISP_RST_OFFSET   16

◆ ISP_CLK_REG

#define ISP_CLK_REG   0x00000c20

◆ ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ ISP_CLK_REG_CLK_SRC_SEL_OFFSET

#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x000

◆ ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x010

◆ ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ ISP_CLK_REG_FACTOR_M_CLEAR_MASK

#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ ISP_CLK_REG_FACTOR_M_OFFSET

#define ISP_CLK_REG_FACTOR_M_OFFSET   0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK

#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK   0x80000000

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF   0x0

◆ ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON

#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON   0x1

◆ ISP_CLK_REG_ISP_CLK_GATING_OFFSET

#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET   31

◆ LEDC_BGR_REG

#define LEDC_BGR_REG   0x00000bfc

◆ LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK   0x00000001

◆ LEDC_BGR_REG_LEDC_GATING_MASK

#define LEDC_BGR_REG_LEDC_GATING_MASK   0x0

◆ LEDC_BGR_REG_LEDC_GATING_OFFSET

#define LEDC_BGR_REG_LEDC_GATING_OFFSET   0

◆ LEDC_BGR_REG_LEDC_GATING_PASS

#define LEDC_BGR_REG_LEDC_GATING_PASS   0x1

◆ LEDC_BGR_REG_LEDC_RST_ASSERT

#define LEDC_BGR_REG_LEDC_RST_ASSERT   0x0

◆ LEDC_BGR_REG_LEDC_RST_CLEAR_MASK

#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK   0x00010000

◆ LEDC_BGR_REG_LEDC_RST_DE_ASSERT

#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT   0x1

◆ LEDC_BGR_REG_LEDC_RST_OFFSET

#define LEDC_BGR_REG_LEDC_RST_OFFSET   16

◆ LEDC_CLK_REG

#define LEDC_CLK_REG   0x00000bf0

◆ LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ LEDC_CLK_REG_CLK_SRC_SEL_HOSC

#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ LEDC_CLK_REG_CLK_SRC_SEL_OFFSET

#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x001

◆ LEDC_CLK_REG_FACTOR_M_CLEAR_MASK

#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ LEDC_CLK_REG_FACTOR_M_OFFSET

#define LEDC_CLK_REG_FACTOR_M_OFFSET   0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK   0x80000000

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF   0x0

◆ LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON

#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON   0x1

◆ LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET

#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET   31

◆ LRADC_BGR_REG

#define LRADC_BGR_REG   0x00000a9c

◆ LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK   0x00000001

◆ LRADC_BGR_REG_LRADC_GATING_MASK

#define LRADC_BGR_REG_LRADC_GATING_MASK   0x0

◆ LRADC_BGR_REG_LRADC_GATING_OFFSET

#define LRADC_BGR_REG_LRADC_GATING_OFFSET   0

◆ LRADC_BGR_REG_LRADC_GATING_PASS

#define LRADC_BGR_REG_LRADC_GATING_PASS   0x1

◆ LRADC_BGR_REG_LRADC_RST_ASSERT

#define LRADC_BGR_REG_LRADC_RST_ASSERT   0x0

◆ LRADC_BGR_REG_LRADC_RST_CLEAR_MASK

#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK   0x00010000

◆ LRADC_BGR_REG_LRADC_RST_DE_ASSERT

#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT   0x1

◆ LRADC_BGR_REG_LRADC_RST_OFFSET

#define LRADC_BGR_REG_LRADC_RST_OFFSET   16

◆ LVDS_BGR_REG

#define LVDS_BGR_REG   0x00000bac

◆ LVDS_BGR_REG_LVDS0_RST_ASSERT

#define LVDS_BGR_REG_LVDS0_RST_ASSERT   0x0

◆ LVDS_BGR_REG_LVDS0_RST_CLEAR_MASK

#define LVDS_BGR_REG_LVDS0_RST_CLEAR_MASK   0x00010000

◆ LVDS_BGR_REG_LVDS0_RST_DE_ASSERT

#define LVDS_BGR_REG_LVDS0_RST_DE_ASSERT   0x1

◆ LVDS_BGR_REG_LVDS0_RST_OFFSET

#define LVDS_BGR_REG_LVDS0_RST_OFFSET   16

◆ LVDS_BGR_REG_LVDS1_RST_ASSERT

#define LVDS_BGR_REG_LVDS1_RST_ASSERT   0x0

◆ LVDS_BGR_REG_LVDS1_RST_CLEAR_MASK

#define LVDS_BGR_REG_LVDS1_RST_CLEAR_MASK   0x00020000

◆ LVDS_BGR_REG_LVDS1_RST_DE_ASSERT

#define LVDS_BGR_REG_LVDS1_RST_DE_ASSERT   0x1

◆ LVDS_BGR_REG_LVDS1_RST_OFFSET

#define LVDS_BGR_REG_LVDS1_RST_OFFSET   17

◆ MBUS_CLK_REG

#define MBUS_CLK_REG   0x00000540

◆ MBUS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define MBUS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ MBUS_CLK_REG_CLK_SRC_SEL_DDRPLL

#define MBUS_CLK_REG_CLK_SRC_SEL_DDRPLL   0x001

◆ MBUS_CLK_REG_CLK_SRC_SEL_HOSC

#define MBUS_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ MBUS_CLK_REG_CLK_SRC_SEL_OFFSET

#define MBUS_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ MBUS_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x100

◆ MBUS_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x011

◆ MBUS_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010

◆ MBUS_CLK_REG_FACTOR_M_CLEAR_MASK

#define MBUS_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ MBUS_CLK_REG_FACTOR_M_OFFSET

#define MBUS_CLK_REG_FACTOR_M_OFFSET   0

◆ MBUS_CLK_REG_MBUS_RST_ASSERT

#define MBUS_CLK_REG_MBUS_RST_ASSERT   0x0

◆ MBUS_CLK_REG_MBUS_RST_CLEAR_MASK

#define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK   0x40000000

◆ MBUS_CLK_REG_MBUS_RST_DE_ASSERT

#define MBUS_CLK_REG_MBUS_RST_DE_ASSERT   0x1

◆ MBUS_CLK_REG_MBUS_RST_OFFSET

#define MBUS_CLK_REG_MBUS_RST_OFFSET   30

◆ MBUS_CLK_REG_SCLK_GATING_CLEAR_MASK

#define MBUS_CLK_REG_SCLK_GATING_CLEAR_MASK   0x80000000

◆ MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_OFF

#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_OFF   0x0

◆ MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_ON

#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_ON   0x1

◆ MBUS_CLK_REG_SCLK_GATING_OFFSET

#define MBUS_CLK_REG_SCLK_GATING_OFFSET   31

◆ MBUS_MAT_CLK_GATING_REG

#define MBUS_MAT_CLK_GATING_REG   0x00000804

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00040000

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET   18

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK   0x00000004

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET   2

◆ MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK   0x00000100

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET   8

◆ MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET   16

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK   0x00000001

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET   0

◆ MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK   0x00000200

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET   9

◆ MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET   22

◆ MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK   0x00000020

◆ MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET   5

◆ MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00200000

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET   21

◆ MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_CLEAR_MASK   0x00000040

◆ MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_OFFSET   6

◆ MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET   17

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK   0x00000002

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK   0x0

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET   1

◆ MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS

#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS   0x1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET   20

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE   0x0

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE   0x1

◆ MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET

#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET   19

◆ MSGBOX_BGR_REG

#define MSGBOX_BGR_REG   0x0000071c

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK   0x00000001

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_MASK

#define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK   0x0

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET

#define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET   0

◆ MSGBOX_BGR_REG_MSGBOX0_GATING_PASS

#define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS   0x1

◆ MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT

#define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT   0x0

◆ MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK   0x00010000

◆ MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT

#define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT   0x1

◆ MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET

#define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET   16

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK   0x00000002

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_MASK

#define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK   0x0

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET

#define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET   1

◆ MSGBOX_BGR_REG_MSGBOX1_GATING_PASS

#define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS   0x1

◆ MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT

#define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT   0x0

◆ MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK

#define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK   0x00020000

◆ MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT

#define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT   0x1

◆ MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET

#define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET   17

◆ NAND0_CLK0_CLK_REG

#define NAND0_CLK0_CLK_REG   0x00000810

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100

◆ NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011

◆ NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET   0

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK   0x80000000

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON   0x1

◆ NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET

#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET   31

◆ NAND0_CLK1_CLK_REG

#define NAND0_CLK1_CLK_REG   0x00000814

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100

◆ NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011

◆ NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET

#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET   0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK   0x80000000

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON   0x1

◆ NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET

#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET   31

◆ NAND_BGR_REG

#define NAND_BGR_REG   0x0000082c

◆ NAND_BGR_REG_NAND0_GATING_CLEAR_MASK

#define NAND_BGR_REG_NAND0_GATING_CLEAR_MASK   0x00000001

◆ NAND_BGR_REG_NAND0_GATING_MASK

#define NAND_BGR_REG_NAND0_GATING_MASK   0x0

◆ NAND_BGR_REG_NAND0_GATING_OFFSET

#define NAND_BGR_REG_NAND0_GATING_OFFSET   0

◆ NAND_BGR_REG_NAND0_GATING_PASS

#define NAND_BGR_REG_NAND0_GATING_PASS   0x1

◆ NAND_BGR_REG_NAND0_RST_ASSERT

#define NAND_BGR_REG_NAND0_RST_ASSERT   0x0

◆ NAND_BGR_REG_NAND0_RST_CLEAR_MASK

#define NAND_BGR_REG_NAND0_RST_CLEAR_MASK   0x00010000

◆ NAND_BGR_REG_NAND0_RST_DE_ASSERT

#define NAND_BGR_REG_NAND0_RST_DE_ASSERT   0x1

◆ NAND_BGR_REG_NAND0_RST_OFFSET

#define NAND_BGR_REG_NAND0_RST_OFFSET   16

◆ NPU_CLK_REG

#define NPU_CLK_REG   0x000006e0

◆ NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X

#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X   0x011

◆ NPU_CLK_REG_CLK_SRC_SEL_OFFSET

#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x000

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x001

◆ NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x010

◆ NPU_CLK_REG_FACTOR_M_CLEAR_MASK

#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ NPU_CLK_REG_FACTOR_M_OFFSET

#define NPU_CLK_REG_FACTOR_M_OFFSET   0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK

#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK   0x80000000

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF   0x0

◆ NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON

#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON   0x1

◆ NPU_CLK_REG_NPU_CLK_GATING_OFFSET

#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET   31

◆ NSI_BGR_REG

#define NSI_BGR_REG   0x0000054c

◆ NSI_BGR_REG_NSI_GATING_CLEAR_MASK

#define NSI_BGR_REG_NSI_GATING_CLEAR_MASK   0x00000001

◆ NSI_BGR_REG_NSI_GATING_MASK

#define NSI_BGR_REG_NSI_GATING_MASK   0x0

◆ NSI_BGR_REG_NSI_GATING_OFFSET

#define NSI_BGR_REG_NSI_GATING_OFFSET   0

◆ NSI_BGR_REG_NSI_GATING_PASS

#define NSI_BGR_REG_NSI_GATING_PASS   0x1

◆ NSI_BGR_REG_NSI_RST_ASSERT

#define NSI_BGR_REG_NSI_RST_ASSERT   0x0

◆ NSI_BGR_REG_NSI_RST_CLEAR_MASK

#define NSI_BGR_REG_NSI_RST_CLEAR_MASK   0x00010000

◆ NSI_BGR_REG_NSI_RST_DE_ASSERT

#define NSI_BGR_REG_NSI_RST_DE_ASSERT   0x1

◆ NSI_BGR_REG_NSI_RST_OFFSET

#define NSI_BGR_REG_NSI_RST_OFFSET   16

◆ PCIE_AUX_CLK_REG

#define PCIE_AUX_CLK_REG   0x00000aa0

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x01000000

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K   0x1

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC   0x0

◆ PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET

#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK

#define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ PCIE_AUX_CLK_REG_FACTOR_M_OFFSET

#define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET   0

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK   0x80000000

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF   0x0

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON   0x1

◆ PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET

#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET   31

◆ PCIE_BGR_REG

#define PCIE_BGR_REG   0x00000aac

◆ PCIE_BGR_REG_PCIE_GATING_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_GATING_CLEAR_MASK   0x00000001

◆ PCIE_BGR_REG_PCIE_GATING_MASK

#define PCIE_BGR_REG_PCIE_GATING_MASK   0x0

◆ PCIE_BGR_REG_PCIE_GATING_OFFSET

#define PCIE_BGR_REG_PCIE_GATING_OFFSET   0

◆ PCIE_BGR_REG_PCIE_GATING_PASS

#define PCIE_BGR_REG_PCIE_GATING_PASS   0x1

◆ PCIE_BGR_REG_PCIE_PE_RST_ASSERT

#define PCIE_BGR_REG_PCIE_PE_RST_ASSERT   0x0

◆ PCIE_BGR_REG_PCIE_PE_RST_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_PE_RST_CLEAR_MASK   0x00040000

◆ PCIE_BGR_REG_PCIE_PE_RST_DE_ASSERT

#define PCIE_BGR_REG_PCIE_PE_RST_DE_ASSERT   0x1

◆ PCIE_BGR_REG_PCIE_PE_RST_OFFSET

#define PCIE_BGR_REG_PCIE_PE_RST_OFFSET   18

◆ PCIE_BGR_REG_PCIE_POWER_UP_RST_ASSERT

#define PCIE_BGR_REG_PCIE_POWER_UP_RST_ASSERT   0x0

◆ PCIE_BGR_REG_PCIE_POWER_UP_RST_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_POWER_UP_RST_CLEAR_MASK   0x00020000

◆ PCIE_BGR_REG_PCIE_POWER_UP_RST_DE_ASSERT

#define PCIE_BGR_REG_PCIE_POWER_UP_RST_DE_ASSERT   0x1

◆ PCIE_BGR_REG_PCIE_POWER_UP_RST_OFFSET

#define PCIE_BGR_REG_PCIE_POWER_UP_RST_OFFSET   17

◆ PCIE_BGR_REG_PCIE_RST_ASSERT

#define PCIE_BGR_REG_PCIE_RST_ASSERT   0x0

◆ PCIE_BGR_REG_PCIE_RST_CLEAR_MASK

#define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK   0x00010000

◆ PCIE_BGR_REG_PCIE_RST_DE_ASSERT

#define PCIE_BGR_REG_PCIE_RST_DE_ASSERT   0x1

◆ PCIE_BGR_REG_PCIE_RST_OFFSET

#define PCIE_BGR_REG_PCIE_RST_OFFSET   16

◆ PCIE_REF_CLK_REG

#define PCIE_REF_CLK_REG   0x00000aa4

◆ PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLEAR_MASK

#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLEAR_MASK   0x80000000

◆ PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_OFF

#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_OFF   0x0

◆ PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_ON

#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_ON   0x1

◆ PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_OFFSET

#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_OFFSET   31

◆ PERI0PLL_GATE_EN_REG

#define PERI0PLL_GATE_EN_REG   0x00000e08

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK   0x00000008

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET   3

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK   0x00080000

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET   19

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK   0x00000040

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET   6

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK   0x00400000

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET   22

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK   0x00000001

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET   0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK   0x00010000

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET   16

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000020

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET   5

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK   0x00000010

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET   4

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK   0x00200000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET   21

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK   0x00100000

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET   20

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000004

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET   2

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK   0x00000002

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET   1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK   0x00040000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET   18

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK   0x00020000

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET   17

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK   0x00000100

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET   8

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK   0x00000080

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET   7

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK   0x01000000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET   24

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK   0x00800000

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET   23

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK   0x00000200

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET   9

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK   0x02000000

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET   25

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK   0x00000400

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET   10

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK   0x04000000

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET   26

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK   0x00000800

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET   11

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK   0x08000000

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE   0x0

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE   0x1

◆ PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET

#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET   27

◆ PLL_AUDIO_BIAS_REG

#define PLL_AUDIO_BIAS_REG   0x00000378

◆ PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET

#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_AUDIO_CTRL_REG

#define PLL_AUDIO_CTRL_REG   0x00000078

◆ PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_AUDIO_CTRL_REG_LOCK_OFFSET

#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET   28

◆ PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED

#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_AUDIO_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_AUDIO_CTRL_REG_PLL_N_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_AUDIO_CTRL_REG_PLL_P_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_P_CLEAR_MASK   0x003f0000

◆ PLL_AUDIO_CTRL_REG_PLL_P_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_P_OFFSET   16

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_AUDIO_PAT0_CTRL_REG

#define PLL_AUDIO_PAT0_CTRL_REG   0x00000178

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_AUDIO_PAT1_CTRL_REG

#define PLL_AUDIO_PAT1_CTRL_REG   0x0000017c

◆ PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_CFG0_REG

#define PLL_CFG0_REG   0x00000f40

◆ PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK

#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK   0xffffffff

◆ PLL_CFG0_REG_PLL_CONFIG0_OFFSET

#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET   0

◆ PLL_CFG1_REG

#define PLL_CFG1_REG   0x00000f44

◆ PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK

#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK   0xffffffff

◆ PLL_CFG1_REG_PLL_CONFIG1_OFFSET

#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET   0

◆ PLL_CFG2_REG

#define PLL_CFG2_REG   0x00000f48

◆ PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK

#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK   0xffffffff

◆ PLL_CFG2_REG_PLL_CONFIG2_OFFSET

#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET   0

◆ PLL_CPU0_BIAS_REG

#define PLL_CPU0_BIAS_REG   0x00000300

◆ PLL_CPU0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_CPU0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_CPU0_BIAS_REG_PLL_CP_OFFSET

#define PLL_CPU0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK

#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000

◆ PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_OFFSET

#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31

◆ PLL_CPU0_CTRL_REG

#define PLL_CPU0_CTRL_REG   0x00000000

◆ PLL_CPU0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CPU0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_CPU0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_CPU0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_CPU0_CTRL_REG_LOCK_OFFSET

#define PLL_CPU0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CPU0_CTRL_REG_LOCK_UNLOCKED

#define PLL_CPU0_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_CPU0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU0_CTRL_REG_PLL_EN_DISABLE

#define PLL_CPU0_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_CPU0_CTRL_REG_PLL_EN_ENABLE

#define PLL_CPU0_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_CPU0_CTRL_REG_PLL_EN_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CPU0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_CPU0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_CPU0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000

◆ PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_OFFSET   24

◆ PLL_CPU0_CTRL_REG_PLL_M_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003

◆ PLL_CPU0_CTRL_REG_PLL_M_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_M_OFFSET   0

◆ PLL_CPU0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_CPU0_CTRL_REG_PLL_N_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_CPU0_TUN_REG

#define PLL_CPU0_TUN_REG   0x00000400

◆ PLL_CPU0_TUN_REG_PLL_B_IN_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00

◆ PLL_CPU0_TUN_REG_PLL_B_IN_OFFSET

#define PLL_CPU0_TUN_REG_PLL_B_IN_OFFSET   8

◆ PLL_CPU0_TUN_REG_PLL_B_OUT_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f

◆ PLL_CPU0_TUN_REG_PLL_B_OUT_OFFSET

#define PLL_CPU0_TUN_REG_PLL_B_OUT_OFFSET   0

◆ PLL_CPU0_TUN_REG_PLL_CNT_INT_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000

◆ PLL_CPU0_TUN_REG_PLL_CNT_INT_OFFSET

#define PLL_CPU0_TUN_REG_PLL_CNT_INT_OFFSET   16

◆ PLL_CPU0_TUN_REG_PLL_REG_OD1_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080

◆ PLL_CPU0_TUN_REG_PLL_REG_OD1_OFFSET

#define PLL_CPU0_TUN_REG_PLL_REG_OD1_OFFSET   7

◆ PLL_CPU0_TUN_REG_PLL_REG_OD_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000

◆ PLL_CPU0_TUN_REG_PLL_REG_OD_OFFSET

#define PLL_CPU0_TUN_REG_PLL_REG_OD_OFFSET   15

◆ PLL_CPU0_TUN_REG_PLL_VCO_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000

◆ PLL_CPU0_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK

#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000

◆ PLL_CPU0_TUN_REG_PLL_VCO_GAIN_OFFSET

#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_OFFSET   24

◆ PLL_CPU0_TUN_REG_PLL_VCO_OFFSET

#define PLL_CPU0_TUN_REG_PLL_VCO_OFFSET   28

◆ PLL_CPU1_BIAS_REG

#define PLL_CPU1_BIAS_REG   0x00000308

◆ PLL_CPU1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_CPU1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_CPU1_BIAS_REG_PLL_CP_OFFSET

#define PLL_CPU1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK

#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000

◆ PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_OFFSET

#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31

◆ PLL_CPU1_CTRL_REG

#define PLL_CPU1_CTRL_REG   0x00000004

◆ PLL_CPU1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CPU1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CPU1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_CPU1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_CPU1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CPU1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_CPU1_CTRL_REG_LOCK_OFFSET

#define PLL_CPU1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CPU1_CTRL_REG_LOCK_UNLOCKED

#define PLL_CPU1_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_CPU1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU1_CTRL_REG_PLL_EN_DISABLE

#define PLL_CPU1_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_CPU1_CTRL_REG_PLL_EN_ENABLE

#define PLL_CPU1_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_CPU1_CTRL_REG_PLL_EN_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CPU1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CPU1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_CPU1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_CPU1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000

◆ PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_OFFSET   24

◆ PLL_CPU1_CTRL_REG_PLL_M_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003

◆ PLL_CPU1_CTRL_REG_PLL_M_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_M_OFFSET   0

◆ PLL_CPU1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_CPU1_CTRL_REG_PLL_N_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_CPU1_TUN_REG

#define PLL_CPU1_TUN_REG   0x00000408

◆ PLL_CPU1_TUN_REG_PLL_B_IN_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00

◆ PLL_CPU1_TUN_REG_PLL_B_IN_OFFSET

#define PLL_CPU1_TUN_REG_PLL_B_IN_OFFSET   8

◆ PLL_CPU1_TUN_REG_PLL_B_OUT_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f

◆ PLL_CPU1_TUN_REG_PLL_B_OUT_OFFSET

#define PLL_CPU1_TUN_REG_PLL_B_OUT_OFFSET   0

◆ PLL_CPU1_TUN_REG_PLL_CNT_INT_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000

◆ PLL_CPU1_TUN_REG_PLL_CNT_INT_OFFSET

#define PLL_CPU1_TUN_REG_PLL_CNT_INT_OFFSET   16

◆ PLL_CPU1_TUN_REG_PLL_REG_OD1_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080

◆ PLL_CPU1_TUN_REG_PLL_REG_OD1_OFFSET

#define PLL_CPU1_TUN_REG_PLL_REG_OD1_OFFSET   7

◆ PLL_CPU1_TUN_REG_PLL_REG_OD_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000

◆ PLL_CPU1_TUN_REG_PLL_REG_OD_OFFSET

#define PLL_CPU1_TUN_REG_PLL_REG_OD_OFFSET   15

◆ PLL_CPU1_TUN_REG_PLL_VCO_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000

◆ PLL_CPU1_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK

#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000

◆ PLL_CPU1_TUN_REG_PLL_VCO_GAIN_OFFSET

#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_OFFSET   24

◆ PLL_CPU1_TUN_REG_PLL_VCO_OFFSET

#define PLL_CPU1_TUN_REG_PLL_VCO_OFFSET   28

◆ PLL_CPU2_BIAS_REG

#define PLL_CPU2_BIAS_REG   0x0000030c

◆ PLL_CPU2_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_CPU2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_CPU2_BIAS_REG_PLL_CP_OFFSET

#define PLL_CPU2_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK

#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK   0x80000000

◆ PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_OFFSET

#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_OFFSET   31

◆ PLL_CPU2_CTRL_REG

#define PLL_CPU2_CTRL_REG   0x00000008

◆ PLL_CPU2_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CPU2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CPU2_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_CPU2_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_CPU2_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CPU2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_CPU2_CTRL_REG_LOCK_OFFSET

#define PLL_CPU2_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CPU2_CTRL_REG_LOCK_UNLOCKED

#define PLL_CPU2_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_CPU2_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU2_CTRL_REG_PLL_EN_DISABLE

#define PLL_CPU2_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_CPU2_CTRL_REG_PLL_EN_ENABLE

#define PLL_CPU2_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_CPU2_CTRL_REG_PLL_EN_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CPU2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CPU2_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_CPU2_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_CPU2_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000

◆ PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_OFFSET   24

◆ PLL_CPU2_CTRL_REG_PLL_M_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_M_CLEAR_MASK   0x00000003

◆ PLL_CPU2_CTRL_REG_PLL_M_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_M_OFFSET   0

◆ PLL_CPU2_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_CPU2_CTRL_REG_PLL_N_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_CPU2_TUN_REG

#define PLL_CPU2_TUN_REG   0x0000040c

◆ PLL_CPU2_TUN_REG_PLL_B_IN_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_B_IN_CLEAR_MASK   0x00007f00

◆ PLL_CPU2_TUN_REG_PLL_B_IN_OFFSET

#define PLL_CPU2_TUN_REG_PLL_B_IN_OFFSET   8

◆ PLL_CPU2_TUN_REG_PLL_B_OUT_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_B_OUT_CLEAR_MASK   0x0000007f

◆ PLL_CPU2_TUN_REG_PLL_B_OUT_OFFSET

#define PLL_CPU2_TUN_REG_PLL_B_OUT_OFFSET   0

◆ PLL_CPU2_TUN_REG_PLL_CNT_INT_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_CNT_INT_CLEAR_MASK   0x007f0000

◆ PLL_CPU2_TUN_REG_PLL_CNT_INT_OFFSET

#define PLL_CPU2_TUN_REG_PLL_CNT_INT_OFFSET   16

◆ PLL_CPU2_TUN_REG_PLL_REG_OD1_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_REG_OD1_CLEAR_MASK   0x00000080

◆ PLL_CPU2_TUN_REG_PLL_REG_OD1_OFFSET

#define PLL_CPU2_TUN_REG_PLL_REG_OD1_OFFSET   7

◆ PLL_CPU2_TUN_REG_PLL_REG_OD_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_REG_OD_CLEAR_MASK   0x00008000

◆ PLL_CPU2_TUN_REG_PLL_REG_OD_OFFSET

#define PLL_CPU2_TUN_REG_PLL_REG_OD_OFFSET   15

◆ PLL_CPU2_TUN_REG_PLL_VCO_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_VCO_CLEAR_MASK   0x70000000

◆ PLL_CPU2_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK

#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK   0x07000000

◆ PLL_CPU2_TUN_REG_PLL_VCO_GAIN_OFFSET

#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_OFFSET   24

◆ PLL_CPU2_TUN_REG_PLL_VCO_OFFSET

#define PLL_CPU2_TUN_REG_PLL_VCO_OFFSET   28

◆ PLL_CPU3_CTRL_REG

#define PLL_CPU3_CTRL_REG   0x00000008

◆ PLL_CPU3_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_CPU3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_CPU3_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_CPU3_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_CPU3_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_CPU3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_CPU3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_CPU3_CTRL_REG_LOCK_OFFSET

#define PLL_CPU3_CTRL_REG_LOCK_OFFSET   28

◆ PLL_CPU3_CTRL_REG_LOCK_UNLOCKED

#define PLL_CPU3_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_CPU3_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_CPU3_CTRL_REG_PLL_EN_DISABLE

#define PLL_CPU3_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_CPU3_CTRL_REG_PLL_EN_ENABLE

#define PLL_CPU3_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_CPU3_CTRL_REG_PLL_EN_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_CPU3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_CPU3_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_CPU3_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_CPU3_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK   0x07000000

◆ PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_OFFSET   24

◆ PLL_CPU3_CTRL_REG_PLL_M_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_M_OFFSET   0

◆ PLL_CPU3_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_CPU3_CTRL_REG_PLL_N_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_DDR_BIAS_REG

#define PLL_DDR_BIAS_REG   0x00000310

◆ PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_DDR_BIAS_REG_PLL_CP_OFFSET

#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_DDR_CTRL_REG

#define PLL_DDR_CTRL_REG   0x00000010

◆ PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_DDR_CTRL_REG_LOCK_OFFSET

#define PLL_DDR_CTRL_REG_LOCK_OFFSET   28

◆ PLL_DDR_CTRL_REG_LOCK_UNLOCKED

#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_DDR_CTRL_REG_PLL_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_DDR_CTRL_REG_PLL_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_DDR_CTRL_REG_PLL_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_DDR_CTRL_REG_PLL_N_OFFSET

#define PLL_DDR_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_DDR_PAT0_CTRL_REG

#define PLL_DDR_PAT0_CTRL_REG   0x00000110

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG

#define PLL_DDR_PAT1_CTRL_REG   0x00000114

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_GPU_BIAS_REG

#define PLL_GPU_BIAS_REG   0x00000330

◆ PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_GPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_GPU_CTRL_REG

#define PLL_GPU_CTRL_REG   0x00000030

◆ PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_GPU_CTRL_REG_LOCK_OFFSET

#define PLL_GPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_GPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_GPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_GPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_GPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_GPU_CTRL_REG_PLL_N_OFFSET

#define PLL_GPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_GPU_PAT0_CTRL_REG

#define PLL_GPU_PAT0_CTRL_REG   0x00000130

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_GPU_PAT1_CTRL_REG

#define PLL_GPU_PAT1_CTRL_REG   0x00000134

◆ PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_LOCK_DBG_CTRL_REG

#define PLL_LOCK_DBG_CTRL_REG   0x00000f04

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK   0x80000000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE   0x0

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE   0x1

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET   31

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIOPLL4X

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIOPLL4X   0x110

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK   0x00700000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPUPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPUPLL   0x000

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CSIPLL4X

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CSIPLL4X   0x100

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL   0x001

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL   0x111

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET   20

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERIPLL2X

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERIPLL2X   0x010

◆ PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL4X

#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL4X   0x011

◆ PLL_NPU_BIAS_REG

#define PLL_NPU_BIAS_REG   0x00000380

◆ PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_NPU_BIAS_REG_PLL_CP_OFFSET

#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_NPU_CTRL_REG

#define PLL_NPU_CTRL_REG   0x00000080

◆ PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_NPU_CTRL_REG_LOCK_OFFSET

#define PLL_NPU_CTRL_REG_LOCK_OFFSET   28

◆ PLL_NPU_CTRL_REG_LOCK_UNLOCKED

#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_NPU_CTRL_REG_PLL_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_NPU_CTRL_REG_PLL_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_NPU_CTRL_REG_PLL_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_NPU_CTRL_REG_PLL_N_OFFSET

#define PLL_NPU_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_NPU_PAT0_CTRL_REG

#define PLL_NPU_PAT0_CTRL_REG   0x00000180

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG

#define PLL_NPU_PAT1_CTRL_REG   0x00000184

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PERI0_BIAS_REG

#define PLL_PERI0_BIAS_REG   0x00000320

◆ PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_PERI0_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI0_CTRL_REG

#define PLL_PERI0_CTRL_REG   0x00000020

◆ PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_PERI0_CTRL_REG_LOCK_OFFSET

#define PLL_PERI0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI0_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI0_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_PERI0_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_PERI0_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_PERI0_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_PERI0_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_PERI0_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_PERI0_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI0_PAT0_CTRL_REG

#define PLL_PERI0_PAT0_CTRL_REG   0x00000120

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG

#define PLL_PERI0_PAT1_CTRL_REG   0x00000124

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_PERI1_BIAS_REG

#define PLL_PERI1_BIAS_REG   0x00000328

◆ PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_PERI1_BIAS_REG_PLL_CP_OFFSET

#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_PERI1_CTRL_REG

#define PLL_PERI1_CTRL_REG   0x00000028

◆ PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_PERI1_CTRL_REG_LOCK_OFFSET

#define PLL_PERI1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_PERI1_CTRL_REG_LOCK_UNLOCKED

#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI1_CTRL_REG_PLL_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_PERI1_CTRL_REG_PLL_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_PERI1_CTRL_REG_PLL_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_PERI1_CTRL_REG_PLL_N_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK   0x00070000

◆ PLL_PERI1_CTRL_REG_PLL_P0_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET   16

◆ PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK   0x00700000

◆ PLL_PERI1_CTRL_REG_PLL_P1_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET   20

◆ PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK   0x0000001c

◆ PLL_PERI1_CTRL_REG_PLL_P2_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET   2

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_PERI1_PAT0_CTRL_REG

#define PLL_PERI1_PAT0_CTRL_REG   0x00000128

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG

#define PLL_PERI1_PAT1_CTRL_REG   0x0000012c

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VE_BIAS_REG

#define PLL_VE_BIAS_REG   0x00000358

◆ PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VE_BIAS_REG_PLL_CP_OFFSET

#define PLL_VE_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VE_CTRL_REG

#define PLL_VE_CTRL_REG   0x00000058

◆ PLL_VE_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_VE_CTRL_REG_LOCK_OFFSET

#define PLL_VE_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VE_CTRL_REG_LOCK_UNLOCKED

#define PLL_VE_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VE_CTRL_REG_PLL_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_VE_CTRL_REG_PLL_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_VE_CTRL_REG_PLL_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VE_CTRL_REG_PLL_N_OFFSET

#define PLL_VE_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VE_PAT0_CTRL_REG

#define PLL_VE_PAT0_CTRL_REG   0x00000158

◆ PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VE_PAT1_CTRL_REG

#define PLL_VE_PAT1_CTRL_REG   0x0000015c

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO0_BIAS_REG

#define PLL_VIDEO0_BIAS_REG   0x00000340

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO0_CTRL_REG

#define PLL_VIDEO0_CTRL_REG   0x00000040

◆ PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO0_PAT0_CTRL_REG

#define PLL_VIDEO0_PAT0_CTRL_REG   0x00000140

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG

#define PLL_VIDEO0_PAT1_CTRL_REG   0x00000144

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO1_BIAS_REG

#define PLL_VIDEO1_BIAS_REG   0x00000348

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO1_CTRL_REG

#define PLL_VIDEO1_CTRL_REG   0x00000048

◆ PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO1_PAT0_CTRL_REG

#define PLL_VIDEO1_PAT0_CTRL_REG   0x00000148

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG

#define PLL_VIDEO1_PAT1_CTRL_REG   0x0000014c

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO2_BIAS_REG

#define PLL_VIDEO2_BIAS_REG   0x00000350

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO2_CTRL_REG

#define PLL_VIDEO2_CTRL_REG   0x00000050

◆ PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO2_PAT0_CTRL_REG

#define PLL_VIDEO2_PAT0_CTRL_REG   0x00000150

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG

#define PLL_VIDEO2_PAT1_CTRL_REG   0x00000154

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PLL_VIDEO3_BIAS_REG

#define PLL_VIDEO3_BIAS_REG   0x00000368

◆ PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK

#define PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK   0x001f0000

◆ PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET

#define PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET   16

◆ PLL_VIDEO3_CTRL_REG

#define PLL_VIDEO3_CTRL_REG   0x00000068

◆ PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK   0x10000000

◆ PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK   0x20000000

◆ PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE

#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE   0x0

◆ PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE

#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET

#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET   29

◆ PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE

#define PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_LOCK_OFFSET

#define PLL_VIDEO3_CTRL_REG_LOCK_OFFSET   28

◆ PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED

#define PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE

#define PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE

#define PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET   31

◆ PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK   0x00000002

◆ PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_OFFSET   1

◆ PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK   0x40000000

◆ PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE

#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE

#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET   30

◆ PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES

#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES   0x1

◆ PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES

#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK   0x00000020

◆ PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET   5

◆ PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK   0x0000ff00

◆ PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET   8

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK   0x00000001

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET   0

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK   0x08000000

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET   27

◆ PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_DISABLE

#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_DISABLE   0x0

◆ PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_ENABLE

#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_ENABLE   0x1

◆ PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_OFFSET   24

◆ PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES

#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES   0x10

◆ PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES

#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES   0x00

◆ PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES

#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES   0x01

◆ PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK

#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK   0x000000c0

◆ PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET

#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET   6

◆ PLL_VIDEO3_PAT0_CTRL_REG

#define PLL_VIDEO3_PAT0_CTRL_REG   0x00000168

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ   0x00

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ   0x10

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ   0x01

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ   0x11

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK   0x00060000

◆ PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET   17

◆ PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ   0x1

◆ PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ

#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ   0x0

◆ PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK   0x00080000

◆ PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET   19

◆ PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK   0x80000000

◆ PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET   31

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK   0x60000000

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0   0x00

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1   0x01

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET   29

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT   0x10

◆ PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT

#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT   0x11

◆ PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET   0

◆ PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK

#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK   0x1ff00000

◆ PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET

#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET   20

◆ PLL_VIDEO3_PAT1_CTRL_REG

#define PLL_VIDEO3_PAT1_CTRL_REG   0x0000016c

◆ PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK

#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK   0x01000000

◆ PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET

#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET   24

◆ PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK

#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK   0x00100000

◆ PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET

#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET   20

◆ PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK

#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK   0x0001ffff

◆ PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET

#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET   0

◆ PWM_BGR_REG

#define PWM_BGR_REG   0x000007ac

◆ PWM_BGR_REG_PWM_GATING_CLEAR_MASK

#define PWM_BGR_REG_PWM_GATING_CLEAR_MASK   0x00000001

◆ PWM_BGR_REG_PWM_GATING_MASK

#define PWM_BGR_REG_PWM_GATING_MASK   0x0

◆ PWM_BGR_REG_PWM_GATING_OFFSET

#define PWM_BGR_REG_PWM_GATING_OFFSET   0

◆ PWM_BGR_REG_PWM_GATING_PASS

#define PWM_BGR_REG_PWM_GATING_PASS   0x1

◆ PWM_BGR_REG_PWM_RST_ASSERT

#define PWM_BGR_REG_PWM_RST_ASSERT   0x0

◆ PWM_BGR_REG_PWM_RST_CLEAR_MASK

#define PWM_BGR_REG_PWM_RST_CLEAR_MASK   0x00010000

◆ PWM_BGR_REG_PWM_RST_DE_ASSERT

#define PWM_BGR_REG_PWM_RST_DE_ASSERT   0x1

◆ PWM_BGR_REG_PWM_RST_OFFSET

#define PWM_BGR_REG_PWM_RST_OFFSET   16

◆ RESET_SHIFT

#define RESET_SHIFT   (16)

◆ RISCV_APB_DB_RST

#define RISCV_APB_DB_RST   (0x1 << 17)

◆ RISCV_CFG_BASE

#define RISCV_CFG_BASE   (0x07130000)

◆ RISCV_CFG_BGR_REG

#define RISCV_CFG_BGR_REG   (SUNXI_DSP_PRCM_BASE + 0x0124)

◆ RISCV_CFG_GATING

#define RISCV_CFG_GATING   (0x1 << 0)

◆ RISCV_CFG_RST

#define RISCV_CFG_RST   (0x1 << 16)

◆ RISCV_CLK_GATING

#define RISCV_CLK_GATING   (0x1 << 31)

◆ RISCV_CLK_REG

#define RISCV_CLK_REG   (SUNXI_DSP_PRCM_BASE + 0x0120)

◆ RISCV_CORE_RST

#define RISCV_CORE_RST   (0x1 << 18)

◆ RISCV_PUBSRAM_CFG_REG

#define RISCV_PUBSRAM_CFG_REG   (SUNXI_DSP_PRCM_BASE + 0x0114)

◆ RISCV_PUBSRAM_GATING

#define RISCV_PUBSRAM_GATING   (0x1 << 0)

◆ RISCV_PUBSRAM_RST

#define RISCV_PUBSRAM_RST   (0x1 << 16)

◆ RISCV_STA_ADD_REG

#define RISCV_STA_ADD_REG   (RISCV_CFG_BASE + 0x0204)

◆ SMHC0_CLK_REG

#define SMHC0_CLK_REG   0x00000830

◆ SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100

◆ SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011

◆ SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC0_CLK_REG_FACTOR_M_OFFSET

#define SMHC0_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC0_CLK_REG_FACTOR_N_OFFSET

#define SMHC0_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON   0x1

◆ SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET

#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET   31

◆ SMHC1_CLK_REG

#define SMHC1_CLK_REG   0x00000834

◆ SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x001

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100

◆ SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M

#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M   0x011

◆ SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC1_CLK_REG_FACTOR_M_OFFSET

#define SMHC1_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC1_CLK_REG_FACTOR_N_OFFSET

#define SMHC1_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON   0x1

◆ SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET

#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET   31

◆ SMHC2_CLK_REG

#define SMHC2_CLK_REG   0x00000838

◆ SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_HOSC

#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M   0x010

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M   0x001

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M   0x100

◆ SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M

#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M   0x011

◆ SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SMHC2_CLK_REG_FACTOR_M_OFFSET

#define SMHC2_CLK_REG_FACTOR_M_OFFSET   0

◆ SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK

#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SMHC2_CLK_REG_FACTOR_N_OFFSET

#define SMHC2_CLK_REG_FACTOR_N_OFFSET   8

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON   0x1

◆ SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET

#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET   31

◆ SMHC_BGR_REG

#define SMHC_BGR_REG   0x0000084c

◆ SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK   0x00000001

◆ SMHC_BGR_REG_SMHC0_GATING_MASK

#define SMHC_BGR_REG_SMHC0_GATING_MASK   0x0

◆ SMHC_BGR_REG_SMHC0_GATING_OFFSET

#define SMHC_BGR_REG_SMHC0_GATING_OFFSET   0

◆ SMHC_BGR_REG_SMHC0_GATING_PASS

#define SMHC_BGR_REG_SMHC0_GATING_PASS   0x1

◆ SMHC_BGR_REG_SMHC0_RST_ASSERT

#define SMHC_BGR_REG_SMHC0_RST_ASSERT   0x0

◆ SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK   0x00010000

◆ SMHC_BGR_REG_SMHC0_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT   0x1

◆ SMHC_BGR_REG_SMHC0_RST_OFFSET

#define SMHC_BGR_REG_SMHC0_RST_OFFSET   16

◆ SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK   0x00000002

◆ SMHC_BGR_REG_SMHC1_GATING_MASK

#define SMHC_BGR_REG_SMHC1_GATING_MASK   0x0

◆ SMHC_BGR_REG_SMHC1_GATING_OFFSET

#define SMHC_BGR_REG_SMHC1_GATING_OFFSET   1

◆ SMHC_BGR_REG_SMHC1_GATING_PASS

#define SMHC_BGR_REG_SMHC1_GATING_PASS   0x1

◆ SMHC_BGR_REG_SMHC1_RST_ASSERT

#define SMHC_BGR_REG_SMHC1_RST_ASSERT   0x0

◆ SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK   0x00020000

◆ SMHC_BGR_REG_SMHC1_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT   0x1

◆ SMHC_BGR_REG_SMHC1_RST_OFFSET

#define SMHC_BGR_REG_SMHC1_RST_OFFSET   17

◆ SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK

#define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK   0x00000004

◆ SMHC_BGR_REG_SMHC2_GATING_MASK

#define SMHC_BGR_REG_SMHC2_GATING_MASK   0x0

◆ SMHC_BGR_REG_SMHC2_GATING_OFFSET

#define SMHC_BGR_REG_SMHC2_GATING_OFFSET   2

◆ SMHC_BGR_REG_SMHC2_GATING_PASS

#define SMHC_BGR_REG_SMHC2_GATING_PASS   0x1

◆ SMHC_BGR_REG_SMHC2_RST_ASSERT

#define SMHC_BGR_REG_SMHC2_RST_ASSERT   0x0

◆ SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK

#define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK   0x00040000

◆ SMHC_BGR_REG_SMHC2_RST_DE_ASSERT

#define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT   0x1

◆ SMHC_BGR_REG_SMHC2_RST_OFFSET

#define SMHC_BGR_REG_SMHC2_RST_OFFSET   18

◆ SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI0_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SPI0_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100

◆ SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011

◆ SPI0_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI0_CLK_REG_FACTOR_M_OFFSET

#define SPI0_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON

#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON   0x1

◆ SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET

#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET   31

◆ SPI1_CLK_REG

#define SPI1_CLK_REG   0x00000944

◆ SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI1_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SPI1_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100

◆ SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011

◆ SPI1_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI1_CLK_REG_FACTOR_M_OFFSET

#define SPI1_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON

#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON   0x1

◆ SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET

#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET   31

◆ SPI2_CLK_REG

#define SPI2_CLK_REG   0x00000948

◆ SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPI2_CLK_REG_CLK_SRC_SEL_HOSC

#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SPI2_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x010

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x001

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x100

◆ SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x011

◆ SPI2_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPI2_CLK_REG_FACTOR_M_OFFSET

#define SPI2_CLK_REG_FACTOR_M_OFFSET   0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON

#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON   0x1

◆ SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET

#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET   31

◆ SPI_BGR_REG

#define SPI_BGR_REG   0x0000096c

◆ SPI_BGR_REG_SPI0_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK   0x00000001

◆ SPI_BGR_REG_SPI0_GATING_MASK

#define SPI_BGR_REG_SPI0_GATING_MASK   0x0

◆ SPI_BGR_REG_SPI0_GATING_OFFSET

#define SPI_BGR_REG_SPI0_GATING_OFFSET   0

◆ SPI_BGR_REG_SPI0_GATING_PASS

#define SPI_BGR_REG_SPI0_GATING_PASS   0x1

◆ SPI_BGR_REG_SPI0_RST_ASSERT

#define SPI_BGR_REG_SPI0_RST_ASSERT   0x0

◆ SPI_BGR_REG_SPI0_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI0_RST_CLEAR_MASK   0x00010000

◆ SPI_BGR_REG_SPI0_RST_DE_ASSERT

#define SPI_BGR_REG_SPI0_RST_DE_ASSERT   0x1

◆ SPI_BGR_REG_SPI0_RST_OFFSET

#define SPI_BGR_REG_SPI0_RST_OFFSET   16

◆ SPI_BGR_REG_SPI1_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK   0x00000002

◆ SPI_BGR_REG_SPI1_GATING_MASK

#define SPI_BGR_REG_SPI1_GATING_MASK   0x0

◆ SPI_BGR_REG_SPI1_GATING_OFFSET

#define SPI_BGR_REG_SPI1_GATING_OFFSET   1

◆ SPI_BGR_REG_SPI1_GATING_PASS

#define SPI_BGR_REG_SPI1_GATING_PASS   0x1

◆ SPI_BGR_REG_SPI1_RST_ASSERT

#define SPI_BGR_REG_SPI1_RST_ASSERT   0x0

◆ SPI_BGR_REG_SPI1_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI1_RST_CLEAR_MASK   0x00020000

◆ SPI_BGR_REG_SPI1_RST_DE_ASSERT

#define SPI_BGR_REG_SPI1_RST_DE_ASSERT   0x1

◆ SPI_BGR_REG_SPI1_RST_OFFSET

#define SPI_BGR_REG_SPI1_RST_OFFSET   17

◆ SPI_BGR_REG_SPI2_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK   0x00000004

◆ SPI_BGR_REG_SPI2_GATING_MASK

#define SPI_BGR_REG_SPI2_GATING_MASK   0x0

◆ SPI_BGR_REG_SPI2_GATING_OFFSET

#define SPI_BGR_REG_SPI2_GATING_OFFSET   2

◆ SPI_BGR_REG_SPI2_GATING_PASS

#define SPI_BGR_REG_SPI2_GATING_PASS   0x1

◆ SPI_BGR_REG_SPI2_RST_ASSERT

#define SPI_BGR_REG_SPI2_RST_ASSERT   0x0

◆ SPI_BGR_REG_SPI2_RST_CLEAR_MASK

#define SPI_BGR_REG_SPI2_RST_CLEAR_MASK   0x00040000

◆ SPI_BGR_REG_SPI2_RST_DE_ASSERT

#define SPI_BGR_REG_SPI2_RST_DE_ASSERT   0x1

◆ SPI_BGR_REG_SPI2_RST_OFFSET

#define SPI_BGR_REG_SPI2_RST_OFFSET   18

◆ SPI_BGR_REG_SPIF_GATING_CLEAR_MASK

#define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK   0x00000008

◆ SPI_BGR_REG_SPIF_GATING_MASK

#define SPI_BGR_REG_SPIF_GATING_MASK   0x0

◆ SPI_BGR_REG_SPIF_GATING_OFFSET

#define SPI_BGR_REG_SPIF_GATING_OFFSET   3

◆ SPI_BGR_REG_SPIF_GATING_PASS

#define SPI_BGR_REG_SPIF_GATING_PASS   0x1

◆ SPI_BGR_REG_SPIF_RST_ASSERT

#define SPI_BGR_REG_SPIF_RST_ASSERT   0x0

◆ SPI_BGR_REG_SPIF_RST_CLEAR_MASK

#define SPI_BGR_REG_SPIF_RST_CLEAR_MASK   0x00080000

◆ SPI_BGR_REG_SPIF_RST_DE_ASSERT

#define SPI_BGR_REG_SPIF_RST_DE_ASSERT   0x1

◆ SPI_BGR_REG_SPIF_RST_OFFSET

#define SPI_BGR_REG_SPIF_RST_OFFSET   19

◆ SPIF_CLK_REG

#define SPIF_CLK_REG   0x00000950

◆ SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ SPIF_CLK_REG_CLK_SRC_SEL_HOSC

#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ SPIF_CLK_REG_CLK_SRC_SEL_OFFSET

#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x001

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x010

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_200M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_200M   0x011

◆ SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M

#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M   0x100

◆ SPIF_CLK_REG_FACTOR_M_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ SPIF_CLK_REG_FACTOR_M_OFFSET

#define SPIF_CLK_REG_FACTOR_M_OFFSET   0

◆ SPIF_CLK_REG_FACTOR_N_CLEAR_MASK

#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK   0x00001f00

◆ SPIF_CLK_REG_FACTOR_N_OFFSET

#define SPIF_CLK_REG_FACTOR_N_OFFSET   8

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK   0x80000000

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF   0x0

◆ SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON

#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON   0x1

◆ SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET

#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET   31

◆ SPIF_GATING_SHIFT

#define SPIF_GATING_SHIFT   (3)

◆ SPIF_RESET_SHIFT

#define SPIF_RESET_SHIFT   (19)

◆ SPINLOCK_BGR_REG

#define SPINLOCK_BGR_REG   0x0000072c

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK   0x00000001

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK   0x0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET   0

◆ SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS

#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS   0x1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT   0x0

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK

#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK   0x00010000

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT

#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT   0x1

◆ SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET

#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET   16

◆ SYSDAP_BGR_REG

#define SYSDAP_BGR_REG   0x0000088c

◆ SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK   0x00000001

◆ SYSDAP_BGR_REG_SYSDAP_GATING_MASK

#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK   0x0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET   0

◆ SYSDAP_BGR_REG_SYSDAP_GATING_PASS

#define SYSDAP_BGR_REG_SYSDAP_GATING_PASS   0x1

◆ SYSDAP_BGR_REG_SYSDAP_RST_ASSERT

#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT   0x0

◆ SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK

#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK   0x00010000

◆ SYSDAP_BGR_REG_SYSDAP_RST_DE_ASSERT

#define SYSDAP_BGR_REG_SYSDAP_RST_DE_ASSERT   0x1

◆ SYSDAP_BGR_REG_SYSDAP_RST_OFFSET

#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET   16

◆ SYSDAP_REQ_CTRL_REG

#define SYSDAP_REQ_CTRL_REG   0x00000f08

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK   0x00000001

◆ SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET

#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET   0

◆ TCONLCD_BGR_REG

#define TCONLCD_BGR_REG   0x00000b7c

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK   0x00000001

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_MASK   0x0

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_OFFSET

#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_OFFSET   0

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_PASS

#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_PASS   0x1

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_RST_ASSERT

#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_ASSERT   0x0

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK   0x00010000

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT

#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT   0x1

◆ TCONLCD_BGR_REG_VO0_TCONLCD0_RST_OFFSET

#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_OFFSET   16

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK   0x00000002

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_MASK   0x0

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_OFFSET

#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_OFFSET   1

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_PASS

#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_PASS   0x1

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_RST_ASSERT

#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_ASSERT   0x0

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK

#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK   0x00020000

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT

#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT   0x1

◆ TCONLCD_BGR_REG_VO0_TCONLCD1_RST_OFFSET

#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_OFFSET   17

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_CLEAR_MASK

#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_CLEAR_MASK   0x00000004

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_MASK

#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_MASK   0x0

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_OFFSET

#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_OFFSET   2

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_PASS

#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_PASS   0x1

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_RST_ASSERT

#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_ASSERT   0x0

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_RST_CLEAR_MASK

#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_CLEAR_MASK   0x00040000

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_RST_DE_ASSERT

#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_DE_ASSERT   0x1

◆ TCONLCD_BGR_REG_VO1_TCONLCD0_RST_OFFSET

#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_OFFSET   18

◆ TCONTV_BGR_REG

#define TCONTV_BGR_REG   0x00000b9c

◆ TCONTV_BGR_REG_TCONTV_GATING_CLEAR_MASK

#define TCONTV_BGR_REG_TCONTV_GATING_CLEAR_MASK   0x00000001

◆ TCONTV_BGR_REG_TCONTV_GATING_MASK

#define TCONTV_BGR_REG_TCONTV_GATING_MASK   0x0

◆ TCONTV_BGR_REG_TCONTV_GATING_OFFSET

#define TCONTV_BGR_REG_TCONTV_GATING_OFFSET   0

◆ TCONTV_BGR_REG_TCONTV_GATING_PASS

#define TCONTV_BGR_REG_TCONTV_GATING_PASS   0x1

◆ TCONTV_BGR_REG_TCONTV_RST_ASSERT

#define TCONTV_BGR_REG_TCONTV_RST_ASSERT   0x0

◆ TCONTV_BGR_REG_TCONTV_RST_CLEAR_MASK

#define TCONTV_BGR_REG_TCONTV_RST_CLEAR_MASK   0x00010000

◆ TCONTV_BGR_REG_TCONTV_RST_DE_ASSERT

#define TCONTV_BGR_REG_TCONTV_RST_DE_ASSERT   0x1

◆ TCONTV_BGR_REG_TCONTV_RST_OFFSET

#define TCONTV_BGR_REG_TCONTV_RST_OFFSET   16

◆ TCONTV_CLK_REG

#define TCONTV_CLK_REG   0x00000b80

◆ TCONTV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TCONTV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TCONTV_CLK_REG_CLK_SRC_SEL_OFFSET

#define TCONTV_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TCONTV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define TCONTV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ TCONTV_CLK_REG_FACTOR_M_CLEAR_MASK

#define TCONTV_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ TCONTV_CLK_REG_FACTOR_M_OFFSET

#define TCONTV_CLK_REG_FACTOR_M_OFFSET   0

◆ TCONTV_CLK_REG_TCONTV_CLK_GATING_CLEAR_MASK

#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLEAR_MASK   0x80000000

◆ TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_OFF

#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_OFF   0x0

◆ TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_ON

#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_ON   0x1

◆ TCONTV_CLK_REG_TCONTV_CLK_GATING_OFFSET

#define TCONTV_CLK_REG_TCONTV_CLK_GATING_OFFSET   31

◆ THS_BGR_REG

#define THS_BGR_REG   0x000009fc

◆ THS_BGR_REG_THS_GATING_CLEAR_MASK

#define THS_BGR_REG_THS_GATING_CLEAR_MASK   0x00000001

◆ THS_BGR_REG_THS_GATING_MASK

#define THS_BGR_REG_THS_GATING_MASK   0x0

◆ THS_BGR_REG_THS_GATING_OFFSET

#define THS_BGR_REG_THS_GATING_OFFSET   0

◆ THS_BGR_REG_THS_GATING_PASS

#define THS_BGR_REG_THS_GATING_PASS   0x1

◆ THS_BGR_REG_THS_RST_ASSERT

#define THS_BGR_REG_THS_RST_ASSERT   0x0

◆ THS_BGR_REG_THS_RST_CLEAR_MASK

#define THS_BGR_REG_THS_RST_CLEAR_MASK   0x00010000

◆ THS_BGR_REG_THS_RST_DE_ASSERT

#define THS_BGR_REG_THS_RST_DE_ASSERT   0x1

◆ THS_BGR_REG_THS_RST_OFFSET

#define THS_BGR_REG_THS_RST_OFFSET   16

◆ TIMER0_CLK_REG

#define TIMER0_CLK_REG   0x00000730

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER0_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER0_CLK_REG_FACTOR_M__1

#define TIMER0_CLK_REG_FACTOR_M__1   0x000

◆ TIMER0_CLK_REG_FACTOR_M__128

#define TIMER0_CLK_REG_FACTOR_M__128   0x111

◆ TIMER0_CLK_REG_FACTOR_M__16

#define TIMER0_CLK_REG_FACTOR_M__16   0x100

◆ TIMER0_CLK_REG_FACTOR_M__2

#define TIMER0_CLK_REG_FACTOR_M__2   0x001

◆ TIMER0_CLK_REG_FACTOR_M__32

#define TIMER0_CLK_REG_FACTOR_M__32   0x101

◆ TIMER0_CLK_REG_FACTOR_M__4

#define TIMER0_CLK_REG_FACTOR_M__4   0x010

◆ TIMER0_CLK_REG_FACTOR_M__64

#define TIMER0_CLK_REG_FACTOR_M__64   0x110

◆ TIMER0_CLK_REG_FACTOR_M__8

#define TIMER0_CLK_REG_FACTOR_M__8   0x011

◆ TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER0_CLK_REG_FACTOR_M_OFFSET

#define TIMER0_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE   0x0

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE   0x1

◆ TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET

#define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET   31

◆ TIMER1_CLK_REG

#define TIMER1_CLK_REG   0x00000734

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER1_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER1_CLK_REG_FACTOR_M__1

#define TIMER1_CLK_REG_FACTOR_M__1   0x000

◆ TIMER1_CLK_REG_FACTOR_M__128

#define TIMER1_CLK_REG_FACTOR_M__128   0x111

◆ TIMER1_CLK_REG_FACTOR_M__16

#define TIMER1_CLK_REG_FACTOR_M__16   0x100

◆ TIMER1_CLK_REG_FACTOR_M__2

#define TIMER1_CLK_REG_FACTOR_M__2   0x001

◆ TIMER1_CLK_REG_FACTOR_M__32

#define TIMER1_CLK_REG_FACTOR_M__32   0x101

◆ TIMER1_CLK_REG_FACTOR_M__4

#define TIMER1_CLK_REG_FACTOR_M__4   0x010

◆ TIMER1_CLK_REG_FACTOR_M__64

#define TIMER1_CLK_REG_FACTOR_M__64   0x110

◆ TIMER1_CLK_REG_FACTOR_M__8

#define TIMER1_CLK_REG_FACTOR_M__8   0x011

◆ TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER1_CLK_REG_FACTOR_M_OFFSET

#define TIMER1_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE   0x0

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE   0x1

◆ TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET

#define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET   31

◆ TIMER2_CLK_REG

#define TIMER2_CLK_REG   0x00000738

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER2_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC   0x00

◆ TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER2_CLK_REG_FACTOR_M__1

#define TIMER2_CLK_REG_FACTOR_M__1   0x000

◆ TIMER2_CLK_REG_FACTOR_M__128

#define TIMER2_CLK_REG_FACTOR_M__128   0x111

◆ TIMER2_CLK_REG_FACTOR_M__16

#define TIMER2_CLK_REG_FACTOR_M__16   0x100

◆ TIMER2_CLK_REG_FACTOR_M__2

#define TIMER2_CLK_REG_FACTOR_M__2   0x001

◆ TIMER2_CLK_REG_FACTOR_M__32

#define TIMER2_CLK_REG_FACTOR_M__32   0x101

◆ TIMER2_CLK_REG_FACTOR_M__4

#define TIMER2_CLK_REG_FACTOR_M__4   0x010

◆ TIMER2_CLK_REG_FACTOR_M__64

#define TIMER2_CLK_REG_FACTOR_M__64   0x110

◆ TIMER2_CLK_REG_FACTOR_M__8

#define TIMER2_CLK_REG_FACTOR_M__8   0x011

◆ TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER2_CLK_REG_FACTOR_M_OFFSET

#define TIMER2_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE   0x0

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE   0x1

◆ TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET

#define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET   31

◆ TIMER3_CLK_REG

#define TIMER3_CLK_REG   0x0000073c

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER3_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER3_CLK_REG_FACTOR_M__1

#define TIMER3_CLK_REG_FACTOR_M__1   0x000

◆ TIMER3_CLK_REG_FACTOR_M__128

#define TIMER3_CLK_REG_FACTOR_M__128   0x111

◆ TIMER3_CLK_REG_FACTOR_M__16

#define TIMER3_CLK_REG_FACTOR_M__16   0x100

◆ TIMER3_CLK_REG_FACTOR_M__2

#define TIMER3_CLK_REG_FACTOR_M__2   0x001

◆ TIMER3_CLK_REG_FACTOR_M__32

#define TIMER3_CLK_REG_FACTOR_M__32   0x101

◆ TIMER3_CLK_REG_FACTOR_M__4

#define TIMER3_CLK_REG_FACTOR_M__4   0x010

◆ TIMER3_CLK_REG_FACTOR_M__64

#define TIMER3_CLK_REG_FACTOR_M__64   0x110

◆ TIMER3_CLK_REG_FACTOR_M__8

#define TIMER3_CLK_REG_FACTOR_M__8   0x011

◆ TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER3_CLK_REG_FACTOR_M_OFFSET

#define TIMER3_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE   0x0

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE   0x1

◆ TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET

#define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET   31

◆ TIMER4_CLK_REG

#define TIMER4_CLK_REG   0x00000740

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER4_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER4_CLK_REG_FACTOR_M__1

#define TIMER4_CLK_REG_FACTOR_M__1   0x000

◆ TIMER4_CLK_REG_FACTOR_M__128

#define TIMER4_CLK_REG_FACTOR_M__128   0x111

◆ TIMER4_CLK_REG_FACTOR_M__16

#define TIMER4_CLK_REG_FACTOR_M__16   0x100

◆ TIMER4_CLK_REG_FACTOR_M__2

#define TIMER4_CLK_REG_FACTOR_M__2   0x001

◆ TIMER4_CLK_REG_FACTOR_M__32

#define TIMER4_CLK_REG_FACTOR_M__32   0x101

◆ TIMER4_CLK_REG_FACTOR_M__4

#define TIMER4_CLK_REG_FACTOR_M__4   0x010

◆ TIMER4_CLK_REG_FACTOR_M__64

#define TIMER4_CLK_REG_FACTOR_M__64   0x110

◆ TIMER4_CLK_REG_FACTOR_M__8

#define TIMER4_CLK_REG_FACTOR_M__8   0x011

◆ TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER4_CLK_REG_FACTOR_M_OFFSET

#define TIMER4_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE   0x0

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE   0x1

◆ TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET

#define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET   31

◆ TIMER5_CLK_REG

#define TIMER5_CLK_REG   0x00000744

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x001

◆ TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K

#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K   0x010

◆ TIMER5_CLK_REG_CLK_SRC_SEL_HOSC

#define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET

#define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M

#define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M   0x011

◆ TIMER5_CLK_REG_FACTOR_M__1

#define TIMER5_CLK_REG_FACTOR_M__1   0x000

◆ TIMER5_CLK_REG_FACTOR_M__128

#define TIMER5_CLK_REG_FACTOR_M__128   0x111

◆ TIMER5_CLK_REG_FACTOR_M__16

#define TIMER5_CLK_REG_FACTOR_M__16   0x100

◆ TIMER5_CLK_REG_FACTOR_M__2

#define TIMER5_CLK_REG_FACTOR_M__2   0x001

◆ TIMER5_CLK_REG_FACTOR_M__32

#define TIMER5_CLK_REG_FACTOR_M__32   0x101

◆ TIMER5_CLK_REG_FACTOR_M__4

#define TIMER5_CLK_REG_FACTOR_M__4   0x010

◆ TIMER5_CLK_REG_FACTOR_M__64

#define TIMER5_CLK_REG_FACTOR_M__64   0x110

◆ TIMER5_CLK_REG_FACTOR_M__8

#define TIMER5_CLK_REG_FACTOR_M__8   0x011

◆ TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK

#define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK   0x00000007

◆ TIMER5_CLK_REG_FACTOR_M_OFFSET

#define TIMER5_CLK_REG_FACTOR_M_OFFSET   0

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK   0x80000000

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE   0x0

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE   0x1

◆ TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET

#define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET   31

◆ TIMER_BGR_REG

#define TIMER_BGR_REG   0x0000074c

◆ TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK

#define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK   0x00000001

◆ TIMER_BGR_REG_TIMER_GATING_MASK

#define TIMER_BGR_REG_TIMER_GATING_MASK   0x0

◆ TIMER_BGR_REG_TIMER_GATING_OFFSET

#define TIMER_BGR_REG_TIMER_GATING_OFFSET   0

◆ TIMER_BGR_REG_TIMER_GATING_PASS

#define TIMER_BGR_REG_TIMER_GATING_PASS   0x1

◆ TIMER_BGR_REG_TIMER_RST_ASSERT

#define TIMER_BGR_REG_TIMER_RST_ASSERT   0x0

◆ TIMER_BGR_REG_TIMER_RST_CLEAR_MASK

#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK   0x00010000

◆ TIMER_BGR_REG_TIMER_RST_DE_ASSERT

#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT   0x1

◆ TIMER_BGR_REG_TIMER_RST_OFFSET

#define TIMER_BGR_REG_TIMER_RST_OFFSET   16

◆ TRACE_CLK_REG

#define TRACE_CLK_REG   0x00000508

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC   0x010

◆ TRACE_CLK_REG_CLK_SRC_SEL_CLK32K

#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K   0x001

◆ TRACE_CLK_REG_CLK_SRC_SEL_HOSC

#define TRACE_CLK_REG_CLK_SRC_SEL_HOSC   0x000

◆ TRACE_CLK_REG_CLK_SRC_SEL_OFFSET

#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x011

◆ TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x100

◆ TRACE_CLK_REG_FACTOR_M_CLEAR_MASK

#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ TRACE_CLK_REG_FACTOR_M_OFFSET

#define TRACE_CLK_REG_FACTOR_M_OFFSET   0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK   0x80000000

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF   0x0

◆ TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON

#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON   0x1

◆ TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET

#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET   31

◆ TWI_BGR_REG

#define TWI_BGR_REG   0x0000091c

◆ TWI_BGR_REG_TWI0_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK   0x00000001

◆ TWI_BGR_REG_TWI0_GATING_MASK

#define TWI_BGR_REG_TWI0_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI0_GATING_OFFSET

#define TWI_BGR_REG_TWI0_GATING_OFFSET   0

◆ TWI_BGR_REG_TWI0_GATING_PASS

#define TWI_BGR_REG_TWI0_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI0_RST_ASSERT

#define TWI_BGR_REG_TWI0_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI0_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI0_RST_CLEAR_MASK   0x00010000

◆ TWI_BGR_REG_TWI0_RST_DE_ASSERT

#define TWI_BGR_REG_TWI0_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI0_RST_OFFSET

#define TWI_BGR_REG_TWI0_RST_OFFSET   16

◆ TWI_BGR_REG_TWI1_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK   0x00000002

◆ TWI_BGR_REG_TWI1_GATING_MASK

#define TWI_BGR_REG_TWI1_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI1_GATING_OFFSET

#define TWI_BGR_REG_TWI1_GATING_OFFSET   1

◆ TWI_BGR_REG_TWI1_GATING_PASS

#define TWI_BGR_REG_TWI1_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI1_RST_ASSERT

#define TWI_BGR_REG_TWI1_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI1_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI1_RST_CLEAR_MASK   0x00020000

◆ TWI_BGR_REG_TWI1_RST_DE_ASSERT

#define TWI_BGR_REG_TWI1_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI1_RST_OFFSET

#define TWI_BGR_REG_TWI1_RST_OFFSET   17

◆ TWI_BGR_REG_TWI2_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK   0x00000004

◆ TWI_BGR_REG_TWI2_GATING_MASK

#define TWI_BGR_REG_TWI2_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI2_GATING_OFFSET

#define TWI_BGR_REG_TWI2_GATING_OFFSET   2

◆ TWI_BGR_REG_TWI2_GATING_PASS

#define TWI_BGR_REG_TWI2_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI2_RST_ASSERT

#define TWI_BGR_REG_TWI2_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI2_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI2_RST_CLEAR_MASK   0x00040000

◆ TWI_BGR_REG_TWI2_RST_DE_ASSERT

#define TWI_BGR_REG_TWI2_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI2_RST_OFFSET

#define TWI_BGR_REG_TWI2_RST_OFFSET   18

◆ TWI_BGR_REG_TWI3_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK   0x00000008

◆ TWI_BGR_REG_TWI3_GATING_MASK

#define TWI_BGR_REG_TWI3_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI3_GATING_OFFSET

#define TWI_BGR_REG_TWI3_GATING_OFFSET   3

◆ TWI_BGR_REG_TWI3_GATING_PASS

#define TWI_BGR_REG_TWI3_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI3_RST_ASSERT

#define TWI_BGR_REG_TWI3_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI3_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI3_RST_CLEAR_MASK   0x00080000

◆ TWI_BGR_REG_TWI3_RST_DE_ASSERT

#define TWI_BGR_REG_TWI3_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI3_RST_OFFSET

#define TWI_BGR_REG_TWI3_RST_OFFSET   19

◆ TWI_BGR_REG_TWI4_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI4_GATING_CLEAR_MASK   0x00000010

◆ TWI_BGR_REG_TWI4_GATING_MASK

#define TWI_BGR_REG_TWI4_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI4_GATING_OFFSET

#define TWI_BGR_REG_TWI4_GATING_OFFSET   4

◆ TWI_BGR_REG_TWI4_GATING_PASS

#define TWI_BGR_REG_TWI4_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI4_RST_ASSERT

#define TWI_BGR_REG_TWI4_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI4_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI4_RST_CLEAR_MASK   0x00100000

◆ TWI_BGR_REG_TWI4_RST_DE_ASSERT

#define TWI_BGR_REG_TWI4_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI4_RST_OFFSET

#define TWI_BGR_REG_TWI4_RST_OFFSET   20

◆ TWI_BGR_REG_TWI5_GATING_CLEAR_MASK

#define TWI_BGR_REG_TWI5_GATING_CLEAR_MASK   0x00000020

◆ TWI_BGR_REG_TWI5_GATING_MASK

#define TWI_BGR_REG_TWI5_GATING_MASK   0x0

◆ TWI_BGR_REG_TWI5_GATING_OFFSET

#define TWI_BGR_REG_TWI5_GATING_OFFSET   5

◆ TWI_BGR_REG_TWI5_GATING_PASS

#define TWI_BGR_REG_TWI5_GATING_PASS   0x1

◆ TWI_BGR_REG_TWI5_RST_ASSERT

#define TWI_BGR_REG_TWI5_RST_ASSERT   0x0

◆ TWI_BGR_REG_TWI5_RST_CLEAR_MASK

#define TWI_BGR_REG_TWI5_RST_CLEAR_MASK   0x00200000

◆ TWI_BGR_REG_TWI5_RST_DE_ASSERT

#define TWI_BGR_REG_TWI5_RST_DE_ASSERT   0x1

◆ TWI_BGR_REG_TWI5_RST_OFFSET

#define TWI_BGR_REG_TWI5_RST_OFFSET   21

◆ UART_BGR_REG

#define UART_BGR_REG   0x0000090c

◆ UART_BGR_REG_UART0_GATING_CLEAR_MASK

#define UART_BGR_REG_UART0_GATING_CLEAR_MASK   0x00000001

◆ UART_BGR_REG_UART0_GATING_MASK

#define UART_BGR_REG_UART0_GATING_MASK   0x0

◆ UART_BGR_REG_UART0_GATING_OFFSET

#define UART_BGR_REG_UART0_GATING_OFFSET   0

◆ UART_BGR_REG_UART0_GATING_PASS

#define UART_BGR_REG_UART0_GATING_PASS   0x1

◆ UART_BGR_REG_UART0_RST_ASSERT

#define UART_BGR_REG_UART0_RST_ASSERT   0x0

◆ UART_BGR_REG_UART0_RST_CLEAR_MASK

#define UART_BGR_REG_UART0_RST_CLEAR_MASK   0x00010000

◆ UART_BGR_REG_UART0_RST_DE_ASSERT

#define UART_BGR_REG_UART0_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART0_RST_OFFSET

#define UART_BGR_REG_UART0_RST_OFFSET   16

◆ UART_BGR_REG_UART1_GATING_CLEAR_MASK

#define UART_BGR_REG_UART1_GATING_CLEAR_MASK   0x00000002

◆ UART_BGR_REG_UART1_GATING_MASK

#define UART_BGR_REG_UART1_GATING_MASK   0x0

◆ UART_BGR_REG_UART1_GATING_OFFSET

#define UART_BGR_REG_UART1_GATING_OFFSET   1

◆ UART_BGR_REG_UART1_GATING_PASS

#define UART_BGR_REG_UART1_GATING_PASS   0x1

◆ UART_BGR_REG_UART1_RST_ASSERT

#define UART_BGR_REG_UART1_RST_ASSERT   0x0

◆ UART_BGR_REG_UART1_RST_CLEAR_MASK

#define UART_BGR_REG_UART1_RST_CLEAR_MASK   0x00020000

◆ UART_BGR_REG_UART1_RST_DE_ASSERT

#define UART_BGR_REG_UART1_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART1_RST_OFFSET

#define UART_BGR_REG_UART1_RST_OFFSET   17

◆ UART_BGR_REG_UART2_GATING_CLEAR_MASK

#define UART_BGR_REG_UART2_GATING_CLEAR_MASK   0x00000004

◆ UART_BGR_REG_UART2_GATING_MASK

#define UART_BGR_REG_UART2_GATING_MASK   0x0

◆ UART_BGR_REG_UART2_GATING_OFFSET

#define UART_BGR_REG_UART2_GATING_OFFSET   2

◆ UART_BGR_REG_UART2_GATING_PASS

#define UART_BGR_REG_UART2_GATING_PASS   0x1

◆ UART_BGR_REG_UART2_RST_ASSERT

#define UART_BGR_REG_UART2_RST_ASSERT   0x0

◆ UART_BGR_REG_UART2_RST_CLEAR_MASK

#define UART_BGR_REG_UART2_RST_CLEAR_MASK   0x00040000

◆ UART_BGR_REG_UART2_RST_DE_ASSERT

#define UART_BGR_REG_UART2_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART2_RST_OFFSET

#define UART_BGR_REG_UART2_RST_OFFSET   18

◆ UART_BGR_REG_UART3_GATING_CLEAR_MASK

#define UART_BGR_REG_UART3_GATING_CLEAR_MASK   0x00000008

◆ UART_BGR_REG_UART3_GATING_MASK

#define UART_BGR_REG_UART3_GATING_MASK   0x0

◆ UART_BGR_REG_UART3_GATING_OFFSET

#define UART_BGR_REG_UART3_GATING_OFFSET   3

◆ UART_BGR_REG_UART3_GATING_PASS

#define UART_BGR_REG_UART3_GATING_PASS   0x1

◆ UART_BGR_REG_UART3_RST_ASSERT

#define UART_BGR_REG_UART3_RST_ASSERT   0x0

◆ UART_BGR_REG_UART3_RST_CLEAR_MASK

#define UART_BGR_REG_UART3_RST_CLEAR_MASK   0x00080000

◆ UART_BGR_REG_UART3_RST_DE_ASSERT

#define UART_BGR_REG_UART3_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART3_RST_OFFSET

#define UART_BGR_REG_UART3_RST_OFFSET   19

◆ UART_BGR_REG_UART4_GATING_CLEAR_MASK

#define UART_BGR_REG_UART4_GATING_CLEAR_MASK   0x00000010

◆ UART_BGR_REG_UART4_GATING_MASK

#define UART_BGR_REG_UART4_GATING_MASK   0x0

◆ UART_BGR_REG_UART4_GATING_OFFSET

#define UART_BGR_REG_UART4_GATING_OFFSET   4

◆ UART_BGR_REG_UART4_GATING_PASS

#define UART_BGR_REG_UART4_GATING_PASS   0x1

◆ UART_BGR_REG_UART4_RST_ASSERT

#define UART_BGR_REG_UART4_RST_ASSERT   0x0

◆ UART_BGR_REG_UART4_RST_CLEAR_MASK

#define UART_BGR_REG_UART4_RST_CLEAR_MASK   0x00100000

◆ UART_BGR_REG_UART4_RST_DE_ASSERT

#define UART_BGR_REG_UART4_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART4_RST_OFFSET

#define UART_BGR_REG_UART4_RST_OFFSET   20

◆ UART_BGR_REG_UART5_GATING_CLEAR_MASK

#define UART_BGR_REG_UART5_GATING_CLEAR_MASK   0x00000020

◆ UART_BGR_REG_UART5_GATING_MASK

#define UART_BGR_REG_UART5_GATING_MASK   0x0

◆ UART_BGR_REG_UART5_GATING_OFFSET

#define UART_BGR_REG_UART5_GATING_OFFSET   5

◆ UART_BGR_REG_UART5_GATING_PASS

#define UART_BGR_REG_UART5_GATING_PASS   0x1

◆ UART_BGR_REG_UART5_RST_ASSERT

#define UART_BGR_REG_UART5_RST_ASSERT   0x0

◆ UART_BGR_REG_UART5_RST_CLEAR_MASK

#define UART_BGR_REG_UART5_RST_CLEAR_MASK   0x00200000

◆ UART_BGR_REG_UART5_RST_DE_ASSERT

#define UART_BGR_REG_UART5_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART5_RST_OFFSET

#define UART_BGR_REG_UART5_RST_OFFSET   21

◆ UART_BGR_REG_UART6_GATING_CLEAR_MASK

#define UART_BGR_REG_UART6_GATING_CLEAR_MASK   0x00000040

◆ UART_BGR_REG_UART6_GATING_MASK

#define UART_BGR_REG_UART6_GATING_MASK   0x0

◆ UART_BGR_REG_UART6_GATING_OFFSET

#define UART_BGR_REG_UART6_GATING_OFFSET   6

◆ UART_BGR_REG_UART6_GATING_PASS

#define UART_BGR_REG_UART6_GATING_PASS   0x1

◆ UART_BGR_REG_UART6_RST_ASSERT

#define UART_BGR_REG_UART6_RST_ASSERT   0x0

◆ UART_BGR_REG_UART6_RST_CLEAR_MASK

#define UART_BGR_REG_UART6_RST_CLEAR_MASK   0x00400000

◆ UART_BGR_REG_UART6_RST_DE_ASSERT

#define UART_BGR_REG_UART6_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART6_RST_OFFSET

#define UART_BGR_REG_UART6_RST_OFFSET   22

◆ UART_BGR_REG_UART7_GATING_CLEAR_MASK

#define UART_BGR_REG_UART7_GATING_CLEAR_MASK   0x00000080

◆ UART_BGR_REG_UART7_GATING_MASK

#define UART_BGR_REG_UART7_GATING_MASK   0x0

◆ UART_BGR_REG_UART7_GATING_OFFSET

#define UART_BGR_REG_UART7_GATING_OFFSET   7

◆ UART_BGR_REG_UART7_GATING_PASS

#define UART_BGR_REG_UART7_GATING_PASS   0x1

◆ UART_BGR_REG_UART7_RST_ASSERT

#define UART_BGR_REG_UART7_RST_ASSERT   0x0

◆ UART_BGR_REG_UART7_RST_CLEAR_MASK

#define UART_BGR_REG_UART7_RST_CLEAR_MASK   0x00800000

◆ UART_BGR_REG_UART7_RST_DE_ASSERT

#define UART_BGR_REG_UART7_RST_DE_ASSERT   0x1

◆ UART_BGR_REG_UART7_RST_OFFSET

#define UART_BGR_REG_UART7_RST_OFFSET   23

◆ USB0_CLK_REG

#define USB0_CLK_REG   0x00000a70

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0x01

◆ USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0x00

◆ USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK   0x03000000

◆ USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET

#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET   24

◆ USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K

#define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K   0x10

◆ USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK

#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK   0x80000000

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF   0x0

◆ USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON

#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON   0x1

◆ USB0_CLK_REG_USB0_CLKEN_OFFSET

#define USB0_CLK_REG_USB0_CLKEN_OFFSET   31

◆ USB0_CLK_REG_USBPHY0_RSTN_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT   0x0

◆ USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK

#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK   0x40000000

◆ USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT

#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT   0x1

◆ USB0_CLK_REG_USBPHY0_RSTN_OFFSET

#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET   30

◆ USB1_CLK_REG

#define USB1_CLK_REG   0x00000a74

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ   0x01

◆ USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ

#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ   0x00

◆ USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK   0x03000000

◆ USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET

#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET   24

◆ USB1_CLK_REG_USB1_CLK12M_SEL_RTC_32K

#define USB1_CLK_REG_USB1_CLK12M_SEL_RTC_32K   0x10

◆ USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK

#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK   0x80000000

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF   0x0

◆ USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON

#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON   0x1

◆ USB1_CLK_REG_USB1_CLKEN_OFFSET

#define USB1_CLK_REG_USB1_CLKEN_OFFSET   31

◆ USB1_CLK_REG_USBPHY1_RSTN_ASSERT

#define USB1_CLK_REG_USBPHY1_RSTN_ASSERT   0x0

◆ USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK

#define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK   0x40000000

◆ USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT

#define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT   0x1

◆ USB1_CLK_REG_USBPHY1_RSTN_OFFSET

#define USB1_CLK_REG_USBPHY1_RSTN_OFFSET   30

◆ USB2_REF_CLK_REG

#define USB2_REF_CLK_REG   0x00000a78

◆ USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK

#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF

#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF   0x0

◆ USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON

#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON   0x1

◆ USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET

#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET   31

◆ USB2_SUSPEND_CLK_REG

#define USB2_SUSPEND_CLK_REG   0x00000a7c

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK   0x80000000

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF   0x0

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON   0x1

◆ USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET

#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET   31

◆ USB_BGR_REG

#define USB_BGR_REG   0x00000a8c

◆ USB_BGR_REG_USB2_GATING_CLEAR_MASK

#define USB_BGR_REG_USB2_GATING_CLEAR_MASK   0x00000200

◆ USB_BGR_REG_USB2_GATING_MASK

#define USB_BGR_REG_USB2_GATING_MASK   0x0

◆ USB_BGR_REG_USB2_GATING_OFFSET

#define USB_BGR_REG_USB2_GATING_OFFSET   9

◆ USB_BGR_REG_USB2_GATING_PASS

#define USB_BGR_REG_USB2_GATING_PASS   0x1

◆ USB_BGR_REG_USB2_PHY_RST_ASSERT

#define USB_BGR_REG_USB2_PHY_RST_ASSERT   0x0

◆ USB_BGR_REG_USB2_PHY_RST_CLEAR_MASK

#define USB_BGR_REG_USB2_PHY_RST_CLEAR_MASK   0x04000000

◆ USB_BGR_REG_USB2_PHY_RST_DE_ASSERT

#define USB_BGR_REG_USB2_PHY_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USB2_PHY_RST_OFFSET

#define USB_BGR_REG_USB2_PHY_RST_OFFSET   26

◆ USB_BGR_REG_USB2_RST_ASSERT

#define USB_BGR_REG_USB2_RST_ASSERT   0x0

◆ USB_BGR_REG_USB2_RST_CLEAR_MASK

#define USB_BGR_REG_USB2_RST_CLEAR_MASK   0x02000000

◆ USB_BGR_REG_USB2_RST_DE_ASSERT

#define USB_BGR_REG_USB2_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USB2_RST_OFFSET

#define USB_BGR_REG_USB2_RST_OFFSET   25

◆ USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK   0x00000010

◆ USB_BGR_REG_USBEHCI0_GATING_MASK

#define USB_BGR_REG_USBEHCI0_GATING_MASK   0x0

◆ USB_BGR_REG_USBEHCI0_GATING_OFFSET

#define USB_BGR_REG_USBEHCI0_GATING_OFFSET   4

◆ USB_BGR_REG_USBEHCI0_GATING_PASS

#define USB_BGR_REG_USBEHCI0_GATING_PASS   0x1

◆ USB_BGR_REG_USBEHCI0_RST_ASSERT

#define USB_BGR_REG_USBEHCI0_RST_ASSERT   0x0

◆ USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK

#define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK   0x00100000

◆ USB_BGR_REG_USBEHCI0_RST_DE_ASSERT

#define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USBEHCI0_RST_OFFSET

#define USB_BGR_REG_USBEHCI0_RST_OFFSET   20

◆ USB_BGR_REG_USBEHCI1_GATING_CLEAR_MASK

#define USB_BGR_REG_USBEHCI1_GATING_CLEAR_MASK   0x00000020

◆ USB_BGR_REG_USBEHCI1_GATING_MASK

#define USB_BGR_REG_USBEHCI1_GATING_MASK   0x0

◆ USB_BGR_REG_USBEHCI1_GATING_OFFSET

#define USB_BGR_REG_USBEHCI1_GATING_OFFSET   5

◆ USB_BGR_REG_USBEHCI1_GATING_PASS

#define USB_BGR_REG_USBEHCI1_GATING_PASS   0x1

◆ USB_BGR_REG_USBEHCI1_RST_ASSERT

#define USB_BGR_REG_USBEHCI1_RST_ASSERT   0x0

◆ USB_BGR_REG_USBEHCI1_RST_CLEAR_MASK

#define USB_BGR_REG_USBEHCI1_RST_CLEAR_MASK   0x00200000

◆ USB_BGR_REG_USBEHCI1_RST_DE_ASSERT

#define USB_BGR_REG_USBEHCI1_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USBEHCI1_RST_OFFSET

#define USB_BGR_REG_USBEHCI1_RST_OFFSET   21

◆ USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK   0x00000001

◆ USB_BGR_REG_USBOHCI0_GATING_MASK

#define USB_BGR_REG_USBOHCI0_GATING_MASK   0x0

◆ USB_BGR_REG_USBOHCI0_GATING_OFFSET

#define USB_BGR_REG_USBOHCI0_GATING_OFFSET   0

◆ USB_BGR_REG_USBOHCI0_GATING_PASS

#define USB_BGR_REG_USBOHCI0_GATING_PASS   0x1

◆ USB_BGR_REG_USBOHCI0_RST_ASSERT

#define USB_BGR_REG_USBOHCI0_RST_ASSERT   0x0

◆ USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK

#define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK   0x00010000

◆ USB_BGR_REG_USBOHCI0_RST_DE_ASSERT

#define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USBOHCI0_RST_OFFSET

#define USB_BGR_REG_USBOHCI0_RST_OFFSET   16

◆ USB_BGR_REG_USBOHCI1_GATING_CLEAR_MASK

#define USB_BGR_REG_USBOHCI1_GATING_CLEAR_MASK   0x00000002

◆ USB_BGR_REG_USBOHCI1_GATING_MASK

#define USB_BGR_REG_USBOHCI1_GATING_MASK   0x0

◆ USB_BGR_REG_USBOHCI1_GATING_OFFSET

#define USB_BGR_REG_USBOHCI1_GATING_OFFSET   1

◆ USB_BGR_REG_USBOHCI1_GATING_PASS

#define USB_BGR_REG_USBOHCI1_GATING_PASS   0x1

◆ USB_BGR_REG_USBOHCI1_RST_ASSERT

#define USB_BGR_REG_USBOHCI1_RST_ASSERT   0x0

◆ USB_BGR_REG_USBOHCI1_RST_CLEAR_MASK

#define USB_BGR_REG_USBOHCI1_RST_CLEAR_MASK   0x00020000

◆ USB_BGR_REG_USBOHCI1_RST_DE_ASSERT

#define USB_BGR_REG_USBOHCI1_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USBOHCI1_RST_OFFSET

#define USB_BGR_REG_USBOHCI1_RST_OFFSET   17

◆ USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK

#define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK   0x00000100

◆ USB_BGR_REG_USBOTG0_GATING_MASK

#define USB_BGR_REG_USBOTG0_GATING_MASK   0x0

◆ USB_BGR_REG_USBOTG0_GATING_OFFSET

#define USB_BGR_REG_USBOTG0_GATING_OFFSET   8

◆ USB_BGR_REG_USBOTG0_GATING_PASS

#define USB_BGR_REG_USBOTG0_GATING_PASS   0x1

◆ USB_BGR_REG_USBOTG0_RST_ASSERT

#define USB_BGR_REG_USBOTG0_RST_ASSERT   0x0

◆ USB_BGR_REG_USBOTG0_RST_CLEAR_MASK

#define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK   0x01000000

◆ USB_BGR_REG_USBOTG0_RST_DE_ASSERT

#define USB_BGR_REG_USBOTG0_RST_DE_ASSERT   0x1

◆ USB_BGR_REG_USBOTG0_RST_OFFSET

#define USB_BGR_REG_USBOTG0_RST_OFFSET   24

◆ USBEHCI0_GATIING_BIT

#define USBEHCI0_GATIING_BIT   24

◆ USBEHCI0_RST_BIT

#define USBEHCI0_RST_BIT   24

◆ USBEHCI1_GATIING_BIT

#define USBEHCI1_GATIING_BIT   25

◆ USBEHCI1_RST_BIT

#define USBEHCI1_RST_BIT   25

◆ USBPHY0_RST_BIT

#define USBPHY0_RST_BIT   0

◆ USBPHY0_SCLK_GATING_BIT

#define USBPHY0_SCLK_GATING_BIT   8

◆ USBPHY1_RST_BIT

#define USBPHY1_RST_BIT   1

◆ USBPHY1_SCLK_GATING_BIT

#define USBPHY1_SCLK_GATING_BIT   9

◆ USBPHY_CONFIG_REG

#define USBPHY_CONFIG_REG   0xcc

◆ VE_BGR_REG

#define VE_BGR_REG   0x0000069c

◆ VE_BGR_REG_VE_GATING_CLEAR_MASK

#define VE_BGR_REG_VE_GATING_CLEAR_MASK   0x00000001

◆ VE_BGR_REG_VE_GATING_MASK

#define VE_BGR_REG_VE_GATING_MASK   0x0

◆ VE_BGR_REG_VE_GATING_OFFSET

#define VE_BGR_REG_VE_GATING_OFFSET   0

◆ VE_BGR_REG_VE_GATING_PASS

#define VE_BGR_REG_VE_GATING_PASS   0x1

◆ VE_BGR_REG_VE_RST_ASSERT

#define VE_BGR_REG_VE_RST_ASSERT   0x0

◆ VE_BGR_REG_VE_RST_CLEAR_MASK

#define VE_BGR_REG_VE_RST_CLEAR_MASK   0x00010000

◆ VE_BGR_REG_VE_RST_DE_ASSERT

#define VE_BGR_REG_VE_RST_DE_ASSERT   0x1

◆ VE_BGR_REG_VE_RST_OFFSET

#define VE_BGR_REG_VE_RST_OFFSET   16

◆ VE_CLK_REG

#define VE_CLK_REG   0x00000690

◆ VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VE_CLK_REG_CLK_SRC_SEL_OFFSET

#define VE_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_300M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M   0x011

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_400M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M   0x010

◆ VE_CLK_REG_CLK_SRC_SEL_PERI0_480M

#define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M   0x001

◆ VE_CLK_REG_CLK_SRC_SEL_VEPLL

#define VE_CLK_REG_CLK_SRC_SEL_VEPLL   0x000

◆ VE_CLK_REG_FACTOR_M_CLEAR_MASK

#define VE_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VE_CLK_REG_FACTOR_M_OFFSET

#define VE_CLK_REG_FACTOR_M_OFFSET   0

◆ VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK

#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK   0x80000000

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF   0x0

◆ VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON

#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON   0x1

◆ VE_CLK_REG_VE_CLK_GATING_OFFSET

#define VE_CLK_REG_VE_CLK_GATING_OFFSET   31

◆ VO0_TCONLCD0_CLK_REG

#define VO0_TCONLCD0_CLK_REG   0x00000b60

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK   0x80000000

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0x1

◆ VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET

#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET   31

◆ VO0_TCONLCD1_CLK_REG

#define VO0_TCONLCD1_CLK_REG   0x00000b64

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET

#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET   0

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK   0x80000000

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF   0x0

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON   0x1

◆ VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET

#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET   31

◆ VO1_TCONLCD0_CLK_REG

#define VO1_TCONLCD0_CLK_REG   0x00000b68

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK   0x07000000

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET   24

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X   0x100

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X   0x000

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X   0x001

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X   0x010

◆ VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X

#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X   0x011

◆ VO1_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK

#define VO1_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK   0x0000001f

◆ VO1_TCONLCD0_CLK_REG_FACTOR_M_OFFSET

#define VO1_TCONLCD0_CLK_REG_FACTOR_M_OFFSET   0

◆ VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLEAR_MASK

#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLEAR_MASK   0x80000000

◆ VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_OFF

#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_OFF   0x0

◆ VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_ON

#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_ON   0x1

◆ VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_OFFSET

#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_OFFSET   31
Generated by doxygen 1.9.8