sys-pwm.h

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/* SPDX-License-Identifier: GPL-2.0+ */
 
#ifndef __SYS_PWM_H__
#define __SYS_PWM_H__
 
#include <io.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
 
#include <sys-clk.h>
#include <sys-gpio.h>
 
#ifdef __cplusplus
extern "C" {
#endif// __cplusplus
 
typedef enum {
    PWM_PIER = 0x00, /* PWM IRQ enable register */
    PWM_PISR = 0x04, /* PWM IRQ status register */
    PWM_CIER = 0x10, /* PWM capture IRQ enable register */
    PWM_CISR = 0x14, /* PWM capture IRQ status register */
 
    PWM_PCCR_BASE = 0x20, /* Base address for PWM clock configuration registers */
    PWM_PCCR01 = 0x20,    /* PWM01 clock configuration register */
    PWM_PCCR23 = 0x24,    /* PWM23 clock configuration register */
    PWM_PCCR45 = 0x28,    /* PWM45 clock configuration register */
    PWM_PCCR67 = 0x2C,    /* PWM67 clock configuration register */
    PWM_PCCR89 = 0x30,    /* PWM89 clock configuration register */
    PWM_PCCRab = 0x34,    /* PWMab clock configuration register */
    PWM_PCCRcd = 0x38,    /* PWMcd clock configuration register */
    PWM_PCCRef = 0x3C,    /* PWMef clock configuration register */
 
    PWM_PCGR = 0x40, /* PWM Clock Gating Register */
 
    PWM_PDZCR_BASE = 0x60, /* Base address for PWM Dead Zone Control registers */
    PWM_PDZCR01 = 0x60,    /* PWM01 Dead Zone Control Register */
    PWM_PDZCR23 = 0x64,    /* PWM23 Dead Zone Control Register */
    PWM_PDZCR45 = 0x68,    /* PWM45 Dead Zone Control Register */
    PWM_PDZCR67 = 0x6C,    /* PWM67 Dead Zone Control Register */
    PWM_PDZCR89 = 0x70,    /* PWM89 Dead Zone Control Register */
    PWM_PDZCRab = 0x74,    /* PWMad Dead Zone Control Register */
    PWM_PDZCRcd = 0x78,    /* PWMcd Dead Zone Control Register */
    PWM_PDZCRef = 0x7C,    /* PWMef Dead Zone Control Register */
 
    PWM_PER = 0x80, /* PWM Enable Register */
 
    PWM_PGR0 = 0x90, /* PWM Group0 Register */
    PWM_PGR1 = 0x94, /* PWM Group1 Register */
    PWM_PGR2 = 0x98, /* PWM Group2 Register */
    PWM_PGR3 = 0x9C, /* PWM Group3 Register */
 
    PWM_CER = 0xC0, /* PWM Capture Enable Register */
 
    PWM_PCR = 0x0100,    /* PWM Control Register */
    PWM_PPR = 0x0104,    /* PWM Period Register */
    PWM_PCNTR = 0x0108,  /* PWM Counter Register */
    PWM_PPCNTR = 0x010C, /* PWM Pulse Counter Register */
    PWM_CCR = 0x0110,    /* Capture Control Register */
    PWM_CRLR = 0x0114,   /* Capture Rise Lock Register */
    PWM_CFLR = 0x0118,   /* Capture Fall Lock Register */
 
    PWM_VR = 0x03F0, /* PWM Version Register */
} sunxi_pwm_reg_offset_t;
 
#define PWM_REG_CHN_OFFSET 0x20
 
#define PWM_CLK_SRC_SHIFT 0x7
#define PWM_CLK_SRC_WIDTH 0x2
 
#define PWM_DIV_M_SHIFT 0x0
#define PWM_DIV_M_WIDTH 0x4
 
#define PWM_PRESCAL_SHIFT 0x0
#define PWM_PRESCAL_WIDTH 0x8
 
#define PWM_ACT_CYCLES_SHIFT 0x0
#define PWM_ACT_CYCLES_WIDTH 0x10
 
#define PWM_PERIOD_CYCLES_SHIFT 0x10
#define PWM_PERIOD_CYCLES_WIDTH 0x10
 
#define PWM_CLK_GATING_SHIFT 0x0
#define PWM_CLK_GATING_WIDTH 0x1
 
#define PWM_EN_CONTROL_SHIFT 0x0
#define PWM_EN_CONTORL_WIDTH 0x1
 
#define PWM_ACT_STA_SHIFT 0x8
#define PWM_ACT_STA_WIDTH 0x1
 
#define PWM_DZ_EN_SHIFT 0x0
#define PWM_DZ_EN_WIDTH 0x1
 
#define PWM_PDZINTV_SHIFT 0x8
#define PWM_PDZINTV_WIDTH 0x8
 
#define PWM_PULSE_SHIFT 0x9
#define PWM_PULSE_WIDTH 0x1
 
#define PWM_PULSE_NUM_SHIFT 0x10
#define PWM_PULSE_NUM_WIDTH 0x10
 
#define PWM_PULSE_START_SHIFT 0xa
#define PWM_PULSE_START_WIDTH 0x1
 
#define PWM_CLK_BYPASS_SHIFT 0x10
 
#define TIME_1_SECOND 1000000000
#define PWM_BIND_NUM (2)
 
typedef enum {
    PWM_MODE_CYCLE = 0, 
    PWM_MODE_PLUSE = 1, 
} sunxi_pwm_mode_t;
 
typedef enum {
    PWM_POLARITY_INVERSED = 0, 
    PWM_POLARITY_NORMAL = 1,   
} sunxi_pwm_polarity_t;
 
typedef enum {
    PWM_CLK_SRC_OSC = 0, 
    PWM_CLK_SRC_APB = 1, 
} sunxi_pwm_source_t;
 
typedef enum {
    PWM_CHANNEL_SINGLE = 0, 
    PWM_CHANNEL_BIND = 1,   
} sunxi_pwm_channel_mode_t;
 
typedef struct sunxi_pwm_channel {
    gpio_mux_t pin;                        
    uint32_t bind_channel;                 
    uint32_t dead_time;                    
    sunxi_pwm_channel_mode_t channel_mode; 
} sunxi_pwm_channel_t;
 
typedef struct sunxi_pwm_clk_src {
    uint32_t clk_src_hosc; 
    uint32_t clk_src_apb;  
} sunxi_pwm_clk_src_t;
 
typedef struct sunxi_pwm {
    uint32_t base;                
    uint8_t id;                   
    sunxi_pwm_channel_t *channel; 
    uint32_t channel_size;        
    sunxi_clk_t pwm_bus_clk;      
    sunxi_clk_t pwm_clk;          
    sunxi_pwm_clk_src_t clk_src;  
    bool status;                  
} sunxi_pwm_t;
 
typedef struct sunxi_pwm_config {
    uint32_t duty_ns;              
    uint32_t period_ns;            
    sunxi_pwm_polarity_t polarity; 
    sunxi_pwm_mode_t pwm_mode;     
    uint32_t pluse_count;          
} sunxi_pwm_config_t;
 
void sunxi_pwm_init(sunxi_pwm_t *pwm);
 
void sunxi_pwm_deinit(sunxi_pwm_t *pwm);
 
int sunxi_pwm_set_config(sunxi_pwm_t *pwm, int channel, sunxi_pwm_config_t *config);
 
int sunxi_pwm_release(sunxi_pwm_t *pwm, int channel);
 
#ifdef __cplusplus
}
#endif// __cplusplus
 
#endif//__SYS_PWM_H__