#include <io.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <sys-clk.h>
#include <sys-gpio.h>
Go to the source code of this file.
|
| enum | sunxi_pwm_reg_offset_t {
PWM_PIER = 0x00
, PWM_PISR = 0x04
, PWM_CIER = 0x10
, PWM_CISR = 0x14
,
PWM_PCCR_BASE = 0x20
, PWM_PCCR01 = 0x20
, PWM_PCCR23 = 0x24
, PWM_PCCR45 = 0x28
,
PWM_PCCR67 = 0x2C
, PWM_PCCR89 = 0x30
, PWM_PCCRab = 0x34
, PWM_PCCRcd = 0x38
,
PWM_PCCRef = 0x3C
, PWM_PCGR = 0x40
, PWM_PDZCR_BASE = 0x60
, PWM_PDZCR01 = 0x60
,
PWM_PDZCR23 = 0x64
, PWM_PDZCR45 = 0x68
, PWM_PDZCR67 = 0x6C
, PWM_PDZCR89 = 0x70
,
PWM_PDZCRab = 0x74
, PWM_PDZCRcd = 0x78
, PWM_PDZCRef = 0x7C
, PWM_PER = 0x80
,
PWM_PGR0 = 0x90
, PWM_PGR1 = 0x94
, PWM_PGR2 = 0x98
, PWM_PGR3 = 0x9C
,
PWM_CER = 0xC0
, PWM_PCR = 0x0100
, PWM_PPR = 0x0104
, PWM_PCNTR = 0x0108
,
PWM_PPCNTR = 0x010C
, PWM_CCR = 0x0110
, PWM_CRLR = 0x0114
, PWM_CFLR = 0x0118
,
PWM_VR = 0x03F0
} |
| |
| enum | sunxi_pwm_mode_t { PWM_MODE_CYCLE = 0
, PWM_MODE_PLUSE = 1
} |
| | PWM operation modes. More...
|
| |
| enum | sunxi_pwm_polarity_t { PWM_POLARITY_INVERSED = 0
, PWM_POLARITY_NORMAL = 1
} |
| | PWM signal polarity. More...
|
| |
| enum | sunxi_pwm_source_t { PWM_CLK_SRC_OSC = 0
, PWM_CLK_SRC_APB = 1
} |
| | PWM clock source. More...
|
| |
| enum | sunxi_pwm_channel_mode_t { PWM_CHANNEL_SINGLE = 0
, PWM_CHANNEL_BIND = 1
} |
| | PWM channel modes. More...
|
| |
◆ PWM_ACT_CYCLES_SHIFT
| #define PWM_ACT_CYCLES_SHIFT 0x0 |
◆ PWM_ACT_CYCLES_WIDTH
| #define PWM_ACT_CYCLES_WIDTH 0x10 |
◆ PWM_ACT_STA_SHIFT
| #define PWM_ACT_STA_SHIFT 0x8 |
◆ PWM_ACT_STA_WIDTH
| #define PWM_ACT_STA_WIDTH 0x1 |
◆ PWM_BIND_NUM
◆ PWM_CLK_BYPASS_SHIFT
| #define PWM_CLK_BYPASS_SHIFT 0x10 |
◆ PWM_CLK_GATING_SHIFT
| #define PWM_CLK_GATING_SHIFT 0x0 |
◆ PWM_CLK_GATING_WIDTH
| #define PWM_CLK_GATING_WIDTH 0x1 |
◆ PWM_CLK_SRC_SHIFT
| #define PWM_CLK_SRC_SHIFT 0x7 |
◆ PWM_CLK_SRC_WIDTH
| #define PWM_CLK_SRC_WIDTH 0x2 |
◆ PWM_DIV_M_SHIFT
| #define PWM_DIV_M_SHIFT 0x0 |
◆ PWM_DIV_M_WIDTH
| #define PWM_DIV_M_WIDTH 0x4 |
◆ PWM_DZ_EN_SHIFT
| #define PWM_DZ_EN_SHIFT 0x0 |
◆ PWM_DZ_EN_WIDTH
| #define PWM_DZ_EN_WIDTH 0x1 |
◆ PWM_EN_CONTORL_WIDTH
| #define PWM_EN_CONTORL_WIDTH 0x1 |
◆ PWM_EN_CONTROL_SHIFT
| #define PWM_EN_CONTROL_SHIFT 0x0 |
◆ PWM_PDZINTV_SHIFT
| #define PWM_PDZINTV_SHIFT 0x8 |
◆ PWM_PDZINTV_WIDTH
| #define PWM_PDZINTV_WIDTH 0x8 |
◆ PWM_PERIOD_CYCLES_SHIFT
| #define PWM_PERIOD_CYCLES_SHIFT 0x10 |
◆ PWM_PERIOD_CYCLES_WIDTH
| #define PWM_PERIOD_CYCLES_WIDTH 0x10 |
◆ PWM_PRESCAL_SHIFT
| #define PWM_PRESCAL_SHIFT 0x0 |
◆ PWM_PRESCAL_WIDTH
| #define PWM_PRESCAL_WIDTH 0x8 |
◆ PWM_PULSE_NUM_SHIFT
| #define PWM_PULSE_NUM_SHIFT 0x10 |
◆ PWM_PULSE_NUM_WIDTH
| #define PWM_PULSE_NUM_WIDTH 0x10 |
◆ PWM_PULSE_SHIFT
| #define PWM_PULSE_SHIFT 0x9 |
◆ PWM_PULSE_START_SHIFT
| #define PWM_PULSE_START_SHIFT 0xa |
◆ PWM_PULSE_START_WIDTH
| #define PWM_PULSE_START_WIDTH 0x1 |
◆ PWM_PULSE_WIDTH
| #define PWM_PULSE_WIDTH 0x1 |
◆ PWM_REG_CHN_OFFSET
| #define PWM_REG_CHN_OFFSET 0x20 |
◆ TIME_1_SECOND
| #define TIME_1_SECOND 1000000000 |
◆ sunxi_pwm_channel_t
PWM channel configuration.
This structure defines the configuration of a PWM channel. It includes the GPIO pin, the bind channel for multi-channel operation, the dead time between signal transitions, and the channel mode.
◆ sunxi_pwm_clk_src_t
PWM clock source configuration.
This structure holds the configuration of the clock sources for the PWM module. It contains fields for the oscillator and APB clock sources.
◆ sunxi_pwm_config_t
PWM configuration parameters.
This structure defines the parameters for configuring the PWM signal's behavior, including the duty cycle, period, polarity, operating mode, and pulse count.
◆ sunxi_pwm_t
Main PWM configuration structure.
This structure holds the complete configuration for the PWM module, including the base address, channel settings, clock source settings, and the module's operational status.
◆ sunxi_pwm_channel_mode_t
PWM channel modes.
This enum defines the operating modes for PWM channels.
- PWM_CHANNEL_SINGLE: Single-channel mode where each PWM channel operates independently.
- PWM_CHANNEL_BIND: Multi-channel bind mode where multiple channels can be synchronized.
| Enumerator |
|---|
| PWM_CHANNEL_SINGLE | Single-channel PWM mode.
|
| PWM_CHANNEL_BIND | Multi-channel bind mode.
|
◆ sunxi_pwm_mode_t
PWM operation modes.
This enum defines the modes of operation for the PWM signal.
- PWM_MODE_CYCLE: PWM signal operates in a continuous cycle.
- PWM_MODE_PLUSE: PWM signal generates a pulse waveform.
| Enumerator |
|---|
| PWM_MODE_CYCLE | PWM operates in cycle mode.
|
| PWM_MODE_PLUSE | PWM operates in pulse mode.
|
◆ sunxi_pwm_polarity_t
PWM signal polarity.
This enum defines the polarity of the PWM signal.
- PWM_POLARITY_INVERSED: Inverted polarity for the PWM signal.
- PWM_POLARITY_NORMAL: Normal polarity for the PWM signal.
| Enumerator |
|---|
| PWM_POLARITY_INVERSED | Inverted PWM signal polarity.
|
| PWM_POLARITY_NORMAL | Normal PWM signal polarity.
|
◆ sunxi_pwm_reg_offset_t
| Enumerator |
|---|
| PWM_PIER | |
| PWM_PISR | |
| PWM_CIER | |
| PWM_CISR | |
| PWM_PCCR_BASE | |
| PWM_PCCR01 | |
| PWM_PCCR23 | |
| PWM_PCCR45 | |
| PWM_PCCR67 | |
| PWM_PCCR89 | |
| PWM_PCCRab | |
| PWM_PCCRcd | |
| PWM_PCCRef | |
| PWM_PCGR | |
| PWM_PDZCR_BASE | |
| PWM_PDZCR01 | |
| PWM_PDZCR23 | |
| PWM_PDZCR45 | |
| PWM_PDZCR67 | |
| PWM_PDZCR89 | |
| PWM_PDZCRab | |
| PWM_PDZCRcd | |
| PWM_PDZCRef | |
| PWM_PER | |
| PWM_PGR0 | |
| PWM_PGR1 | |
| PWM_PGR2 | |
| PWM_PGR3 | |
| PWM_CER | |
| PWM_PCR | |
| PWM_PPR | |
| PWM_PCNTR | |
| PWM_PPCNTR | |
| PWM_CCR | |
| PWM_CRLR | |
| PWM_CFLR | |
| PWM_VR | |
◆ sunxi_pwm_source_t
PWM clock source.
This enum defines the available clock sources for the PWM module.
- PWM_CLK_SRC_OSC: Clock sourced from the oscillator.
- PWM_CLK_SRC_APB: Clock sourced from the APB bus.
| Enumerator |
|---|
| PWM_CLK_SRC_OSC | Clock source is the oscillator.
|
| PWM_CLK_SRC_APB | Clock source is the APB bus.
|
◆ sunxi_pwm_deinit()
Deinitialize the PWM instance.
This function deinitializes the PWM instance by deactivating the clocks and re-initializing the GPIOs for each channel. It also marks the PWM as uninitialized (status set to false).
- Parameters
-
| pwm | Pointer to the PWM instance structure. |
◆ sunxi_pwm_init()
Initialize the PWM instance.
This function initializes the PWM instance by setting up the necessary clocks and marking the PWM as initialized (status set to true).
- Parameters
-
| pwm | Pointer to the PWM instance structure. |
◆ sunxi_pwm_release()
| int sunxi_pwm_release |
( |
sunxi_pwm_t * |
pwm, |
|
|
int |
channel |
|
) |
| |
Release the PWM channel.
This function releases the specified PWM channel. It checks if the PWM is initialized, validates the channel index, and then either releases a bound channel or a single channel based on the current channel mode.
- Parameters
-
| pwm | Pointer to the PWM instance structure. |
| channel | The PWM channel to release (0-based index). |
- Returns
- 0 on success, -1 if an error occurs (e.g., PWM not initialized, invalid channel index).
◆ sunxi_pwm_set_config()
Set configuration for a PWM channel.
This function sets the configuration for the specified PWM channel. It checks if the PWM is initialized, validates the channel index, and then applies the configuration either for a bound channel or a single channel based on the current channel mode.
- Parameters
-
| pwm | Pointer to the PWM instance structure. |
| channel | The PWM channel to configure (0-based index). |
| config | Pointer to the PWM configuration structure containing the settings. |
- Returns
- 0 on success, -1 if an error occurs (e.g., PWM not initialized, invalid channel index).