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SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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Go to the source code of this file.
| #define CAL_ANA_EN (1) |
| #define CAL_EN (0) |
| #define GPIO_1_8V_MODE 1 |
| #define GPIO_3_3V_MODE 0 |
| #define GPIO_BIAS_MAIN_NAME "gpio_bias" |
| #define GPIO_BIAS_MAX_LEN (32) |
| #define GPIO_POW_MODE_REG (0x0340) |
| #define GPIO_POW_MODE_VAL_REG (0x0348) |
| #define PLL_LDO_REG (SUNXI_CPU_SUBSYS_CTRL_BASE + 0x144) |
| #define RES_CAL_CTRL_REG (SUNXI_RPRCM_BASE + 0X310) |
| #define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x44) |
| #define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x40) |
| #define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0) |
| #define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4) |
| #define SUNXI_AIPU_BASE 0x03050000 |
| #define SUNXI_AIPU_DBG_BASE 0x02074000 |
| #define SUNXI_APB_ROM1_BASE 0x08801000 |
| #define SUNXI_APB_ROM2_BASE 0x08841000 |
| #define SUNXI_ATB_FUNNEL_BASE 0x08843000 |
| #define SUNXI_AUDIO_SYS_BASE 0x02031000 |
| #define SUNXI_CCI_BASE 0x03700000 |
| #define SUNXI_CCMU_OS0__BASE 0x02002000 |
| #define SUNXI_CCMU_OS1__BASE 0x02004000 |
| #define SUNXI_CCU_BASE (SUNXI_CCMU_OS0__BASE) |
| #define SUNXI_CE_BASE (SUNXI_CE_NS_BASE) |
| #define SUNXI_CE_KEY_SRAM_BASE 0x03041400 |
| #define SUNXI_CE_NS_BASE 0x03040000 |
| #define SUNXI_CE_S_BASE 0x03040800 |
| #define SUNXI_CE_SYS_BASE 0x03040000 |
| #define SUNXI_CLUSTER_CFG_BASE 0x08860000 |
| #define SUNXI_CLUSTER_DBUG_BASE 0x09800000 |
| #define SUNXI_COMBPHY0_BASE 0x06C80000 |
| #define SUNXI_COMBPHY1_BASE 0x06CA0000 |
| #define SUNXI_CPU0_MSGBOX_OS0__BASE 0x03C42000 |
| #define SUNXI_CPU0_MSGBOX_OS1__BASE 0x03C43000 |
| #define SUNXI_CPU1_MSGBOX_OS0__BASE 0x03C44000 |
| #define SUNXI_CPU1_MSGBOX_OS1__BASE 0x03C45000 |
| #define SUNXI_CPU_GIC600_BASE 0x03400000 |
| #define SUNXI_CPU_PLL_CFG_BASE 0x08870000 |
| #define SUNXI_CPU_SUBSYS_CTRL_BASE 0x08000000 |
| #define SUNXI_CPUIDLE_BASE 0x07050000 |
| #define SUNXI_CPUS_BIST_BASE 0x07031000 |
| #define SUNXI_CPUS_CFG_BASE (0x07000400U) |
| #define SUNXI_CPUX_MSGBOX_BASE 0x03004000 |
| #define SUNXI_CPUXCFG_BASE (SUNXI_CPU_SUBSYS_CTRL_BASE) |
| #define SUNXI_CS_TS_CTRL_BASE 0x08805000 |
| #define SUNXI_CS_TS_READ_BASE 0x08807000 |
| #define SUNXI_CSI_BASE 0x05800000 |
| #define SUNXI_CTI_BASE 0x08803000 |
| #define SUNXI_DCU_BASE 0x03010000 |
| #define SUNXI_DE0_BASE 0x05000000 |
| #define SUNXI_DE1_BASE 0x0D000000 |
| #define SUNXI_DI_BASE 0x05400000 |
| #define SUNXI_DISPLAY0_TOP_BASE 0x05500000 |
| #define SUNXI_DISPLAY1_TOP_BASE 0x05510000 |
| #define SUNXI_DMA_BASE (SUNXI_DMAC_BASE) |
| #define SUNXI_DMAC1_OS0__BASE 0x03C46000 |
| #define SUNXI_DMAC1_OS1__BASE 0x03C47000 |
| #define SUNXI_DMAC_BASE (SUNXI_DMAC_OS0__BASE) |
| #define SUNXI_DMAC_OS0__BASE 0x03002000 |
| #define SUNXI_DMAC_OS1__BASE 0x03003000 |
| #define SUNXI_DSI0_BASE 0x05506000 |
| #define SUNXI_DSI1_BASE 0x05508000 |
| #define SUNXI_DSP0_DRAM0_BASE 0x00030000 |
| #define SUNXI_DSP0_DRAM0_LOCAL_SRAM__BASE 0x00420000 |
| #define SUNXI_DSP0_DRAM1_BASE 0x00038000 |
| #define SUNXI_DSP0_DRAM1_LOCAL_SRAM__BASE 0x00440000 |
| #define SUNXI_DSP0_IRAM_BASE 0x00020000 |
| #define SUNXI_DSP0_IRAM_LOCAL_SRAM__BASE 0x00400000 |
| #define SUNXI_DSP_CFG_BASE 0x07300000 |
| #define SUNXI_DSP_INTC_BASE 0x07302000 |
| #define SUNXI_DSP_MSGBOX_BASE 0x07320000 |
| #define SUNXI_DSP_TIMER_BASE 0x07323000 |
| #define SUNXI_DSP_TZMA_BASE 0x07303000 |
| #define SUNXI_DSP_WDG_BASE 0x07301000 |
| #define SUNXI_EDP0_BASE 0x05720000 |
| #define SUNXI_ETB_BASE 0x0880B000 |
| #define SUNXI_FIXS_BROM_BASE 0x00000000 |
| #define SUNXI_G2D_BASE 0x05440000 |
| #define SUNXI_GATING_BIT (0) |
| #define SUNXI_GIC600_BASE (SUNXI_CPU_GIC600_BASE) |
| #define SUNXI_GMAC0_BASE 0x04500000 |
| #define SUNXI_GMAC1_BASE 0x04510000 |
| #define SUNXI_GPADC1_BASE 0x0200C000 |
| #define SUNXI_GPADC_BASE 0x02009000 |
| #define SUNXI_GPIO_OS0__BASE 0x02000000 |
| #define SUNXI_GPIO_OS1__BASE 0x02001000 |
| #define SUNXI_GPU0_BASE 0x01800000 |
| #define SUNXI_HDMI_BASE 0x05520000 |
| #define SUNXI_HS_BROM_BASE 0x00011000 |
| #define SUNXI_I2S1_BASE 0x02031000 |
| #define SUNXI_I2S2_BASE 0x02032000 |
| #define SUNXI_I2S3_BASE 0x02033000 |
| #define SUNXI_I2S4_BASE 0x02034000 |
| #define SUNXI_I2S5_BASE 0x02035000 |
| #define SUNXI_IRRX_BASE 0x02076000 |
| #define SUNXI_IRTX_BASE 0x02075000 |
| #define SUNXI_ISP_BASE 0x05900000 |
| #define SUNXI_KEYSRAM_DEBUG_BASE 0x03042400 |
| #define SUNXI_LBC_BASE 0x02600000 |
| #define SUNXI_LBC_DIRECT_BASE 0x10000000 |
| #define SUNXI_LEDC_BASE 0x02008000 |
| #define SUNXI_LRADC0_BASE 0x0200B000 |
| #define SUNXI_MCU_DMA_OS0__BASE 0x07150000 |
| #define SUNXI_MCU_DMA_OS1__BASE 0x07151000 |
| #define SUNXI_MCU_DMIC_BASE 0x07144000 |
| #define SUNXI_MCU_I2S_BASE 0x07143000 |
| #define SUNXI_MCU_PRCM_BASE 0x07140000 |
| #define SUNXI_MCU_SPINLOCK_BASE 0x07152000 |
| #define SUNXI_MCU_SRAM0_BASE 0x07200000 |
| #define SUNXI_MCU_SRAM1_BASE 0x07280000 |
| #define SUNXI_MCU_TZMA0_BASE 0x07141000 |
| #define SUNXI_MCU_TZMA1_BASE 0x07142000 |
| #define SUNXI_MEMC0_BASE 0x0A000000 |
| #define SUNXI_MMC0_BASE (SUNXI_SMHC0_BASE) |
| #define SUNXI_MMC1_BASE (SUNXI_SMHC1_BASE) |
| #define SUNXI_MMC2_BASE (SUNXI_SMHC2_BASE) |
| #define SUNXI_MSI_LITE0_BASE 0x03800000 |
| #define SUNXI_MSI_LITE1_BASE 0x03801000 |
| #define SUNXI_MSI_LITE2_BASE 0x07153000 |
| #define SUNXI_NAND_BASE 0x04011000 |
| #define SUNXI_NPD_BASE 0x02070000 |
| #define SUNXI_NPU_BASE 0x03600000 |
| #define SUNXI_NPU_MEM_BASE 0x01700000 |
| #define SUNXI_NPU_TZMA_BASE 0x02073000 |
| #define SUNXI_NS_BROM_BASE 0x00017000 |
| #define SUNXI_NSI_BASE 0x02020000 |
| #define SUNXI_NSI_CPU0_BASE 0x02071000 |
| #define SUNXI_NSI_SBR_BASE 0x02072000 |
| #define SUNXI_PCIE0_BASE 0x06000000 |
| #define SUNXI_PCIE1_BASE 0x06500000 |
| #define SUNXI_PCIE_SLV0_BASE 0x20000000 |
| #define SUNXI_PCIE_SLV1_BASE 0x28000000 |
| #define SUNXI_PCK600_QCHANNEL_BASE 0x07060000 |
| #define SUNXI_PIO_BASE (SUNXI_GPIO_OS0__BASE) |
| #define SUNXI_PWM0_BASE 0x02052000 |
| #define SUNXI_PWM1_BASE 0x02053000 |
| #define SUNXI_R_GPIO_OS0__BASE 0x07025000 |
| #define SUNXI_R_GPIO_OS1__BASE 0x07026000 |
| #define SUNXI_R_INTC_BASE 0x07024000 |
| #define SUNXI_R_IRRX_BASE 0x07040000 |
| #define SUNXI_R_MBOX_BASE 0x07094000 |
| #define SUNXI_R_PIO_BASE (SUNXI_R_GPIO_OS0__BASE) |
| #define SUNXI_R_PRCM_BASE 0x07010000 |
| #define SUNXI_R_PWM_BASE 0x07023000 |
| #define SUNXI_R_SPC_BASE 0x07002000 |
| #define SUNXI_R_SPI_BASE 0x07092000 |
| #define SUNXI_R_TIMER_BASE 0x07091000 |
| #define SUNXI_R_TWD_BASE 0x07022000 |
| #define SUNXI_R_TWI0_BASE 0x07083000 |
| #define SUNXI_R_TWI1_BASE 0x07084000 |
| #define SUNXI_R_TWI2_BASE 0x07085000 |
| #define SUNXI_R_TZMA_BASE 0x07003000 |
| #define SUNXI_R_UART0_BASE 0x07080000 |
| #define SUNXI_R_UART1_BASE 0x07081000 |
| #define SUNXI_R_UART2_BASE 0x07082000 |
| #define SUNXI_R_WDG_BASE 0x07021000 |
| #define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE) |
| #define SUNXI_RISCV 0XE0000000 |
| #define SUNXI_RISCV_CFG_BASE 0x07130000 |
| #define SUNXI_RISCV_CLIC_BASE 0xE0800000 |
| #define SUNXI_RISCV_CLINT_BASE 0xE0000000 |
| #define SUNXI_RISCV_LCNT_BASE 0x07134000 |
| #define SUNXI_RISCV_MBOX_BASE 0x07136000 |
| #define SUNXI_RISCV_SYSMAP_BASE 0xEFFFF000 |
| #define SUNXI_RISCV_TIMER_BASE 0x07138000 |
| #define SUNXI_RISCV_WDG_BASE 0x07132000 |
| #define SUNXI_RPIO_BASE (SUNXI_R_GPIO_OS0__BASE) |
| #define SUNXI_RPRCM_BASE (SUNXI_R_PRCM_BASE) |
| #define SUNXI_RPWM_BASE (SUNXI_R_PWM_BASE) |
| #define SUNXI_RST_BIT (16) |
| #define SUNXI_RTC_BASE 0x07090000 |
| #define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) |
| #define SUNXI_RTWI0_GATING_BIT (0) |
| #define SUNXI_RTWI0_RST_BIT (16) |
| #define SUNXI_RTWI_BASE (SUNXI_R_TWI0_BASE) |
| #define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c) |
| #define SUNXI_SECURE_DEBUG_CFG_BASE 0x03042000 |
| #define SUNXI_SERDES_SYS_BASE 0x06C00000 |
| #define SUNXI_SID_BASE 0x03006000 |
| #define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200) |
| #define SUNXI_SMHC0_BASE 0x04020000 |
| #define SUNXI_SMHC1_BASE 0x04021000 |
| #define SUNXI_SMHC2_BASE 0x04022000 |
| #define SUNXI_SMHC3_BASE 0x04023000 |
| #define SUNXI_SMMU_BASE 0x03900000 |
| #define SUNXI_SOC_VER_MASK (0x7) |
| #define SUNXI_SOC_VER_REG (SUNXI_SYSCTRL_BASE + 0x24) |
| #define SUNXI_SPC_BASE 0x02054000 |
| #define SUNXI_SPDIF0_BASE 0x02036000 |
| #define SUNXI_SPI0_BASE 0x04025000 |
| #define SUNXI_SPI1_BASE 0x04026000 |
| #define SUNXI_SPI2_BASE 0x04027000 |
| #define SUNXI_SPI_FLASH_BASE 0x047F0000 |
| #define SUNXI_SPI_FLASH_XIP_BASE 0x0E000000 |
| #define SUNXI_SPINLOCK_BASE 0x03005000 |
| #define SUNXI_SRAM_A2_BASE 0x00044000 |
| #define SUNXI_SS_BASE (SUNXI_CE_BASE) |
| #define SUNXI_SYSCRL_BASE (SUNXI_SYSCTRL_BASE) |
| #define SUNXI_SYSCTRL_BASE 0x03000000 |
| #define SUNXI_TCON_LCD0_BASE 0x05501000 |
| #define SUNXI_TCON_LCD1_BASE 0x05502000 |
| #define SUNXI_TCON_LCD2_BASE 0x05503000 |
| #define SUNXI_TCON_LCD3_BASE 0x05504000 |
| #define SUNXI_TCON_TV0_BASE 0x05730000 |
| #define SUNXI_TCON_TV1_BASE 0x05731000 |
| #define SUNXI_TCON_TV2_BASE 0x05732000 |
| #define SUNXI_THS_BASE 0x0200A000 |
| #define SUNXI_TIMER0_BASE 0x03009000 |
| #define SUNXI_TIMER1_BASE 0x0300A000 |
| #define SUNXI_TIMER_BASE (SUNXI_TIMER0_BASE) |
| #define SUNXI_TIMESTAMP_CTRL_BASE 0x08020000 |
| #define SUNXI_TIMESTAMP_STA_BASE 0x08010000 |
| #define SUNXI_TPIU_BASE 0x08809000 |
| #define SUNXI_TWI0_BASE 0x02700000 |
| #define SUNXI_TWI1_BASE 0x02701000 |
| #define SUNXI_TWI2_BASE 0x02702000 |
| #define SUNXI_TWI3_BASE 0x02703000 |
| #define SUNXI_TWI4_BASE 0x02704000 |
| #define SUNXI_TWI5_BASE 0x02705000 |
| #define SUNXI_TWI6_BASE 0x02706000 |
| #define SUNXI_TWI7_BASE 0x02707000 |
| #define SUNXI_TWI8_BASE 0x02708000 |
| #define SUNXI_UART0_BASE 0x02500000 |
| #define SUNXI_UART1_BASE 0x02501000 |
| #define SUNXI_UART2_BASE 0x02502000 |
| #define SUNXI_UART3_BASE 0x02503000 |
| #define SUNXI_UART4_BASE 0x02504000 |
| #define SUNXI_UART5_BASE 0x02505000 |
| #define SUNXI_UART6_BASE 0x02506000 |
| #define SUNXI_UART7_BASE 0x02507000 |
| #define SUNXI_UART8_BASE 0x02508000 |
| #define SUNXI_UFS_BASE 0x04520000 |
| #define SUNXI_USB0_BASE 0x04100000 |
| #define SUNXI_USB1_BASE 0x04200000 |
| #define SUNXI_USB2_BASE 0x04300000 |
| #define SUNXI_USB3_1_BASE 0x06A00000 |
| #define SUNXI_USBOTG_BASE (SUNXI_USB0_BASE) |
| #define SUNXI_VE_DEC_BASE 0x01C0E000 |
| #define SUNXI_VE_ENC0_BASE 0x01C10000 |
| #define SUNXI_VE_ENC1_BASE 0x01C11000 |
| #define SUNXI_WDT0_BASE 0x02050000 |
| #define SUNXI_WDT1_BASE 0x02051000 |
| #define VDD_ADDA_OFF_GATING (9) |
| #define VDD_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x250) |
1.9.8