sys-sdhci.h

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/* SPDX-License-Identifier: GPL-2.0+ */
 
#ifndef _SYS_SDHCI_H_
#define _SYS_SDHCI_H_
 
#include <io.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
 
#include <reg/reg-smhc.h>
#include <sys-gpio.h>
 
#include <log.h>
 
#include "sys-mmc.h"
 
#ifdef __cplusplus
extern "C" {
#endif// __cplusplus
 
#define SMHC_DES_NUM_SHIFT 12 /* smhc2!! */
#define SMHC_DES_BUFFER_MAX_LEN (1 << SMHC_DES_NUM_SHIFT)
 
#define MMC_REG_FIFO_OS (0x200)
 
#define SMHC_TIMEOUT 0xfffff
#define SMHC_DMA_TIMEOUT 0xffffff
#define SMHC_WAITBUSY_TIMEOUT 0xfffff
#define SMHC_DATA_TIMEOUT 0xfffff
#define SMHC_RESP_TIMEOUT 0xff
 
enum {
    MMC_CONTROLLER_0 = 0,
    MMC_CONTROLLER_1 = 1,
    MMC_CONTROLLER_2 = 2,
};
 
typedef enum {
    MMC_TYPE_SD,
    MMC_TYPE_EMMC,
} sunxi_sdhci_type_t;
 
typedef struct sunxi_sdhci_desc {
    uint32_t : 1, dic : 1,   /* disable interrupt on completion */
            last_desc : 1,   /* 1-this data buffer is the last buffer */
            first_desc : 1,  /* 1-data buffer is the first buffer, 0-data buffer contained in the next descriptor is 1st buffer */
            des_chain : 1,   /* 1-the 2nd address in the descriptor is the next descriptor address */
            end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */
            : 24,            /* Reserved */
            err_flag : 1,    /* transfer error flag */
            own : 1;         /* des owner:1-idma owns it, 0-host owns it */
 
    uint32_t data_buf_sz : 16, data_buf_dummy : 16;
    uint32_t buf_addr;
    uint32_t next_desc_addr;
} sunxi_sdhci_desc_t __attribute__((aligned(8)));
 
typedef struct sunxi_sdhci_host {
    sdhci_reg_t *reg;
    uint32_t commreg;
    uint8_t fatal_err;
    uint8_t timing_mode;
 
    /* DMA DESC */
    sunxi_sdhci_desc_t *sdhci_desc;
} sunxi_sdhci_host_t;
 
typedef struct sunxi_sdhci_pinctrl {
    gpio_mux_t gpio_d0;
    gpio_mux_t gpio_d1;
    gpio_mux_t gpio_d2;
    gpio_mux_t gpio_d3;
    gpio_mux_t gpio_d4;
    gpio_mux_t gpio_d5;
    gpio_mux_t gpio_d6;
    gpio_mux_t gpio_d7;
    gpio_mux_t gpio_cmd;
    gpio_mux_t gpio_clk;
    gpio_mux_t gpio_ds;
    gpio_mux_t gpio_rst;
    gpio_mux_t gpio_cd;
    uint8_t cd_level;
} sunxi_sdhci_pinctrl_t;
 
typedef struct sunxi_sdhci_timing {
    uint32_t odly;
    uint32_t sdly;
    uint8_t auto_timing;
} sunxi_sdhci_timing_t;
 
typedef struct sunxi_sdhci_clk {
    uint32_t reg_base;
    uint8_t factor_n;
    uint8_t reg_factor_n_offset;
    uint8_t factor_m;
    uint8_t reg_factor_m_offset;
    uint8_t clk_sel;
    uint32_t parent_clk;
} sunxi_sdhci_clk_t;
 
typedef struct sunxi_sdhci {
    char *name;
    uint32_t reg_base;
    uint32_t id;
    uint32_t width;
    sunxi_clk_t clk_ctrl;
    sunxi_sdhci_clk_t sdhci_clk;
    uint32_t max_clk;
    uint32_t dma_des_addr;
    sunxi_sdhci_type_t sdhci_mmc_type;
 
    /* Pinctrl info */
    sunxi_sdhci_pinctrl_t pinctrl;
 
    /* Private data */
    mmc_t *mmc;
    sunxi_sdhci_host_t *mmc_host;
    sunxi_sdhci_timing_t *timing_data;
} sunxi_sdhci_t;
 
#define SDHCI_DEFAULT_CLK_RST_OFFSET(x) (16 + x)
#define SDHCI_DEFAULT_CLK_GATE_OFFSET(x) (x)
#define SDHCI_DEFAULT_CLK_FACTOR_M_OFFSET (0)
#define SDHCI_DEFAULT_CLK_FACTOR_N_OFFSET (8)
 
int sunxi_sdhci_init(sunxi_sdhci_t *sdhci);
 
int sunxi_sdhci_core_init(sunxi_sdhci_t *sdhci);
 
void sunxi_sdhci_set_ios(sunxi_sdhci_t *sdhci);
 
int sunxi_sdhci_update_phase(sunxi_sdhci_t *sdhci);
 
int sunxi_sdhci_xfer(sunxi_sdhci_t *sdhci, mmc_cmd_t *cmd, mmc_data_t *data);
 
void sunxi_sdhci_dump_reg(sunxi_sdhci_t *sdhci);
 
/* Internal Use */
extern int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz);
 
extern uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci);
 
#ifdef __cplusplus
}
#endif// __cplusplus
 
#endif// _SYS_SDHCI_H_