103#define SPI_CLK_SEL_PERIPH_300M (0x1)
104#define SPI_CLK_SEL_PERIPH_200M (0x2)
105#define SPI_CLK_SEL_FACTOR_N_OFF (8)
106#define SPI_DEFAULT_CLK_RST_OFFSET(x) (x + 16)
107#define SPI_DEFAULT_CLK_GATE_OFFSET(x) (x)
u32_t uint32_t
Definition stdint.h:13
u8_t uint8_t
Definition stdint.h:7
SPI Clock Configuration Structure.
Definition sys-spi.h:79
uint32_t spi_clock_cfg_base
Base address of the SPI clock configuration.
Definition sys-spi.h:80
spi_clk_cdr_mode_t cdr_mode
Clock mode.
Definition sys-spi.h:84
uint32_t spi_clock_factor_n_offset
Clock factor offset.
Definition sys-spi.h:82
uint32_t spi_clock_source
Source of the SPI clock.
Definition sys-spi.h:81
uint32_t spi_clock_freq
SPI clock frequency.
Definition sys-spi.h:83
SPI GPIO Configuration Structure.
Definition sys-spi.h:65
gpio_mux_t gpio_cs
Chip Select GPIO pin.
Definition sys-spi.h:66
gpio_mux_t gpio_wp
Write Protect GPIO pin.
Definition sys-spi.h:70
gpio_mux_t gpio_miso
Master In Slave Out (MISO) GPIO pin.
Definition sys-spi.h:68
gpio_mux_t gpio_sck
SPI Clock (SCK) GPIO pin.
Definition sys-spi.h:67
gpio_mux_t gpio_mosi
Master Out Slave In (MOSI) GPIO pin.
Definition sys-spi.h:69
gpio_mux_t gpio_hold
Hold GPIO pin.
Definition sys-spi.h:71
SPI Device Configuration Structure.
Definition sys-spi.h:92
uint32_t base
Base address of the SPI peripheral.
Definition sys-spi.h:93
uint8_t id
SPI device ID.
Definition sys-spi.h:94
uint32_t clk_rate
Clock rate for the SPI device.
Definition sys-spi.h:95
sunxi_clk_t parent_clk_reg
Parent clock register configuration.
Definition sys-spi.h:98
sunxi_spi_gpio_t gpio
GPIO configuration for the SPI device.
Definition sys-spi.h:96
sunxi_spi_clk_t spi_clk
SPI clock configuration.
Definition sys-spi.h:99
sunxi_dma_t * dma_handle
DMA handle for the SPI device.
Definition sys-spi.h:97
int sunxi_spi_update_clk(sunxi_spi_t *spi, uint32_t clk)
Updates the SPI clock rate.
Definition sys-spi.c:933
int sunxi_spi_transfer(sunxi_spi_t *spi, spi_io_mode_t mode, void *txbuf, uint32_t txlen, void *rxbuf, uint32_t rxlen)
Performs SPI data transfer.
Definition sys-spi.c:958
int sunxi_spi_init(sunxi_spi_t *spi)
Initializes the SPI interface.
Definition sys-spi.c:893
spi_io_mode_t
SPI Input/Output Mode Enumeration.
Definition sys-spi.h:30
@ SPI_IO_DUAL_RX
Dual I/O mode, using two data lines for receiving.
Definition sys-spi.h:32
@ SPI_IO_SINGLE
Single I/O mode, using one data line.
Definition sys-spi.h:31
@ SPI_IO_QUAD_RX
Quad I/O mode, using four data lines for receiving.
Definition sys-spi.h:33
@ SPI_IO_QUAD_IO
Quad I/O mode, using four data lines for both transmitting and receiving.
Definition sys-spi.h:34
spi_clk_cdr_mode_t
SPI Clock CDR Mode Enumeration.
Definition sys-spi.h:54
@ SPI_CDR1_MODE
Clock Data Recovery mode 1.
Definition sys-spi.h:55
@ SPI_CDR2_MODE
Clock Data Recovery mode 2.
Definition sys-spi.h:56
@ SPI_CDR_NONE
No Clock Data Recovery mode.
Definition sys-spi.h:57
void sunxi_spi_disable(sunxi_spi_t *spi)
Disables the SPI interface.
Definition sys-spi.c:916
spi_speed_mode_t
SPI Speed Mode Enumeration.
Definition sys-spi.h:42
@ SPI_MOD_FREQUENCY
Medium frequency: 50 MHz.
Definition sys-spi.h:44
@ SPI_HIGH_FREQUENCY
High frequency: 60 MHz.
Definition sys-spi.h:45
@ SPI_LOW_FREQUENCY
Low frequency: 24 MHz.
Definition sys-spi.h:43
@ SPI_MAX_FREQUENCY
Maximum frequency: 100 MHz.
Definition sys-spi.h:46