|
| enum | {
SPI_GCR = 0x04
, SPI_TCR = 0x08
, SPI_IER = 0x10
, SPI_ISR = 0x14
,
SPI_FCR = 0x18
, SPI_FSR = 0x1c
, SPI_WCR = 0x20
, SPI_CCR = 0x24
,
SPI_DLY = 0x28
, SPI_MBC = 0x30
, SPI_MTC = 0x34
, SPI_BCC = 0x38
,
SPI_TXD = 0x200
, SPI_RXD = 0x300
} |
| |
| enum | {
SPI_GCR_SRST_POS = 31
, SPI_GCR_SRST_MSK = (1 << SPI_GCR_SRST_POS)
, SPI_GCR_TPEN_POS = 7
, SPI_GCR_TPEN_MSK = (1 << SPI_GCR_TPEN_POS)
,
SPI_GCR_MODE_POS = 1
, SPI_GCR_MODE_MSK = (1 << SPI_GCR_MODE_POS)
, SPI_GCR_EN_POS = 0
, SPI_GCR_EN_MSK = (1 << SPI_GCR_EN_POS)
} |
| |
| enum | {
SPI_BCC_DUAL_RX = (1 << 28)
, SPI_BCC_QUAD_IO = (1 << 29)
, SPI_BCC_STC_MSK = (0x00ffffff)
, SPI_BCC_DUM_POS = 24
,
SPI_BCC_DUM_MSK = (0xf << SPI_BCC_DUM_POS)
} |
| |
| enum | { SPI_MBC_CNT_MSK = (0x00ffffff)
} |
| |
| enum | { SPI_MTC_CNT_MSK = (0x00ffffff)
} |
| |
| enum | {
SPI_TCR_SPOL_POS = 2
, SPI_TCR_SPOL_MSK = (1 << SPI_TCR_SPOL_POS)
, SPI_TCR_SS_OWNER_POS = 6
, SPI_TCR_SS_OWNER_MSK = (1 << SPI_TCR_SS_OWNER_POS)
,
SPI_TCR_DHB_POS = 8
, SPI_TCR_DHB_MSK = (1 << SPI_TCR_DHB_POS)
, SPI_TCR_SDC_POS = 11
, SPI_TCR_SDC_MSK = (1 << SPI_TCR_SDC_POS)
,
SPI_TCR_SDM_POS = 13
, SPI_TCR_SDM_MSK = (1 << SPI_TCR_SDM_POS)
} |
| |
| enum | {
SPI_FCR_RX_LEVEL_POS = 0
, SPI_FCR_RX_LEVEL_MSK = (0xff < SPI_FCR_RX_LEVEL_POS)
, SPI_FCR_RX_DRQEN_POS = 8
, SPI_FCR_RX_DRQEN_MSK = (0x1 << SPI_FCR_RX_DRQEN_POS)
,
SPI_FCR_RX_TESTEN_POS = 14
, SPI_FCR_RX_TESTEN_MSK = (0x1 << SPI_FCR_RX_TESTEN_POS)
, SPI_FCR_RX_RST_POS = 15
, SPI_FCR_RX_RST_MSK = (0x1 << SPI_FCR_RX_RST_POS)
,
SPI_FCR_TX_LEVEL_POS = 16
, SPI_FCR_TX_LEVEL_MSK = (0xff << SPI_FCR_TX_LEVEL_POS)
, SPI_FCR_TX_DRQEN_POS = 24
, SPI_FCR_TX_DRQEN_MSK = (0x1 << SPI_FCR_TX_DRQEN_POS)
,
SPI_FCR_TX_TESTEN_POS = 30
, SPI_FCR_TX_TESTEN_MSK = (0x1 << SPI_FCR_TX_TESTEN_POS)
, SPI_FCR_TX_RST_POS = 31
, SPI_FCR_TX_RST_MSK = (0x1 << SPI_FCR_TX_RST_POS)
} |
| |
| enum | { SPI_FSR_RF_CNT_POS = 0
, SPI_FSR_RF_CNT_MSK = (0xff << SPI_FSR_RF_CNT_POS)
, SPI_FSR_TF_CNT_POS = 16
, SPI_FSR_TF_CNT_MSK = (0xff << SPI_FSR_TF_CNT_POS)
} |
| |
|
| static uint32_t | sunxi_spi_set_clk (sunxi_spi_t *spi, u32 spi_clk, u32 mclk, u32 cdr2) |
| |
| static int | spi_clk_init (sunxi_spi_t *spi, uint32_t mod_clk) |
| |
| static void | spi_reset_fifo (sunxi_spi_t *spi) |
| |
| static uint32_t | spi_query_txfifo (sunxi_spi_t *spi) |
| |
| static uint32_t | spi_query_rxfifo (sunxi_spi_t *spi) |
| |
| static int | spi_dma_cfg (void) |
| |
| static int | spi_dma_init (void) |
| |
| static void | sunxi_spi_gpio_init (sunxi_spi_t *spi) |
| |
| static int | sunxi_spi_get_clk (sunxi_spi_t *spi) |
| |
| int | sunxi_spi_init (sunxi_spi_t *spi) |
| | Initializes the SPI interface.
|
| |
| void | sunxi_spi_disable (sunxi_spi_t *spi) |
| | Disables the SPI interface.
|
| |
| static void | spi_set_counters (sunxi_spi_t *spi, int txlen, int rxlen, int stxlen, int dummylen) |
| |
| static void | spi_write_tx_fifo (sunxi_spi_t *spi, uint8_t *buf, uint32_t len) |
| |
| static uint32_t | spi_read_rx_fifo (sunxi_spi_t *spi, uint8_t *buf, uint32_t len) |
| |
| static void | spi_set_io_mode (sunxi_spi_t *spi, spi_io_mode_t mode) |
| |
| int | sunxi_spi_transfer (sunxi_spi_t *spi, spi_io_mode_t mode, void *txbuf, uint32_t txlen, void *rxbuf, uint32_t rxlen) |
| | Performs SPI data transfer.
|
| |
Initializes the SPI interface.
This function initializes the SPI interface by configuring the GPIO pins, clock, bus, and counters. If a DMA handle is set, DMA mode is used for data transfers. The function calls several other SPI initialization functions to set up the SPI hardware.
- Parameters
-
| spi | Pointer to the SPI structure containing configuration and register information. |
- Returns
- 0 on success.