SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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Functions | Variables
board.c File Reference
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <log.h>
#include <common.h>
#include <reg-ncat.h>
#include <sys-clk.h>
#include <mmu.h>
#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-sdcard.h>
#include <sys-spi.h>
#include <sys-uart.h>
Include dependency graph for board.c:

Functions

void clean_syterkit_data (void)
 

Variables

sunxi_serial_t uart_dbg
 
sunxi_spi_t sunxi_spi0
 
sdhci_t sdhci0
 
dram_para_t dram_para
 

Function Documentation

◆ clean_syterkit_data()

void clean_syterkit_data ( void  )

Variable Documentation

◆ dram_para

dram_para_t dram_para
Initial value:
= {
.dram_clk = 792,
.dram_type = 3,
.dram_zq = 0x7b7bfb,
.dram_odt_en = 0x01,
.dram_para1 = 0x000010d2,
.dram_para2 = 0,
.dram_mr0 = 0x1c70,
.dram_mr1 = 0x42,
.dram_mr2 = 0x18,
.dram_mr3 = 0,
.dram_tpr0 = 0x004a2195,
.dram_tpr1 = 0x02423190,
.dram_tpr2 = 0x0008b061,
.dram_tpr3 = 0xb4787896,
.dram_tpr4 = 0,
.dram_tpr5 = 0x48484848,
.dram_tpr6 = 0x00000048,
.dram_tpr7 = 0x1620121e,
.dram_tpr8 = 0,
.dram_tpr9 = 0,
.dram_tpr10 = 0,
.dram_tpr11 = 0x00770000,
.dram_tpr12 = 0x00000002,
.dram_tpr13 = 0x34050100,
}

◆ sdhci0

sdhci_t sdhci0
Initial value:
= {
.name = "sdhci0",
.id = 0,
.reg = (sdhci_reg_t *) 0x04020000,
.voltage = MMC_VDD_27_36,
.width = MMC_BUS_WIDTH_4,
.clock = MMC_CLK_50M,
.removable = 0,
.isspi = FALSE,
.skew_auto_mode = TRUE,
.gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2},
.gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2},
}
#define CCU_MMC_CTRL_PLL_PERIPH1X
Definition reg-ccu.h:83
#define TRUE
Definition common.h:25
#define FALSE
Definition common.h:24
@ MMC_BUS_WIDTH_4
Definition sys-sdcard.h:141
@ MMC_VDD_27_36
Definition sys-sdcard.h:135
Definition reg-smhc.h:186
@ GPIO_PORTF
Definition sys-gpio.h:44
@ GPIO_PERIPH_MUX2
Definition sys-gpio.h:22
#define GPIO_PIN(x, y)
Definition sys-gpio.h:66
@ MMC_CLK_50M
Definition sys-mmc.h:289

◆ sunxi_spi0

sunxi_spi_t sunxi_spi0
Initial value:
= {
.base = SUNXI_SPI0_BASE,
.id = 0,
.clk_rate = 75 * 1000 * 1000,
.gpio =
{
.gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
.gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
.gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
.gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
},
}
#define SUNXI_SPI0_BASE
Definition reg-ncat.h:40
@ GPIO_PORTC
Definition sys-gpio.h:41
@ GPIO_PERIPH_MUX4
Definition sys-gpio.h:24

◆ uart_dbg

sunxi_serial_t uart_dbg
Initial value:
= {
.id = 0,
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin =
{
},
.uart_clk =
{
.gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0),
},
}
#define CCU_UART_BGR_REG
Definition reg-ccu.h:70
#define CCU_BASE
Definition reg-ccu.h:8
#define SUNXI_UART0_BASE
Definition reg-ncat.h:32
@ UART_STOP_BIT_0
Definition sys-uart.h:41
@ UART_BAUDRATE_115200
Definition sys-uart.h:24
#define SERIAL_DEFAULT_PARENT_CLK
Definition sys-uart.h:99
#define SERIAL_DEFAULT_CLK_RST_OFFSET(x)
Definition sys-uart.h:96
@ UART_PARITY_NO
Definition sys-uart.h:34
@ UART_DLEN_8
Definition sys-uart.h:50
#define SERIAL_DEFAULT_CLK_GATE_OFFSET(x)
Definition sys-uart.h:97
@ GPIO_PORTB
Definition sys-gpio.h:40
@ GPIO_PERIPH_MUX6
Definition sys-gpio.h:26