SyterKit 0.4.0.x
SyterKit is a bare-metal framework
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Functions | Variables
board.c File Reference
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <log.h>
#include <common.h>
#include <reg-ncat.h>
#include <sys-clk.h>
#include <mmu.h>
#include <mmc/sys-sdhci.h>
#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-i2c.h>
#include <sys-sdcard.h>
#include <sys-sid.h>
#include <sys-spi.h>
#include <sys-uart.h>
Include dependency graph for board.c:

Functions

int sunxi_nsi_init (void)
 
void neon_enable (void)
 
void clean_syterkit_data (void)
 
void show_chip ()
 

Variables

sunxi_serial_t uart_dbg
 
sunxi_i2c_t i2c_pmu
 
sunxi_sdhci_t sdhci0
 
uint32_t dram_para [128]
 

Function Documentation

◆ clean_syterkit_data()

void clean_syterkit_data ( void  )

◆ neon_enable()

void neon_enable ( void  )

◆ show_chip()

void show_chip ( )

◆ sunxi_nsi_init()

int sunxi_nsi_init ( void  )

Variable Documentation

◆ dram_para

uint32_t dram_para[128]

◆ i2c_pmu

sunxi_i2c_t i2c_pmu
Initial value:
= {
.base = SUNXI_RTWI_BASE,
.id = SUNXI_R_I2C0,
.gpio =
{
.gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2},
.gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2},
},
.i2c_clk =
{
.gate_reg_base = SUNXI_RTWI_BRG_REG,
.gate_reg_offset = TWI_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = SUNXI_RTWI_BRG_REG,
.rst_reg_offset = TWI_DEFAULT_CLK_RST_OFFSET(0),
.parent_clk = 24000000,
},
}
#define SUNXI_RTWI_BRG_REG
Definition reg-ncat.h:61
#define SUNXI_RTWI_BASE
Definition reg-ncat.h:58
@ GPIO_PORTL
Definition sys-gpio.h:50
@ GPIO_PERIPH_MUX2
Definition sys-gpio.h:22
#define GPIO_PIN(x, y)
Definition sys-gpio.h:66
@ SUNXI_R_I2C0
Reserved I2C device 0.
Definition sys-i2c.h:71
#define TWI_DEFAULT_CLK_GATE_OFFSET(x)
Definition sys-i2c.h:135
#define TWI_DEFAULT_CLK_RST_OFFSET(x)
Definition sys-i2c.h:134
@ SUNXI_I2C_SPEED_400K
400 kHz I2C speed.
Definition sys-i2c.h:55

◆ sdhci0

sunxi_sdhci_t sdhci0

◆ uart_dbg

sunxi_serial_t uart_dbg
Initial value:
= {
.id = 0,
.baud_rate = UART_BAUDRATE_115200,
.dlen = UART_DLEN_8,
.stop = UART_STOP_BIT_0,
.parity = UART_PARITY_NO,
.gpio_pin =
{
.gpio_tx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
.gpio_rx = {GPIO_PIN(GPIO_PORTB, 11), GPIO_PERIPH_MUX2},
},
.uart_clk =
{
.gate_reg_base = SUNXI_CCU_BASE + UART0_GAR_REG,
.gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0),
.rst_reg_base = SUNXI_CCU_BASE + UART0_GAR_REG,
.rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0),
},
}
#define SUNXI_UART0_BASE
Definition reg-ncat.h:32
#define SUNXI_CCU_BASE
Definition reg-ncat.h:18
#define UART0_GAR_REG
Definition reg-ccu.h:1388
@ UART_STOP_BIT_0
Definition sys-uart.h:41
@ UART_BAUDRATE_115200
Definition sys-uart.h:24
#define SERIAL_DEFAULT_PARENT_CLK
Definition sys-uart.h:99
#define SERIAL_DEFAULT_CLK_RST_OFFSET(x)
Definition sys-uart.h:96
@ UART_PARITY_NO
Definition sys-uart.h:34
@ UART_DLEN_8
Definition sys-uart.h:50
#define SERIAL_DEFAULT_CLK_GATE_OFFSET(x)
Definition sys-uart.h:97
@ GPIO_PORTB
Definition sys-gpio.h:40