board.c File Reference

#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
#include <log.h>
#include <common.h>
#include <reg-ncat.h>
#include <sys-clk.h>
#include <mmu.h>
#include <mmc/sys-sdhci.h>
#include <sys-dram.h>
#include <sys-gpio.h>
#include <sys-i2c.h>
#include <sys-sid.h>
#include <sys-spi.h>
#include <sys-uart.h>

Include dependency graph for board.c:

Enumerations
enum	dram_training_type { DRAM_TRAINING_OFF = 0x60 , DRAM_TRAINING_HALF = 0x860 , DRAM_TRAINING_FULL = 0xc60 }

Functions
void	neon_enable (void)
void	gicr_set_waker (void)
void	clean_syterkit_data (void)
void	rtc_set_vccio_det_spare (void)
void	set_rpio_power_mode (void)
int	sunxi_nsi_init (void)
void	enable_sram_a3 ()
void	show_chip ()

Variables
sunxi_serial_t	uart_dbg
sunxi_serial_t	uart_dbg_1m5
sunxi_dma_t	sunxi_dma
sunxi_spi_t	sunxi_spi0
sunxi_sdhci_t	sdhci0
sunxi_sdhci_t	sdhci2
sunxi_i2c_t	i2c_pmu
const uint32_t	dram_para [32]
const char *	dram_para_name [2]

Enumeration Type Documentation

dram_training_type

enum dram_training_type

Enumerator
DRAM_TRAINING_OFF
DRAM_TRAINING_HALF
DRAM_TRAINING_FULL

Function Documentation

clean_syterkit_data()

void clean_syterkit_data

(

void

)

enable_sram_a3()

void enable_sram_a3

(

)

gicr_set_waker()

void gicr_set_waker

(

void

)

neon_enable()

void neon_enable

(

void

)

rtc_set_vccio_det_spare()

void rtc_set_vccio_det_spare

(

void

)

set_rpio_power_mode()

void set_rpio_power_mode

(

void

)

show_chip()

void show_chip

(

)

sunxi_nsi_init()

int sunxi_nsi_init

(

void

)

Variable Documentation

dram_para

const uint32_t dram_para[32]

dram_para_name

const char* dram_para_name[2]

Initial value:

= {
        "dram_para00",
        "dram_para24",
}

i2c_pmu

sunxi_i2c_t i2c_pmu

Initial value:

= {
        .base = SUNXI_RTWI_BASE,
        .id = SUNXI_R_I2C0,
        .speed = SUNXI_I2C_SPEED_400K,
        .gpio =
                {
                        .gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX2},
                        .gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX2},
                },
        .i2c_clk =
                {
                        .gate_reg_base = SUNXI_RTWI_BRG_REG,
                        .gate_reg_offset = TWI_DEFAULT_CLK_GATE_OFFSET(0),
                        .rst_reg_base = SUNXI_RTWI_BRG_REG,
                        .rst_reg_offset = TWI_DEFAULT_CLK_RST_OFFSET(0),
                        .parent_clk = 24000000,
                },
}

sdhci0

sunxi_sdhci_t sdhci0

sdhci2

sunxi_sdhci_t sdhci2

sunxi_dma

sunxi_dma_t sunxi_dma

Initial value:

= {
        .dma_reg_base = SUNXI_DMA_BASE,
        .bus_clk =
                {
                        .gate_reg_base = CCU_BASE + CCU_MBUS_MAT_CLK_GATING_REG,
                        .gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
                },
        .dma_clk =
                {
                        .rst_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
                        .rst_reg_offset = DMA_DEFAULT_CLK_RST_OFFSET,
                        .gate_reg_base = CCU_BASE + CCU_DMA_BGR_REG,
                        .gate_reg_offset = DMA_DEFAULT_CLK_GATE_OFFSET,
                },
}

sunxi_spi0

sunxi_spi_t sunxi_spi0

Initial value:

= {
        .base = SUNXI_SPI0_BASE,
        .id = 0,
        .clk_rate = 75 * 1000 * 1000,
        .gpio =
                {
                        .gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4},
                        .gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4},
                        .gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4},
                        .gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4},
                        .gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4},
                        .gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4},
                },
        .spi_clk =
                {
                        .spi_clock_cfg_base = CCU_BASE + CCU_SPI0_CLK_REG,
                        .spi_clock_factor_n_offset = SPI_CLK_SEL_FACTOR_N_OFF,
                        .spi_clock_source = SPI_CLK_SEL_PERIPH_300M,
                },
        .parent_clk_reg =
                {
                        .rst_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
                        .rst_reg_offset = SPI_DEFAULT_CLK_RST_OFFSET(0),
                        .gate_reg_base = CCU_BASE + CCU_SPI_BGR_REG,
                        .gate_reg_offset = SPI_DEFAULT_CLK_GATE_OFFSET(0),
                        .parent_clk = 300000000,
                },
        .dma_handle = &sunxi_dma,
}

uart_dbg

sunxi_serial_t uart_dbg

Initial value:

= {
        .base = SUNXI_UART0_BASE,
        .id = 0,
        .baud_rate = UART_BAUDRATE_115200,
        .dlen = UART_DLEN_8,
        .stop = UART_STOP_BIT_0,
        .parity = UART_PARITY_NO,
        .gpio_pin =
                {
                        .gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
                        .gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
                },
        .uart_clk =
                {
                        .gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
                        .gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0),
                        .rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
                        .rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0),
                        .parent_clk = SERIAL_DEFAULT_PARENT_CLK,
                },
}

uart_dbg_1m5

sunxi_serial_t uart_dbg_1m5

Initial value:

= {
        .base = SUNXI_UART0_BASE,
        .id = 0,
        .baud_rate = UART_BAUDRATE_1500000,
        .dlen = UART_DLEN_8,
        .stop = UART_STOP_BIT_0,
        .parity = UART_PARITY_NO,
        .gpio_pin =
                {
                        .gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2},
                        .gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2},
                },
        .uart_clk =
                {
                        .gate_reg_base = CCU_BASE + CCU_UART_BGR_REG,
                        .gate_reg_offset = SERIAL_DEFAULT_CLK_GATE_OFFSET(0),
                        .rst_reg_base = CCU_BASE + CCU_UART_BGR_REG,
                        .rst_reg_offset = SERIAL_DEFAULT_CLK_RST_OFFSET(0),
                        .parent_clk = SERIAL_DEFAULT_PARENT_CLK,
                },
}